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Messages from 25150

Article: 25150
Subject: Re: Looks like Xilinx is at it again!
From: "Gary Watson" <gary2@nexsan.com>
Date: Mon, 28 Aug 2000 21:28:34 +0100
Links: << >>  << T >>  << A >>
Well, Xilinx has welcomed me back to using their parts by sending me an
email denying access to the web-based tech support service which is
advertised for Foundation 3.1i.  The reason given is that I'm not in the USA
or Canada (which is doubly annoying since I am American; I just happen to
have started a company in the UK).

Thus far, from the installation process to this latest insult, I am having a
uniformly negative experience with Foundation 3.1i.

--

Gary Watson
gary2@nexsan.com
Nexsan Technologies Ltd.
Derby DE21 7BF  ENGLAND
http://www.nexsan.com


"Ray Andraka" <ray@andraka.com> wrote in message
news:39A15F1A.5321452@andraka.com...
> Hey folks, has anyone tried to get support from xilinx lately for 3.1?
They've
> now got a web page you have to log into to get support.  All well and good
if it
> worked I suppose.  Thing is I've registered several times now.  For
registering
> you get an autogenerated note back saying it will take a day to grant
access to
> websupport.  THing is even after two weeks it still gives you the new
> registration page when you log in (frustrating part is it fills in all the
> blanks except the registration code, so I'm already there in the data
base).
> Used to be you could submit a case directly without this crap.  No more
though.
> Now we have to waste more time dealing with stupidity to get legitimate
issues
> on registered and licensed software resolved.  I suppose this is par for
the
> course in the trend to make the tools and support more customer
unfriendly.
> Whoever came up with this farce ought to be taken out back and shot.
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com


Article: 25151
Subject: Re: Large amout of Interconnect between FPGAs
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 28 Aug 2000 19:00:39 -0400
Links: << >>  << T >>  << A >>
I am not board layout engineer, but one rule that should always work to
give you good signals on a board trace is to use very short point to
point traces. The round trip delay is about 1 nS per foot. With a edge
time of .5 to 1 nS the round trip time needs to be less than this. So
you get about 3 to 4 inches of trace as a maximum before you need to
worry about terminations, etc. 

But you will want to be concerned with ground bounce with the central
chip with 512 IOs. This can be a real problem if the fast edge rates are
turned on. 


Steven DeLong wrote:
> 
> I have an application that requires the connection of a large amount of
> I/O between multiple FPGAs on a single PCB. The application requires one
> type of device to fan in/out to 8 each of a second type of device. Each
> connection requires about 6.4 Gbit of bandwidth in each direction.
> 
> One connection scheme could use two 32 bit buses (one bus in each
> direction) between each of the eight devices and the one device. The bus
> bits would each run at 200 Mb/s. That's 64 single ended
> drivers/receivers on each of the eight devices and 512 single ended
> drivers/receivers on the other device.
> 
> Does anyone have any experience with anything similar to the above
> and/or large amounts of high-speed interconnect between chips? What type
> of I/O was used (LVTTL, LVDS, HSTTL, etc.) What, if any type of
> terminations were used? Any other suggestions?
> 
> I would like to avoid external terminations and reduce as much as
> possible the number of physical routes between the devices because of
> PCB real estate limitations.

When you say you want to minimize the *number* of routes between
devices, how can this be done since you have already defined the number
of signals? I don't understand what you are asking here. 

Of course if you wanted to use LVDS, you would need 128 IOs on the 8
chips and 1024 IOs on the central chip. I am not sure if a chip this
large is made. Can you change your topology to minimize the IOs on the
central chip? Can it be split into multiple parts in any manner such as
in a bit slice of 16 bits each?


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 25152
Subject: Re: availability of Spartan II
From: bob_42690@my-deja.com
Date: Tue, 29 Aug 2000 00:39:46 GMT
Links: << >>  << T >>  << A >>


>
> Just a little nudge. Were you still trying to get a realistic
> availability answer? I at the very least am very interested in the
> answer.
>

FYI
I think Peter went away on vacation or something because
on 8-25-00, Peter replied in another thread

"Peter Alfke's personal opinions.
I'll read the flames in 3 weeks."




Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25153
Subject: Re: Non-disclosures in job interviews, Round One
From: Jon Kirwan <jkirwan@easystreet.com>
Date: Mon, 28 Aug 2000 18:34:39 -0700
Links: << >>  << T >>  << A >>
On Fri, 25 Aug 2000 19:22:18 -0700 (PDT), "Matthew S. Staben"
<mstaben@poboxes.com> wrote:

>A legal document ultimately is tested in a court of law.  It is unfortunate that these 
>days, with the apparent ignorance exhibited by the Lawmakers (eg. UCITA) this 
>buffer may not offer much comfort.  Even so, signing a NDA for an interview seems 
>at worst to me a non-enforceable agreement.  There is no paperwork, tax 
>document, employment record, whatever, of the person being interviewed; just the 
>NDA being the sole document that proves the interviewee was ever present.  And 
>because of the lack of supporting evidence, there is no case.  If any of you out 
>there can think of a situation where a certain judgement would be entered against 
>the NDA-violating defendant, I'd like to hear about it.

One problem I've observed is the feelings that some folks have over
them.  I discussed a recent case where a company had an NDA in hand
that they believed allowed them power they didn't frankly have.  In
the process of trying to force the issue, they demolished important
relationships that they needed.

The court never got involved.  But bad feelings abounded over little.


>I'm also of the opinion that a non-specific NDA would have less legal ground than 
>one that is specific.

This is my exact sense, as well.

<snip>

Jon
Article: 25154
Subject: Re: Vacancy at European Space Agency
From: Regis Caillet <regis.caillet@imt.unine.ch>
Date: Tue, 29 Aug 2000 09:06:17 +0200
Links: << >>  << T >>  << A >>
jgais@ws.estec.esa.nl wrote:

> OK folks, if anyone ever wanted my job - here is your chance!
>
> I will be leaving ESA by the end of the year to pursue a
> mixed academic/consulting career, and we need some talented
> person to replace me. The vacancy notice can be found at:
>
> http://www.esa.int/hr/VN/281.html
>
> Feel free to contact me if you need more information.
> Note that only citizens from the ESA member states can
> be considered.
>
> For those of you interested in the LEON project: don't
> worry, I will be continuing working on it as before. We
> are now testing the new AMBA version and next release is
> expected in September.
>
> Regards, Jiri Gaisler.
>
> ---------------------------------------------------------------------
> Jiri Gaisler, ESA/ESTEC, Box 299, 2200 AG Noordwijk, the Netherlands
> email: jgais@ws.estec.esa.nl voice:+31-71-5654880  fax:+31-71-5654295
> ERC32 home page at http://www.estec.esa.nl/wsmwww/erc32
> LEON home page at http://www.estec.esa.nl/wsmwww/leon
> ---------------------------------------------------------------------

why you go away ?

Regis Caillet

Article: 25155
Subject: Re: Problems Fitting Design When Inserting More Than One Internal Global Buffer...
From: "Christian Reithmeier" <Christian.Reithmeier@elca.de>
Date: Tue, 29 Aug 2000 11:23:52 +0200
Links: << >>  << T >>  << A >>

Nestor <nestor@ece.concordia.ca> wrote in message
news:7pwp5.187831$Gh.3453711@news20.bellglobal.com...
> Hi everyone.
>
>       I have written a vhdl design which I cannot fit in an Altera
> flex10k100a-1 because of limited or problematic internal global signal
> resources (I believe).

Hi Nestor,

I think I had the same problem with my design and this version of MAX+plus
II.
Using an LCELL in front of the output-pin helped me to fix it.


Christian Reithmeier
El Camino GmbH
http://www.elca.de



Article: 25156
Subject: Using a FPGA as I/O expansion on embedded PC ??
From: "Tim Hove" <info@polygonpower.com>
Date: Tue, 29 Aug 2000 09:54:02 GMT
Links: << >>  << T >>  << A >>
Hi All
I'm a software developer with a little hardware problem. An An embedded
computer we had ordered from a private konsultant is newer gonna show.
Therefore I'm looking for a replacement with specification that won't force
us to change the current design dramaticly. For this purpose I need an
embedded PC using a FPGA as I/O expansion. Does anyone know if such a
product exists??
Further; how big a FPGA  would  I have to get to run a SPI Bus??.
In case you can't tell, I don't know much about FPGA's.
Any help is very welcome.

Tim




Article: 25157
Subject: Re: Using a FPGA as I/O expansion on embedded PC ??
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Tue, 29 Aug 2000 22:09:47 +1200
Links: << >>  << T >>  << A >>
Tim Hove wrote:
> 
> Hi All
> I'm a software developer with a little hardware problem. An An embedded
> computer we had ordered from a private konsultant is newer gonna show.
> Therefore I'm looking for a replacement with specification that won't force
> us to change the current design dramaticly. For this purpose I need an
> embedded PC using a FPGA as I/O expansion. Does anyone know if such a
> product exists??
> Further; how big a FPGA  would  I have to get to run a SPI Bus??.

 If you mean as a slave, a 16V8 will do it, that's a SPLD, not a FPGA.

 If you want a SPI host, then anything from a 24 pin ATF750 upwards
will do - still in SPLD territory.

 Even the smallest FPGA will allow a very complex SPI bus - you 
could configure BIT clock, Active edges, Master/Slave, Noise 
filtering, Shift lengths, and even shift FIFOs, all as SOFT
options.

 If you just want IO, then a CPLD will have a much lower cost/pin than
a FPGA.

 We have done many designs for PLDs as I/O expansion, and even have
our own protocal, SPL, that can be implemented on SPI hardware.

- jg

======= 80x51 Tools & PLD Specialists  =========
= http://www.DesignTools.co.nz
Article: 25158
Subject: Spurious errors in full FPGA?
From: nds@iee.et.tu-dresden.de (Norman Desal)
Date: 29 Aug 2000 10:10:30 GMT
Links: << >>  << T >>  << A >>
Hi,

I have run into a problem in a design using a XC95108 by XILINX.

This is a design including a simple I2C-Slave and some registers for 
demultiplexing a 8bit data stream to a 16bit wide.

I'm encountering faults in the function of the circuit which depend
on the existence or nonexistence of test connections in the FPGA, i.e.
the FPGA doesn't work, I put a test connection to an IOB and (voila) 
the circuit works. But not without the test connection.

I'm not sure what the cause for this behaviour may be. The circuit
is quite full, i.e. 102 of 108 Macrocells are used, some of them 
obviously for routing. I suspect a problem with clock skew, but the 
design is completely synchronous and the clock frequency is quite low.

Could some friendly soul give me some hints?

Thanks,

Norman
Article: 25159
Subject: Re: run time doubled with Xilinx 3.1i upgrade
From: erika_uk@my-deja.com
Date: Tue, 29 Aug 2000 13:44:13 GMT
Links: << >>  << T >>  << A >>
hey,

what's FE_SHELL?
why many users prefer to use script file command?
why PERL ?

can someone explain me the benefits from doing so ?

regards

--Erika



In article <39A535EA.43A26B98@free-ip.com>,
  davidk@free-ip.com wrote:
> Vikram Pasham wrote:
> > In the make file you can use
> > "set_pad_register" constraint to use IOB registers. The syntax for
using this constraint is
> >
> > set_pad_register TRUE  net_name
> >
> > You can do a "man" on this constraint in FE_SHELL to get all the
details.
>
> I did some investigation yesterday on FE_SHELL commands and ran
> across the one you mention.  What I didn't like about that is
> the number of net names that I would have to do that command on.
> The odds of missing one is huge.
>
> Instead, I created a FPGA Express constraint file and did the
> following command:
> 	import_constraint -file synth_constraints.exc
>
> The constraint file was essentially empty with the exception of
setting
> the default value for IOFF's to TRUE.  This seems to have worked.
>
> Now I can correctly compile my code, I can give some preliminary
> results.
>
> Under F2.1i+SP6, on a Spartan-II 50k gate -5 speed grade:
> 	736 Slices (96%), 101 MHz, approx 10 minutes for PAR.
>
> Same as above, but on F3.1i+SP2:
> 	699 Slices (91%), 102.5 MHz, approx 25 minutes for PAR.
>
> So I can say, with certainty, that run times have more than
> doubled for _THIS_ design, but with marginal improvements in
> speed and size.
>
> Ray A.:  No floorplanning.  Just VHDL with a basic *.UCF.
>
> David Kessner
> davidk@free-ip.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25160
Subject: Re: availability of Spartan II
From: sulimma@my-deja.com
Date: Tue, 29 Aug 2000 14:12:16 GMT
Links: << >>  << T >>  << A >>
In article <39A55CB3.E20DEB8A@xilinx.com>,
  peter.alfke@xilinx.com wrote:
> Simon is of course right, in general. But Spartan-II is a special
case:
> It is derived from "good old Virtex", which has been around for well
over a
> year.
> From a software point ov view, there is no big difference. The
speedsfile
> numbers differ, there is no temp-measuring diode in Spartan-II, and,
perhaps
> most importantly for your projects, the packages differ. And
Spartan-II extends
> the Virtex family downwards to '30 and '15, devices that will never
exist in
> Virtex.
> "Besides that..." there is no difference. So you can definitely start
the
> software portion of your design without any worry. I have tried to get
a
> realistic availability answer out of Spartan marketing. Let's see.
>
> Peter Alfke, Xilinx Applications
> ============================
> "S. Ramirez" wrote:

How about partial reconfiguration? It is not mentioned in the spartan-II
datasheet? (unless I am blind)

Is it supported anyway?

Kolja Sulimma


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 25161
Subject: Anyone used Spartan II XC2S200 yet?
From: "K. Mori" <mori.kevin@NOJUNKsicom.com>
Date: Tue, 29 Aug 2000 08:05:33 -0700
Links: << >>  << T >>  << A >>
We've completed a board design aimed at using the Spartan II 200 (pq208).
That's all well and good except that there are no BSDL files for the 200 part!
We're using Alliance 3.1i with service pack 2.
To debug this in the state the board is in now, we need to use jtag programming.
Has anyone successfully programmed the XC2S200 part with JTAG?
If so let me know how you did it.  We've tried using BSDL files from other
similar devices but I assume it doesn't work because the die pads and cells are
numbered differently between devices.  BTW, if you do a "Init Chain" command
it comes back saying it's a Virtex 200 part.

Thanks,
Kevin
(remove "NOJUNK" from address for reply)
Article: 25162
Subject: Re: run time doubled with Xilinx 3.1i upgrade
From: David Kessner <davidk@free-ip.com>
Date: Tue, 29 Aug 2000 09:13:16 -0600
Links: << >>  << T >>  << A >>
erika_uk@my-deja.com wrote:
> what's FE_SHELL?
> why many users prefer to use script file command?
> why PERL ?
> 
> can someone explain me the benefits from doing so ?

Your questions touch on a fundamental problem with Xilinx Foundation,
and to a lesser extent all other FPGA development tools.  And that
problem is that the standard graphical user interface (I.E., Project
Manager) is _almost_ useless for any serious project.  You can use
Project Manager's GUI for serious projects, but there are huge
benefits for dumping it in favor of another way.

This is one of those "don't get me started" topics that I could
rant on for hours on how brain dead the GUI is.  If you really
want to know, then send me a private email.  Suffice it to say
that using something else is more flexible and powerful.

So on to your questions...

> what's FE_SHELL?

FE_SHELL stands for, I think, FPGA Express Shell.  Practically
speaking it is a way to run the synthesis process from a command
line or script.  From the command line, or a makefile, you run
FE_SHELL and give it the filename for your script.  FPGA Express
will then run your script and do the synthesis process.

> why many users prefer to use script file command?
> why PERL ?

The "typical" way to not use Project Manager is to use a makefile,
along with the make utility.  Make is a standard tool that has been
used in the software world for at least 25 years (maybe 35 years!). 
In a makefile you list many rules for building your software
executable, or in our case our FPGA bitfile.  

What makes a makefile powerful is that it can run other programs
to complete a step.  In software, it will run a C compiler, or a
linker.  In hardware it can run FPGA Express, or PAR.  Makefiles
do have their limitations, but that's where other tools really 
help.

One thing you might want to do in your make process is after PAR
you'd want to look at the timing report file and see if you met all
timing constraints.  If your constraints were not met you might want
to rerun PAR with a different cost table.  The make utility doesn't
have the ability to scan through an arbitrary file (like the timing
report file) and look for specific things.  But other programs, like
Perl, can.  So some people use other programs like Perl to do things 
that the standard make cannot.  


> can someone explain me the benefits from doing so ?

Here are some benefits:

	1.  You can use a true revision control system that isn't
	    severely broken (I.E., Foundation 2.1i and maybe 3.1i).
	2.  You can more easily do things (like rerun PAR based on
	    your timing results).
	3.  You can generate multiple FPGA's at one time.  This is 
	    useful if you have _almost_ the same FPGA go into two
	    different boards-- for example:  a newer version of the
	    PCB has a faster speed grade, different pinouts, added
	    logic, etc.  You don't have to manually create all
	    variations.
	4.  You can automatically run core generation programs,
	    like the NCO core in the Free-LIB1 package or the 
	    microcode generation program in the Free-6502 core
	    (available at http://www.free-ip.com :).
	5.  More seamless integration with simulators and non-FPGA
	    related programs.
	6.  Less error-prone and "labor intensive" compiling.

Hope that helps!

David Kessner
davidk@free-ip.com
Article: 25163
Subject: Re: largest fpga in the industry
From: Jerry English <jenglish@planetc.com>
Date: Tue, 29 Aug 2000 11:20:40 -0400
Links: << >>  << T >>  << A >>
I checked the distributors inventory over the web and found one that quoted prices on
the
XCV3200E. YEE-OUCH!!! $6K to $8K 1 to 24. I don't mind paying $6K for a few
devices in order to shake the bugs out of the system but these prices pretty much
exclude the
XCV3200E from any sort of production application. Even if the price dropped by two
orders
of magnitude as quantities approached 25K, it just doesn't compete with the price of
an ASIC.
I did notice that Xilinx provides a path
for the Spartan family that allows the design to be converted to a hard wired ASIC. Is
that
option available for the XCV3200E?

I know this is somewhat off thread but it seem appropriate to bring it up. If the
pricing of the
XCV3200E remains in the stratosphere then I believe its doomed to be nothing more than
a
ASIC breadboard.

regards
Jerry

Peter Alfke wrote:

> Let me describe the biggest FPGA that Xilinx is shipping now ( and I mean shipping
> today to paying customers ):
>
> The Virtex XCV3200E has a 104 x 156 array of CLBs. That makes it 16,224 CLBs, each
> with four Logic Cells. That means there are 64,896 Logic Cells, each consisting of
> a 4-input look-up table plus a flip-flop.
> You can use each LUT as either logic (ROM), as 16-bit RAM, or as 16-bit shift
> register. ( Altera can use the LUT only as logic (ROM).
>
> Independent of these CLBs, there are 208  BlockRAMs, each with 4096 bits and two
> completely independent access mechanisms ( true dual-ported). That makes it
> 851,968 bits of RAM, not counting the RAMs in the LUTs.
>
> I am sure that this is bigger than Altera's biggest device.
> This is today's situation. next year, there will be significantly larger devices
> from Xilinx.
> But the question was: What's shipping today? Answer: the XCV3200E.
>
> The numbers above are honest engineering numbers, no smoke or mirrors.  All the
> other goodies, like multiplexers, carry logic, digital delay-locked loops, and
> versatile I/Os are not counted, they are "free".
>
> Peter Alfke, Xilinx Applications
> ===============================
> Ray Andraka wrote:
>
> > That should be reasonably easy to compare, at least relative to other marketing
> > parameters.  I think right now that honor goes to the Altera APEX EP20K1500E.
> > That metric, however isn't really all that useful.  If you just want memory
> > without regard to the logic capabilities, then why not just use memory.  Xilinx
> > devices have the ability to use the CLBs as memory as well as the block RAMs.
> > That, and the cell structure can make a xilinx design occupy less than half the
> > LUTs of an equivalent designin ALtera.  Given equal number of LUTs, that could
> > be an awful lot of distributed RAM cells which could tip the balance the other
> > way.  In evaluating a part, you really need to look at the whole picture,
> > including the tools and how they fit into your purchasing plans.
> >
> > yorams70@my-deja.com wrote:
> > >
> > >         Hi.
> > > I would like to know what is the largest fpga in the industry in
> > > terms of internal RAM. (and I mean RAM that it's usage will not
> > > come on the cost of logic cells use).
> > >
> > > ThankX,
> > > Yoram.
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com

Article: 25164
Subject: Re: availability of Spartan II
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 29 Aug 2000 08:21:03 -0700
Links: << >>  << T >>  << A >>

--------------14902931BBCDEE5D25870773
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Bob,

Just because Peter may be out enjoying his travels doesn't mean there
isn't someone watching the store.

I just visited with those who know, and Spartan II is sampling in all
but a couple of parts, and production orders with reasonable leadtimes
are being taken now on most parts, and shipping.

There should be a means of checking your design in any part size because
of the overlap with Virtex, and the shared architecture.  At the worst,
the design may have to be recompiled with a newer speeds file when it
arrives.

I was a "user" of Xilinx parts for 15 years before joining Xilinx.  I
agree that I want a piece of silicon in my hand before I commit to any
new design.  Its OK for it to be an ES (engineering sample) part, as I
know that Xilinx is committed to getting it into production ASAP barring
any natural disasters.  The track record of announcement, ES material
availability, and production availability is also important.

That is why it benefits no one to be dishonest about parts and
availability -- it is too easy to check out (just call distribution and
ask, or email Peter!!!).

Xilinx is committed to helping you get to market as fast as you possibly
can.

Please contact your distributor for details, as all part availability
and status is posted on the distributor information website.

Austin Lesea, IC Design FPGA Lab, Xilinx


bob_42690@my-deja.com wrote:

> >
> > Just a little nudge. Were you still trying to get a realistic
> > availability answer? I at the very least am very interested in the
> > answer.
> >
>
> FYI
> I think Peter went away on vacation or something because
> on 8-25-00, Peter replied in another thread
>
> "Peter Alfke's personal opinions.
> I'll read the flames in 3 weeks."
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

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<!doctype html public "-//w3c//dtd html 4.0 transitional//en">
<html>
Bob,
<p>Just because Peter may be out enjoying his travels doesn't mean there
isn't someone watching the store.
<p>I just visited with those who know, and Spartan II is sampling in all
but a couple of parts, and production orders with reasonable leadtimes
are being taken now on most parts, and <i>shipping</i>.
<p>There should be a means of checking your design in any part size because
of the overlap with Virtex, and the shared architecture.&nbsp; At the worst,
the design may have to be recompiled with a newer speeds file when it arrives.
<p>I was a "user" of Xilinx parts for 15 years before joining Xilinx.&nbsp;
I agree that I want a piece of silicon in my hand before I commit to any
new design.&nbsp; Its OK for it to be an ES (engineering sample) part,
as I know that Xilinx is committed to getting it into production ASAP barring
any natural disasters.&nbsp; The track record of announcement, ES material
availability, and production availability is also important.
<p>That is why it benefits no one to be dishonest about parts and availability
-- it is too easy to check out (just call distribution and ask, or email
Peter!!!).
<p>Xilinx is committed to helping you get to market as fast as you possibly
can.
<p>Please contact your distributor for details, as all part availability
and status is posted on the distributor information website.
<p>Austin Lesea, IC Design FPGA Lab, Xilinx
<br>&nbsp;
<p>bob_42690@my-deja.com wrote:
<blockquote TYPE=CITE>>
<br>> Just a little nudge. Were you still trying to get a realistic
<br>> availability answer? I at the very least am very interested in the
<br>> answer.
<br>>
<p>FYI
<br>I think Peter went away on vacation or something because
<br>on 8-25-00, Peter replied in another thread
<p>"Peter Alfke's personal opinions.
<br>I'll read the flames in 3 weeks."
<p>Sent via Deja.com <a href="http://www.deja.com/">http://www.deja.com/</a>
<br>Before you buy.</blockquote>
</html>

--------------14902931BBCDEE5D25870773--

Article: 25165
Subject: Re: largest fpga in the industry
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 29 Aug 2000 15:36:42 GMT
Links: << >>  << T >>  << A >>
In article <39ABD4C8.8D2B63F2@planetc.com>,
Jerry English  <jenglish@planetc.com> wrote:

> I checked the distributors inventory over the web and found one that
> quoted prices on the XCV3200E. YEE-OUCH!!! $6K to $8K 1 to 24. I
> don't mind paying $6K for a few devices in order to shake the bugs
> out of the system but these prices pretty much exclude the XCV3200E
> from any sort of production application. Even if the price dropped
> by two orders of magnitude as quantities approached 25K, it just
> doesn't compete with the price of an ASIC.  I did notice that Xilinx
> provides a path for the Spartan family that allows the design to be
> converted to a hard wired ASIC. Is that option available for the
> XCV3200E?

	The price isn't suprising, considering the die size (25 x 25mm
in a .18uM process).  The suprising part is that it can be built at
ALL, with any sort of yeild.  I don't think the part is intended for
any market where prices are key, but where time-to-market is the key.
If you are selling a $100k box, but you need to sell it TODAY, then
you throw something like the XCV3200E at the problem.

	Remember, to some people, a 2x capacity FPGA is more than 2x
the value of the previous size, because the bisection bandwidth within
the FPGA is much much larger than 2 separate, smaller arrays.
SOMEBODY must buy these things for Xilinx to bother manufacturing
them.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 25166
Subject: Re: largest fpga in the industry
From: Ray Andraka <ray@andraka.com>
Date: Tue, 29 Aug 2000 17:36:28 GMT
Links: << >>  << T >>  << A >>
Cisco.

True the big devices are $$$, but then it wasn't that long ago a 4025E-2 was
over $2K.  Still, those biggies have a home in low volume High cost applications
like cellular base stations, DOD stuff, R&D and of course ASIC prototyping.

"Nicholas C. Weaver" wrote:
> 
> In article <39ABD4C8.8D2B63F2@planetc.com>,
> Jerry English  <jenglish@planetc.com> wrote:
> 
> > I checked the distributors inventory over the web and found one that
> > quoted prices on the XCV3200E. YEE-OUCH!!! $6K to $8K 1 to 24. I
> > don't mind paying $6K for a few devices in order to shake the bugs
> > out of the system but these prices pretty much exclude the XCV3200E
> > from any sort of production application. Even if the price dropped
> > by two orders of magnitude as quantities approached 25K, it just
> > doesn't compete with the price of an ASIC.  I did notice that Xilinx
> > provides a path for the Spartan family that allows the design to be
> > converted to a hard wired ASIC. Is that option available for the
> > XCV3200E?
> 
>         The price isn't suprising, considering the die size (25 x 25mm
> in a .18uM process).  The suprising part is that it can be built at
> ALL, with any sort of yeild.  I don't think the part is intended for
> any market where prices are key, but where time-to-market is the key.
> If you are selling a $100k box, but you need to sell it TODAY, then
> you throw something like the XCV3200E at the problem.
> 
>         Remember, to some people, a 2x capacity FPGA is more than 2x
> the value of the previous size, because the bisection bandwidth within
> the FPGA is much much larger than 2 separate, smaller arrays.
> SOMEBODY must buy these things for Xilinx to bother manufacturing
> them.
> --
> Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 25167
Subject: Re: largest fpga in the industry
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 29 Aug 2000 12:01:09 -0700
Links: << >>  << T >>  << A >>
Ray,

Love those 'low volume' base stations.

Let's see now, how many base stations do you need to cover, let's say, Europe?
Korea?  Japan?  Argentina?

For G3, at 1.8 GHz and 1.9 GHz, cells must be located frequently, more so than with
the 800 and 900 MHz AMPS and GSM systems.

Consumers are demanding higher bit rates, which necessitate even more closely spaced
base stations, and even more processing power for RAKE receivers.  The base
stations' costs are amortized over the number of subscribers and revenues they
provide.  Thus, a base station may never go to ASIC's, and yet may actually be a
high volume product.

Its a great time to be shipping the largest and fastest FPGAs,

Austin


Ray Andraka wrote:

> Cisco.
>
> True the big devices are $$$, but then it wasn't that long ago a 4025E-2 was
> over $2K.  Still, those biggies have a home in low volume High cost applications
> like cellular base stations, DOD stuff, R&D and of course ASIC prototyping.
>
> "Nicholas C. Weaver" wrote:
> >
> > In article <39ABD4C8.8D2B63F2@planetc.com>,
> > Jerry English  <jenglish@planetc.com> wrote:
> >
> > > I checked the distributors inventory over the web and found one that
> > > quoted prices on the XCV3200E. YEE-OUCH!!! $6K to $8K 1 to 24. I
> > > don't mind paying $6K for a few devices in order to shake the bugs
> > > out of the system but these prices pretty much exclude the XCV3200E
> > > from any sort of production application. Even if the price dropped
> > > by two orders of magnitude as quantities approached 25K, it just
> > > doesn't compete with the price of an ASIC.  I did notice that Xilinx
> > > provides a path for the Spartan family that allows the design to be
> > > converted to a hard wired ASIC. Is that option available for the
> > > XCV3200E?
> >
> >         The price isn't suprising, considering the die size (25 x 25mm
> > in a .18uM process).  The suprising part is that it can be built at
> > ALL, with any sort of yeild.  I don't think the part is intended for
> > any market where prices are key, but where time-to-market is the key.
> > If you are selling a $100k box, but you need to sell it TODAY, then
> > you throw something like the XCV3200E at the problem.
> >
> >         Remember, to some people, a 2x capacity FPGA is more than 2x
> > the value of the previous size, because the bisection bandwidth within
> > the FPGA is much much larger than 2 separate, smaller arrays.
> > SOMEBODY must buy these things for Xilinx to bother manufacturing
> > them.
> > --
> > Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

Article: 25168
Subject: Re: Anyone used Spartan II XC2S200 yet?
From: Scott Schlachter <scott.schlachter@xilinx.com>
Date: Tue, 29 Aug 2000 12:06:53 -0700
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
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The BSDL files for several more of the Spartan-II parts have recently been produced
in "Prelim" stage.  We will have more of the Spartan-II family BSDL files on the web
very soon, probably within the next day or two, including the XCS200 files, so
please stay tuned. (http://support.xilinx.com/support/sw_bsdl.htm).   As for the
"Init Chain" responding as a Virtex part, this was caused by an early die's IDCODE
being mislabeled, and this has since been fixed.
Regards,
-Scott Schlachter
 Xilinx - Systems Engineer

"K. Mori" wrote:

> We've completed a board design aimed at using the Spartan II 200 (pq208).
> That's all well and good except that there are no BSDL files for the 200 part!
> We're using Alliance 3.1i with service pack 2.
> To debug this in the state the board is in now, we need to use jtag programming.
> Has anyone successfully programmed the XC2S200 part with JTAG?
> If so let me know how you did it.  We've tried using BSDL files from other
> similar devices but I assume it doesn't work because the die pads and cells are
> numbered differently between devices.  BTW, if you do a "Init Chain" command
> it comes back saying it's a Virtex 200 part.
>
> Thanks,
> Kevin
> (remove "NOJUNK" from address for reply)

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Article: 25169
Subject: Spartan II vs. Virtex
From: "S. Ramirez" <sramirez@cfl.rr.com>
Date: Tue, 29 Aug 2000 19:50:23 GMT
Links: << >>  << T >>  << A >>
     Does anyone know the exact differences, hardware wise, between a
Spartan II and a Virtex?
     Peter mentioned earlier that there was a temperature diode difference
(no diode in Spartan II), but there's got to be more to it in order to
explain the cost differential.
-Simon Ramirez, Consultant
 Synchronous Design, Inc.


Article: 25170
Subject: Re: Spartan II vs. Virtex
From: nweaver@boom.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: 29 Aug 2000 20:05:02 GMT
Links: << >>  << T >>  << A >>
In article <3uUq5.2462$_8.341101@typhoon.tampabay.rr.com>,
S. Ramirez <sramirez@cfl.rr.com> wrote:
>     Does anyone know the exact differences, hardware wise, between a
>Spartan II and a Virtex?
>     Peter mentioned earlier that there was a temperature diode difference
>(no diode in Spartan II), but there's got to be more to it in order to
>explain the cost differential.

	My understanding is that the logic block was relayed out with
more of an emphasis on compactness over performance, so it is denser
in terms of CLBs/unit silicon area, but at a performance penalty.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu
Article: 25171
Subject: Re: run time doubled with Xilinx 3.1i upgrade
From: dan.hopper-N0SPAM@N0SPAM.ericsson.com (Dan Hopper)
Date: 29 Aug 2000 20:42:34 GMT
Links: << >>  << T >>  << A >>
On 28 Aug 2000 15:27:26 GMT, Dan Hopper <dan.hopper-N0SPAM@N0SPAM.ericsson.com> wrote:
>On Wed, 23 Aug 2000 08:26:45 -0600, David Kessner <davidk@free-ip.com> wrote:
>>I've seen multiple problems with 3.1i that I'm still trying to sort
>>out.  Some of the problems are:
>>
>>	- FF's not being put into IOB's when F2.1i successfully put 
>>	  them there (Spartan-II).  This was not fixed with SP2.
>
>Also, 3.1i was supposed to address the issue of tristate FFs not
>being placed in IOBs as directed.  It doesn't, unfortunately.

This in fact turned out to be a misunderstanding on my part of the
logic sense of the tri-state enable of the output buffer.  Whileas
the datasheet schematic implies to me that it is an active high
signal (labeled "OE" and no bubble), it is in fact active low. 
Poking around in FPGA Editor and paying more attention on the second
time around showed that the software was aware of it even if I
wasn't.

So recoding the HDL to use an active low enable was enough to get
3.1i to use the IOB tri-state FF.


As far as the original poster's issue - I thought this was also a
problem of mine until I realized it was simple harmless warnings
that 3.1i was spitting out that 2.1i kept to itself.  As it turns
out, my synthesis tool is flagging any eligible FF with the IOB
property, and relying on the P&R tools to decide which ones make it
to the IOB.  

So, for example, for one signal I have 8 FFs that are each reading
in a signal from an input pin, any one of which could be mapped as
an output FF in the IOB.  But clearly only one of the eight can be
mapped into the IOB - the rest must go into CLBs.  2.1i silently
did the right thing, but 3.1i complains (issues warnings) about each
of the 7 with the IOB true property set that must be placed into
CLBs.  The same number of FFs are being mapped into hardware, only
the presence of a boatload of warnings in 3.1i SP2 is different.

Dan
Article: 25172
Subject: Re: Spartan II vs. Virtex
From: Marc Baker <marc.baker@xilinx.com>
Date: Tue, 29 Aug 2000 13:57:00 -0700
Links: << >>  << T >>  << A >>
The only significant architectural difference is that Spartan-II has power
down pins in place of the Virtex temperature diode.  The cost savings are
mostly in the back end, using a more advanced process than the original Virtex
family and different packages.  The Spartan-II family spans a different
density range than Virtex.  See the Xilinx web site for more information
(http://www.xilinx.com/products/spartan2/ask/architecture.htm).

"S. Ramirez" wrote:

>      Does anyone know the exact differences, hardware wise, between a
> Spartan II and a Virtex?
>      Peter mentioned earlier that there was a temperature diode difference
> (no diode in Spartan II), but there's got to be more to it in order to
> explain the cost differential.
> -Simon Ramirez, Consultant
>  Synchronous Design, Inc.

--
Marc Baker
Xilinx Applications
(408) 879-5375


Article: 25173
Subject: Xilinx and CD databooks (rant)
From: Victor the Cleaner <jonathan@the-gimp.canuck.com>
Date: 29 Aug 2000 22:14:48 GMT
Links: << >>  << T >>  << A >>
Rant or not, this is the right forum for it, and I can't believe
that this isn't a bigger issue across our industry.  What scares
me to death is the possibility that otherwise-intelligent people
who agree with me are keeping quiet because they're afraid of
being seen as "resistant to new technology", regardless of how
misplaced or misapplied that technology might be.  If you agree,
please circulate freely.

jl

(sent yesterday to databook@xilinx.com and Xilinx's CEO)

I don't know which semi-literate, multimedia-infatuated moron is
responsible for the so-called "databook on CD" I'm forced to deal
with right now, but you people had better get over it and get back
to paper.
  
I'm a career engineer, and having been in design for 20 years.  If
you think that makes me some kind of old fart who can't deal with
the Internet and new media, think again.  I was away from design for 
a couple of years while starting an Internet company, which I still 
operate, and we do work for some pretty big companies with pretty
modern content.  We also do some pretty challenging software R+D -
ask around and see if anyone you know has ever heard of an "Internet
company" with a Cray.
  
I got back into design a couple of years ago, though, and was disgusted
to discover the extent to which actual hard-copy data books had been 
replaced by CD distributions, most of them so badly implemented as to
be unusable.  I understand the positive motivations:  cheaper to produce
and distribute, more "environmentally friendly", etc., etc.
  
However, the downside is not worth it. 
  
I started designing with FPGAs (and learning VHDL) about a year ago,
choosing to use Xilinx because the quality of both the local support
(via Insight) and the data book were top-notch, and especially helpful
to a beginning user.  My first design (in Spartan) is now in production
and I'm working on new designs under Spartan II and Virtex that will  
be in production before the end of the year.
  
The problem, though, is that your 2000 "data book" is making it
increasingly difficult and frustrating to use your products.  Imagine
this:  You go to the tap to get a glass of water.  When you turn the
handle, though, you have to listen to a fifteen-second fanfare *before*
any water will come out the spigot.  It might be mildly amusing *once*,
but EVERY SINGLE TIME?  With no apparent way to disable it?  That's
how I look at the stupid blinking-boxes screen that opens your CD.
  
But that's just the beginning.  Your nagware then asks me (every single
time) whether I want to install your viewer, which I don't now, and likely
will never wish to.  I tried it once, and installing it took me down more
useless tangents than I wish to recall.  It asked me whether I wanted to
use the Internet.  Even though I indicated "No", it screwed with my
network settings anyway, turning off my modem and switching my connection
to a LAN, which I don't have at the location where I'm presently working -
that's why I'm using the modem.  Then it told me the databook was out of
date.  Then it told me my acrobat reader was out of date.  Then, when I
pretty much decided "fuck it" and wanted to start up my mailer to send you
this mail, I had to go screw with the network settings to restore the
modem connection broken by your viewer application.

In other words, the whole experience SUCKED, taking minutes to fail to
deliver the information that a real book would have delivered in SECONDS.

Now, it would be easy for you to misinterpret this mail and send my
complaints, out of context, to your Macromedia-happy multimedia developers
so that they might tweak and adjust out the the offending behaviours.  That
would be completely missing the point.  The point is that databooks on CD
DO NOT, and CAN NOT work as well as paper books.

"So", you say, "just print out the parts you want and don't use the CD."
That's just a really dumb thing to do, isn't it?  First, being a printer
isn't my job.  Printing your databook on an average laser printer would
result in a book on the order of 10 times the size of the paper version
you should be delivering.  My paper is 8.5x11, yours is 9x7.  My printer
is single-sided, you print double-sided.  I use heavy, thick bond paper,
you use much lighter stock.  All of which assumes, of course, that acroread,
the printer, and whatever other bits happen to be in the path, work properly
on every page and don't force me to go screw with resolution, etc.  But at
the end of the day, I'm a design engineer, and I shouldn't be wasting my
time printing an inferior version of the book it's your responsibility to
supply me with.

Are you starting to get the message?  I don't want blinking flashing splash
screens.  I don't want messages from the president.  I don't want propaganda
on your product line, and I sure as hell don't want spinning logos.  I was
in the virtual reality business in 91/92 when SIGGRAPH banned spinning logos,
so you can be sure there's nothing clever about them in the year 2000.

So how about getting with the ticket here, folks?  Intelligent, literate
designers don't want this crap.  They want books.  Books they can read in
bed and on the john.  Books they can scribble notes in.  Books they can take
along for a weekend *away* from the computers.  Books whose pages they can
flip back and forth between *infinitely* faster than they can with a
remarkably useless application like acroread (PDF?  Around here that stands
for "pedofiles").  Books for smart people.  
  
I look forward to your reply.

Jonathan Levine
Canada Connect Corp.
Calgary

Article: 25174
Subject: Re: Spartan II vs. Virtex
From: "Dan" <daniel.deconinck@sympatico.ca>
Date: Tue, 29 Aug 2000 22:16:34 GMT
Links: << >>  << T >>  << A >>
Are you saying the route resource/Logic ratio was decreased in Spartan II.
Thus making it more difficult to route your design in a Spartan II vs. a
similarly sized Virtex ?

Dan




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