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Messages from 24750

Article: 24750
Subject: Re: Non-disclosures in job interviews
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 13:49:58 -0400
Links: << >>  << T >>  << A >>
OneStone wrote:
> 
> rickman wrote:
> >
> > OneStone wrote:
> > > I do embedded systems, I'm mad. I work ludicrous hours, I drink caffeine
> > > and have the worlds most disturbed diet. I consider psychology and
> > > psychiatry one rung at least below witch doctors. I don't do psych
> > > tests, pee in bottles or sign anything to get an interview and neither
> > > should anyone else have to. At the end of the day there is a world wide
> > > shortage of good engineers so if they get too obnoxious with their tests
> > > they won't find many takers, and will end up the losers.
> >
> > If you have not been reading Ayn Rand, you should...
> >
> > Try "Atlas Shrugged".
> >
> > --
> >
> > Rick Collins
> >
> 
> Never heard of the author. Other than trade papers, tech manuals and
> scientific papers I like to keep my reading light. I presume from the
> "Atlas Shrugged" quote that the implication is that the employers don't
> care about my attitude, they are big enough not to bother, and will
> always find mugs who are prepared to compromise. Fine, let them employ
> mugs. Employ mugs, get coffee. Simple.
> 
> Al

Actually the book, "Atlas Shrugged", had as protagonists the people in
the world who "can" and as antagonists the people in the world who leach
off of the "doers". The rest of the world was just the huddled masses
caught in the middle. At one point the "doers" do a walk out abandoning
the companies and factories of the world and let it all go to ruin. 

At the time I was reading it, I thought it was a load of crap as all the
characters are very exaggerated and overdone. I did not even finish the
last quarter of the book. But over the years I have seen a lot of
reality in the "doer" vs. the "leach" concept. The "leaches" in the book
actually felt that the "doers" owed them not just a living, but a high
life!



-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24751
Subject: Re: Permanently programming FPGAs
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Thu, 17 Aug 2000 18:13:30 +0000
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> Ben Franchuk wrote:
--cut--
 > What I would like to see is a low cost development board
> > using Nonvol SRAM. The chips that look like core memory - on power
> > down they save to EEPROM and power up they restore to ram.
> > While the chips are slow 150ns and low density 64k bit they
> > would have the advantage for both programing FPGA's and use
> > as memory in CPU  designs. You load both sets of chips from
> > the host computer and then take your board off to use else where.
> > Ben.
> 
> What is the advantage of using such a nonvolatile SRAM chip over using
> an EEPROM or Flash? How does the SRAM add anything to the equation?

Well in my case I DON'T have EPROM programmer.
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Octal Computers:Where a step backward is two steps forward!"
 http://www.jetnet.ab.ca/users/bfranchuk/index.html
Article: 24752
Subject: Re: Board suggestion for high gate count FPGA board
From: Jerry English <jenglish@planetc.com>
Date: Thu, 17 Aug 2000 14:16:46 -0400
Links: << >>  << T >>  << A >>
Take a look at www.dini.com. They haave a pci board with
up to 6 xilinx virtex e series on it.



Starry Hung wrote:

> Hi,
>
> I am going to buy some prototyping boards with high gate count FPGA such
> as Xilinx Virtex or Altera APEX, and would like to hear more suggestions
> from you gurus. Xilinx or Altera? Which board is good? etc.
>
> Thanks,
>
> - starry.

Article: 24753
Subject: Re: Non-disclosures in job interviews
From: "Got Me Lucky Charms" <ggilbert@prsguitars.com>
Date: Thu, 17 Aug 2000 14:33:33 -0400
Links: << >>  << T >>  << A >>
I think you're right in many regards.
Discussing specific technical abilities does not always require the
discussion
of specific details of a project.  One can discuss ability in many specific,
say,
DSP areas, problem solving, knowledge, etc., without giving away the goose,
so to speak.
But, when a person comes into a company, there is always dangers of "leaky
employees"
who may not realize what they are saying, or marketing related info (product
plans,
timing, etc.) might be given away by accident.
Surely coordination is warranted.  However, there just plain old are some
specific piece of information that can sometimes be "piece together" by
the interviewee.  In my industry, by the pure nature of the interview
itself,
I know what they are up to.  Not necessarily with specific, but with enough
info
to put 2 and 2 together.  Just recently at a convention, I was introduced to
a company inquiring about my availability as a consultant.  Viola!  I knew
what they were trying to do.  There were only 2 basic possibilities.  A
5 minute, non-specific discussion, and I had it figured out.
Now, it's not in good taste for my to call up 3 of my best friends in the
world,
who happen to work at a competitor of these other folks, and unload.
That would allow that company to position themselves, and further weaken
the efforts of company A to get into an area.

So, I still hold by the argument that and NODE is not completely
inappropriate for
reasons even less benign than "direct collusion" or "direct disclosure".
Propriety goes beyond just technical propriety.

However, your point is well taken. And, I personally think it's best to heed
your
ideas when you are on the interviewer side of the table, especially.


rickman <spamgoeshere4@yahoo.com> wrote in message
news:399C22E8.D11DDF8F@yahoo.com...
> In every case I have come across there was nothing proprietary given to
> me at an interview. I just got back from an interview where I requested
> that they not use the NDA and not disclose information. It was not a
> problem. I got what I needed and they certainly were not limited in what
> they could ask me.
>
> You can talk in general about the need to discuss proprietary info, but
> there is seldom the case for it.
>
>
> "¸.·´¯`·.¸.·>Strings" wrote:
> >
> > I guess you've never had to protect your assets?
> > To say "stupid" is short-sighted.  Sorry.  There
> > are situations that warrant protection.
> >
> > Jon Kirwan <jkirwan@easystreet.com> wrote in message
> > > It's still stupid to sign one for an interview, in my opinion.
> > >
> > > Jon
>
> --
>
> Rick Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
>
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 24754
Subject: Re: state encoding in Synplify!!!
From: Andy Holt <andyh@ncity.ac.uk>
Date: Thu, 17 Aug 2000 19:43:41 +0100
Links: << >>  << T >>  << A >>


Peter Alfke wrote:
> 

> But it is inherently impossible to have a single-bit change in a state machine
> where, depending on control inputs, the code might jump in many ways.
> So, what's the meaning of a "Gray-encoded" state machine?

At first I thought you were wrong here and a similar technique to "one
hot" could be used with at most twice as many flip-flops as one hot
encoding, but a little analysis showed this is not so.

Considering the following mini state machine (only showing what
transitions can take place, not their conditions)

A -> B or C or D 
B -> C or D
C -> <who cares>
D -> <who cares>

Let us assume that there exists a Gray encoding for this state machine

Then A differs from each of B, C, D by one bit only.

For convenience consider A to be represented 111 (we can always choose
complements to ensure this)
then B,C,D have to be (in some order): 011, 101, 110 (i.e. the three
one-bit changes)
but then the change from B to C requires at least 2 bit changes.
Thus we do not have a Gray encoding

It might be possible to get round this by having multiple mappings for
each state but this would get so ridiculously messy as to defeat any
possible advantage in having a 1-bit state change.

Andy

Article: 24755
Subject: Re: Clock recovery in FPGA
From: oivan@my-deja.com
Date: Thu, 17 Aug 2000 19:11:01 GMT
Links: << >>  << T >>  << A >>
Unfortunately the bit rate of the data is 200MHz and I don't have
faster Clock available. Thanks!

In article <399C19F2.916ADE68@andraka.com>,
  Ray Andraka <ray@andraka.com> wrote:
> what is the bit rate of the stream, and what is the fastest clock you
have
> available?  The higher the ratio, the easier the job is.  Basically
you are
> looking at a DPLL (digital phase lock loop) design.  In simple terms,
the DPLL
> is for the most part a counter whose modulus is adjusted slightly if
the
> terminal count doesn't line up with the next bit edge.
>
> oivan@my-deja.com wrote:
> >
> > Hi,
> > Has anyone designed circuit that performs clock recovery from serial
> > data stream, in FPGA. I would appreciate any info.
> > Thanks.
> >
> > Sent via Deja.com http://www.deja.com/
> > Before you buy.
>
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 24756
Subject: Re: Xilinx design flow with Mentor
From: Laurent Gauch <laurent.gauch@aps-euro.com>
Date: Thu, 17 Aug 2000 15:18:38 -0400
Links: << >>  << T >>  << A >>
Use it now !

For me, that's the better flow for FPGA design !
And when you write your code, think "reuse". FPGA Advantage suite allows
the reuse.

Good work!
Laurent

Paul Smith a écrit :

> Hi all
>
> I'm new to Xilinx FPGAs, although I've done several Viewlogic schematic
> based Actel designs.
>
> I'm starting a design which should fit in a Xilinx Spartan II, either a
> XC2S30 or XC2S50.  I need to use the blockRAM in dual port mode.
>
> I have access to Mentor products, and would like to use mainly HDL,
> although I may want to enter some sections of the design as schematics.
>
> It looks like the Mentor FPGA Advantage suite (Renoir, ModelSim, and
> Leonardo) will work for me.  Anyone out there have experience with this
> toolset for the Spartan II target?
>
> I assume I also need the Xilinx Alliance software?
>
> TIA
>
> Paul Smith

Article: 24757
Subject: Re: Non-disclosures in job interviews
From: Jon Kirwan <jkirwan@easystreet.com>
Date: Thu, 17 Aug 2000 13:02:26 -0700
Links: << >>  << T >>  << A >>
On Thu, 17 Aug 2000 09:26:55 -0400, "¸.·´¯`·.¸.·>Strings"
<ggilbert@prsguitars.com> wrote:

>I guess you've never had to protect your assets?
>To say "stupid" is short-sighted.  Sorry.  There
>are situations that warrant protection.

I didn't say that the company was stupid.  And that there might be
situations where the company feels it must be that aggressive.  I just
won't cooperate.

An interviewee signing something they cannot possibly understand and
putting themselves in a potentially difficult "caught in the middle"
situation most likely is stupid to do so.  That's based on 30 years of
personal experience.

Jon

Article: 24758
Subject: Re: Clock recovery in FPGA
From: Muzaffer Kal <muzaffer@kal.st>
Date: 17 Aug 2000 20:26:07 GMT
Links: << >>  << T >>  << A >>
If you have no higher clock rate, it is very difficult without an
analog PLL. If you had samples at twice the data rate, you could do a
fully digital clock/data recovery based on detecting the phase error
and getting the correct data by interpolation. If you have no need for
equalization, you can do a DLL using semi-digital gates and do
correction directly but this requires very detailed floor planning on
an FPGA. This is how we solved USB2 data recovery problem.

oivan@my-deja.com wrote:

>Unfortunately the bit rate of the data is 200MHz and I don't have
>faster Clock available. Thanks!
>
>In article <399C19F2.916ADE68@andraka.com>,
>  Ray Andraka <ray@andraka.com> wrote:
>> what is the bit rate of the stream, and what is the fastest clock you
>have
>> available?  The higher the ratio, the easier the job is.  Basically
>you are
>> looking at a DPLL (digital phase lock loop) design.  In simple terms,
>the DPLL
>> is for the most part a counter whose modulus is adjusted slightly if
>the
>> terminal count doesn't line up with the next bit edge.
>>
>> oivan@my-deja.com wrote:
>> >
>> > Hi,
>> > Has anyone designed circuit that performs clock recovery from serial
>> > data stream, in FPGA. I would appreciate any info.
>> > Thanks.
>> >
>> > Sent via Deja.com http://www.deja.com/
>> > Before you buy.
>>
>> --
>> -Ray Andraka, P.E.
>> President, the Andraka Consulting Group, Inc.
>> 401/884-7930     Fax 401/884-7950
>> email ray@andraka.com
>> http://www.andraka.com  or http://www.fpga-guru.com
>>
>
>
>Sent via Deja.com http://www.deja.com/
>Before you buy.

Article: 24759
Subject: Re: Non-disclosures in job interviews
From: Marc Warden <marc.warden@att.net>
Date: Thu, 17 Aug 2000 22:06:10 GMT
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> I am not a lawyer, but I have, over the past 40 years, interviewed many
> hundreds of candidates.
> It would never occur to me to divulge secrets about my company's plans to
> an applicant. You just assume that he will talk to the competition, and may
> end up working there.
> So you try to assess his/her skills.
> There may be touchy cases, e.g. when a computer or semiconductor company
> would interview people with telecom experiences. They might draw the
> conclusion that Ithis company is interested in that market and has some
> plans there. But that's the risk the employer runs.
> But it would be irresponsible and dumb to divulge detailed product plans to
> a non-committed applicant.
>
> Peter Alfke

Yes, as someone else posted "excellent".

I too have interviewed job applicants and it is not for me to divulge sensitive
or proprietary information or ask the applicant to divulge the same.

And when I'm on the other side of the table, when I'm the person being
interviewed, I do not want to know any sensitive information and I do not leak
any proprietary or sensitive information about my current employeer and its
plans, products..

I don't think I've ever been asked to sign an NDA prior to being interviewed
and I don't think any of the job candidates I've interviewed have had to sign
an NDA before the interview.

Would I sign one? It depends. If I really knew I wanted to work for the company
and felt that it very unlikely that were I not to be offered a job, or if for
some reason I decided I didn't want to work for the company, and it very
unlikely that I would apply for and seek work at a company competing wtih the
company that was asking me to sign the NDA, I probably would. It also depends
upon how the NDA is presented, the tone and attitude with which it is presented
to me.

Sincerely,

 MarcW.


Article: 24760
Subject: Re: Non-disclosures in job interviews
From: Jon Kirwan <jkirwan@easystreet.com>
Date: Thu, 17 Aug 2000 16:23:37 -0700
Links: << >>  << T >>  << A >>
On Thu, 17 Aug 2000 13:43:40 -0400, rickman <spamgoeshere4@yahoo.com>
wrote:

>> In fact, a great way to handle the situation is to tell people that
>> you are interviewing with multiple companies.  The ball actually is in their
>> court
>> to not tell you too much stuff.  It MAY prevent an interview.  It should be
>> on paper.
>> That is the choice you make.  Oh well.  But it AIN'T THAT BAD.
>
>Sure you can shrug and sign. But company A was being so paranoid that
>they made *ALL* visitors of any type to sign an NDA in the visitor log.
>It would seem that they have a problem with not revealing "too much"
>stuff.
>
>Why would they do all this if they don't intend to enforce their actions
>in court?

I kind of wonder just how well a company can enforce an agreement that
is so routinely applied.  Technically, I believe it should be an
arrangement between two parties with a meeting of the minds.  But
asking everyone to routinely sign a standard document is rather
undirected.  And I wonder about that.

Jon
Article: 24761
Subject: Re: Non-disclosures in job interviews, Round One
From: peb@amleth.demon.co.uk ("Paul E. Bennett")
Date: Thu, 17 Aug 00 23:27:46 GMT
Links: << >>  << T >>  << A >>
In article <399BEE62.7E7F25A9@bittware.com>
           rhuizen@bittware.com "Ron Huizen" writes:

> It's hard to believe that with the major shortage of good
> engineers these days, that a company can treat potential new
> hires like that!  Man, if they treat you that way just for an interview,
> imagine what they might do to you if you're an actual employee!

I live three miles from a site where the visitor log contains an NDA 
clause and it is required that you sign to accept the terms as part of 
the condition of paying them a visit. It is, however, just because of 
the sort of site they are. I have no problem with their NDA statement 
as it is a fair one and works both ways.

In all of this you have to look at the client within the context of 
their business area and interests.

-- 
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-814586 .... see http://www.feabhas.com for details.
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************

Article: 24762
Subject: Re: Non-disclosures in job interviews
From: peb@amleth.demon.co.uk ("Paul E. Bennett")
Date: Thu, 17 Aug 00 23:41:24 GMT
Links: << >>  << T >>  << A >>
In article <399BF174.A99313E7@ops.de> Paul.Augart@ops.de "Paul Augart" writes:

> This is a multi-part message in MIME format.
> --------------1F16AD12B05880F84B6ECE54
> Content-Type: text/plain; charset=us-ascii
> Content-Transfer-Encoding: 7bit
> 
> Hello Mr. Holle,
> 
>     No! This is very interesting to me.
> I have had little experience with NDAs and would I like to learn, what to
> look out for and how to handle such a situation.
> This is also part of an Engineers life/work (sadly, I would be happy to
> work on tech stuff, but we live in the real world, and this goes with
> it!).
> 

An NDA is simply a requirement that:

  You will keep any sensitive information I divulge to you as part of our
  discussions, document transmissions or other communications secure from
  disclosure to any un-authorised (by me) third party (including keeping 
  any documents issued safe and secure).

  I will, likewise, keep any sensitive information you divulge to me 
  through discussion, document transmission or other communications secure
  from disclosure to third parties not authorised by you.

  Any information that becomes public knowledge by authorised release or
  from a third party separately from that covered by the agreement is not
  part of the agreement.

  Release Authorisation shall be recorded in a log of such releases.

Somewhere along the line you have to document what the sensitive 
information is (otherwise you will not remember it's status). Some 
companies will state a time limit to the agreement but some will desire
the agreement to stand for a very long time and often will not mention
a time limit.

Anyway, that is the jist of it. I have seen some agreement documents which
look like they need many man-years of Harvard Law School training just to 
be able to read them. You should be able to compose the fully legitimate 
terms into a one or two page document at most.

-- 
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-814586 .... see http://www.feabhas.com for details.
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************

Article: 24763
Subject: Re: state encoding in Synplify!!!
From: Ray Andraka <ray@andraka.com>
Date: Thu, 17 Aug 2000 23:45:30 GMT
Links: << >>  << T >>  << A >>
There are some rules that apply for a machine with hamming distances of one on
all states (this is what we are talking about here, but I really hesitate
calling it gray code.  Gray code is a specific count sequence).  In the case of
your little machine, you need to add two transition states to make it work (the
number of states around a loop has to be even to get back to the starting state
with only one bit change per transition).  if you add transition states CT and
DT then:

A=> B or C or D
B=> Ct or Dt
Ct=> C
Dt=> D

then it works out just fine.  Like I said, you need to follow the rules if you
want to play the game.

A= 000
B= 001
Ct= 011
C= 010
Dt = 101
D = 100






Andy Holt wrote:
> 
> Peter Alfke wrote:
> >
> 
> > But it is inherently impossible to have a single-bit change in a state machine
> > where, depending on control inputs, the code might jump in many ways.
> > So, what's the meaning of a "Gray-encoded" state machine?
> 
> At first I thought you were wrong here and a similar technique to "one
> hot" could be used with at most twice as many flip-flops as one hot
> encoding, but a little analysis showed this is not so.
> 
> Considering the following mini state machine (only showing what
> transitions can take place, not their conditions)
> 
> A -> B or C or D
> B -> C or D
> C -> <who cares>
> D -> <who cares>
> 
> Let us assume that there exists a Gray encoding for this state machine
> 
> Then A differs from each of B, C, D by one bit only.
> 
> For convenience consider A to be represented 111 (we can always choose
> complements to ensure this)
> then B,C,D have to be (in some order): 011, 101, 110 (i.e. the three
> one-bit changes)
> but then the change from B to C requires at least 2 bit changes.
> Thus we do not have a Gray encoding
> 
> It might be possible to get round this by having multiple mappings for
> each state but this would get so ridiculously messy as to defeat any
> possible advantage in having a 1-bit state change.
> 
> Andy

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24764
Subject: Re: Non-disclosures in job interviews, Round One
From: peb@amleth.demon.co.uk ("Paul E. Bennett")
Date: Thu, 17 Aug 00 23:46:00 GMT
Links: << >>  << T >>  << A >>
In article <8ngv2n$o0l$1@news.drenet.dnd.ca>
           qn42@hotmail.com "Darren Kuhn" writes:


> I find this all kinda interesting considering I find myself on the opposite
> end of the scale, if I was to go for an interview I wouldn't be able to talk
> much about my abilities/areas of work because of the security issues
> involved in my present work...and I doubt they would sign a NDA from me.

Should you be talking about such issues without authorisation from your
current employer? So, if you cannot talk about your current work how do
you convince someone else you are worth employing?

-- 
********************************************************************
Paul E. Bennett ....................<email://peb@amleth.demon.co.uk>
Forth based HIDECS Consultancy .....<http://www.amleth.demon.co.uk/>
Mob: +44 (0)7811-639972 .........NOW AVAILABLE:- HIDECS COURSE......
Tel: +44 (0)1235-814586 .... see http://www.feabhas.com for details.
Going Forth Safely ..... EBA. www.electric-boat-association.org.uk..
********************************************************************

Article: 24765
Subject: Re: Clock recovery in FPGA
From: Ray Andraka <ray@andraka.com>
Date: Thu, 17 Aug 2000 23:47:52 GMT
Links: << >>  << T >>  << A >>
Without a faster clock, you'll probably not be successful with a fully digital
system (it might be possible to do with a DLL, but I wouldn't count on doing it
in an FPGA)

Your best bet is probably going to an analog PLL designed specifically for clock
recovery at the bit rate you are using, such as they do in any number of
deserializers out there.

oivan@my-deja.com wrote:
> 
> Unfortunately the bit rate of the data is 200MHz and I don't have
> faster Clock available. Thanks!
> 
> In article <399C19F2.916ADE68@andraka.com>,
>   Ray Andraka <ray@andraka.com> wrote:
> > what is the bit rate of the stream, and what is the fastest clock you
> have
> > available?  The higher the ratio, the easier the job is.  Basically
> you are
> > looking at a DPLL (digital phase lock loop) design.  In simple terms,
> the DPLL
> > is for the most part a counter whose modulus is adjusted slightly if
> the
> > terminal count doesn't line up with the next bit edge.
> >
> > oivan@my-deja.com wrote:
> > >
> > > Hi,
> > > Has anyone designed circuit that performs clock recovery from serial
> > > data stream, in FPGA. I would appreciate any info.
> > > Thanks.
> > >
> > > Sent via Deja.com http://www.deja.com/
> > > Before you buy.
> >
> > --
> > -Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930     Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com  or http://www.fpga-guru.com
> >
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24766
Subject: Re: Non-disclosures in job interviews
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 21:01:01 -0400
Links: << >>  << T >>  << A >>
Got Me Lucky Charms wrote:
> to put 2 and 2 together.  Just recently at a convention, I was introduced to
> a company inquiring about my availability as a consultant.  Viola!  I knew
> what they were trying to do.  There were only 2 basic possibilities.  A
> 5 minute, non-specific discussion, and I had it figured out.
> Now, it's not in good taste for my to call up 3 of my best friends in the
> world,
> who happen to work at a competitor of these other folks, and unload.
> That would allow that company to position themselves, and further weaken
> the efforts of company A to get into an area.
> 
> So, I still hold by the argument that and NODE is not completely
> inappropriate for
> reasons even less benign than "direct collusion" or "direct disclosure".
> Propriety goes beyond just technical propriety.

But your analysis of the questions presented is in no way restricted.
You would be perfectly free, even if you had signed a non-disclosure
agreement, to tell your friends what you "believe" the other company to
be up to. They did not tell you, you surmized it. The agreement you
would have had to sign can only protect the facts that were presented to
you. 

By the same token, vendors have a great deal of insight into what a
company is doing by token of what they are buying or even asking for
info on. They are never, in my knowledge, asked to sign a NDA before
being told what datasheets are requested of them. 

Information will leak out of any company. Heck, it leaks out of the
government when people can go to jail over it. A company that goes to
such lengths to get legal protection against this can be very dangerous
regardless of whether or not you really violated the agreement. 


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24767
Subject: Re: Non-disclosures in job interviews
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 21:11:21 -0400
Links: << >>  << T >>  << A >>
"Paul E. Bennett" wrote:
> An NDA is simply a requirement that:
> 
>   You will keep any sensitive information I divulge to you as part of our
>   discussions, document transmissions or other communications secure from
>   disclosure to any un-authorised (by me) third party (including keeping
>   any documents issued safe and secure).
> 
>   I will, likewise, keep any sensitive information you divulge to me
>   through discussion, document transmission or other communications secure
>   from disclosure to third parties not authorised by you.
> 
>   Any information that becomes public knowledge by authorised release or
>   from a third party separately from that covered by the agreement is not
>   part of the agreement.
> 
>   Release Authorisation shall be recorded in a log of such releases.
> 
> Somewhere along the line you have to document what the sensitive
> information is (otherwise you will not remember it's status). Some
> companies will state a time limit to the agreement but some will desire
> the agreement to stand for a very long time and often will not mention
> a time limit.
> 
> Anyway, that is the jist of it. I have seen some agreement documents which
> look like they need many man-years of Harvard Law School training just to
> be able to read them. You should be able to compose the fully legitimate
> terms into a one or two page document at most.

Your summary of an NDA is general, but not always accurate. Each one is
unique and may contain some very different clauses. For example, the one
that I made the modification to very clearly indicated that the company
not only was not willing to keep my sensitive information confidential,
and that I would not disclose any sensitive information to them. This
keeps me from ever pursuing a suit against them. 

Further, the modification I wanted to make was to document the the
sensitive information. It would be in their interest not to document
this as they could later claim any information was part of the
interview. 

This was a very one-sided agreement which was done to protect the
company at the expense of the interviewee. This is not unusual. 

-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24768
Subject: Re: Implementing an All Digital PLL in FPGA
From: Matthew Donadio <m.p.donadio@ieee.org>
Date: Thu, 17 Aug 2000 21:37:05 -0400
Links: << >>  << T >>  << A >>
"John B. Sampson" wrote:
> Artur Leung wrote in message <399B5718.F6498094@REMOVEittc.ukans.edu>...
> >     I am working on a digital QPSK demodulator and run into problems of
> >designing an all-digital phase-locked loop (ADPLL) for the carrier
> >recovery circuitry.
> >...

> You might want to have a look at the data sheet for Intersil's Digital
> Costas Loop IC. I think this IC implements much of what you want, and the
> data sheet has lots of details on how it works.
> ...
> http://www.intersil.com/data/fn/fn3/fn3652/fn3652.pdf

In addition to the datasheet for the HSP50210, these two books may be of
some use:

@Book{dig-sync,
  author =    "Umberto Mengali and Aldo N. D'Andrea",
  title =     "Synchronization Techniques for Digital Receivers",
  publisher = "Plenum Press",
  year =       1997,
  address =   "New York",
  series =    "Applications of Communications Theory"
}

@Book{sync-v2,
  author =    "Heinrich Meyr and Marc Moeneclaey and Stefan A. Fechtel",
  title =     "Digital Communication Receivers: Synchronization, Channel
               Estimation, and Signal Processing",
  publisher = "Wiley-Interscience",
  year =       1998,
  series =    "Wiley Series in Telecommunications and Signal
               Processing",
  address =   "New York"
}

--Matt Donadio (m.p.donadio@ieee.org)
Article: 24769
Subject: Re: Deterministic FPGA routing?
From: murray@pa.dec.com (Hal Murray)
Date: 18 Aug 2000 02:06:35 GMT
Links: << >>  << T >>  << A >>

> Please, Altera and Xilinx, never give up the command line interface to 
> your tools.

I'd like to second that.  Good documentation is important too.

What I really want is something that cooperates with make.
Aside from all the options that I can specify on the command
line, I need to understand the sequence of steps to go through
and I need to know what files each step produces.

I consider the Makefile to be a critical part of the documentation.

-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 24770
Subject: Re: state encoding in Synplify!!!
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 17 Aug 2000 22:22:10 -0400
Links: << >>  << T >>  << A >>
Yes, you can do this, but this is still not a general solution. The
states C and D may need to last for only one clock cycle or have other
restrictions that prevent you from using the Ct and Dt states. 

I am inclined to think that "Gray" is not really a valid FSM encoding
option with the HDL synthesis engines. It is probably specifed only for
counters. 


Ray Andraka wrote:
> 
> There are some rules that apply for a machine with hamming distances of one on
> all states (this is what we are talking about here, but I really hesitate
> calling it gray code.  Gray code is a specific count sequence).  In the case of
> your little machine, you need to add two transition states to make it work (the
> number of states around a loop has to be even to get back to the starting state
> with only one bit change per transition).  if you add transition states CT and
> DT then:
> 
> A=> B or C or D
> B=> Ct or Dt
> Ct=> C
> Dt=> D
> 
> then it works out just fine.  Like I said, you need to follow the rules if you
> want to play the game.
> 
> A= 000
> B= 001
> Ct= 011
> C= 010
> Dt = 101
> D = 100


-- 

Rick Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com
Article: 24771
Subject: Re: Xilinx design flow with Mentor
From: "Austin Franklin" <austin@dark76room.com>
Date: 18 Aug 2000 02:36:37 GMT
Links: << >>  << T >>  << A >>
What exactly do you mean by 'reuse'?  Also, what did you compare these
tools to, as you said it's the 'better' flow?


Laurent Gauch <laurent.gauch@aps-euro.com> wrote in article
<399C3A8D.A4C69277@aps-euro.com>...
> Use it now !
> 
> For me, that's the better flow for FPGA design !
> And when you write your code, think "reuse". FPGA Advantage suite allows
> the reuse.
> 
> Good work!
> Laurent
> 
> Paul Smith a écrit :
> 
> > Hi all
> >
> > I'm new to Xilinx FPGAs, although I've done several Viewlogic schematic
> > based Actel designs.
> >
> > I'm starting a design which should fit in a Xilinx Spartan II, either a
> > XC2S30 or XC2S50.  I need to use the blockRAM in dual port mode.
> >
> > I have access to Mentor products, and would like to use mainly HDL,
> > although I may want to enter some sections of the design as schematics.
> >
> > It looks like the Mentor FPGA Advantage suite (Renoir, ModelSim, and
> > Leonardo) will work for me.  Anyone out there have experience with this
> > toolset for the Spartan II target?
> >
> > I assume I also need the Xilinx Alliance software?
> >
> > TIA
> >
> > Paul Smith
> 
> 
Article: 24772
Subject: Re: Comparing Xilinx FPGAs
From: murray@pa.dec.com (Hal Murray)
Date: 18 Aug 2000 06:21:56 GMT
Links: << >>  << T >>  << A >>

> As for the clock enable I do agree. 
> However, the lack of high speed high
> fanout nets limits its use in fast
> circuits.  The secondary high fanout
> nets are way too slow for use in the
> type designs where the clock enables
> would be helpful on a large scale.  You
> wind up using extra CLBs to construct a
> clock enable tree to keep up with the
> speeds the chip is otherwise capable
> of.

Peter:  Here is a good example of the type
of info I'd like to see in the paper data
book.  How fast can I run a system using
a high-fanout clock enable?  How fast with
a local signal feeding a whole column or
16 or 32 bits of register?

Make reasonable assumptions/restrictions on
placement if that's appropriate, but then
I'll probably want similar info without
the restrictions.
-- 
These are my opinions, not necessarily my employers.  I hate spam.
Article: 24773
Subject: Re: state encoding in Synplify!!!
From: Ray Andraka <ray@andraka.com>
Date: Fri, 18 Aug 2000 06:37:26 GMT
Links: << >>  << T >>  << A >>
I agree that it doesn't belong in a synthesized machine unless it is only
referring to counters.  Generally speaking, the only times I've really seen a
need for a Hamming-1 machine is when there is something very asynchronous going
on -- typically that means a clockless state machine.

rickman wrote:
> 
> Yes, you can do this, but this is still not a general solution. The
> states C and D may need to last for only one clock cycle or have other
> restrictions that prevent you from using the Ct and Dt states.
> 
> I am inclined to think that "Gray" is not really a valid FSM encoding
> option with the HDL synthesis engines. It is probably specifed only for
> counters.
> 
> Ray Andraka wrote:
> >
> > There are some rules that apply for a machine with hamming distances of one on
> > all states (this is what we are talking about here, but I really hesitate
> > calling it gray code.  Gray code is a specific count sequence).  In the case of
> > your little machine, you need to add two transition states to make it work (the
> > number of states around a loop has to be even to get back to the starting state
> > with only one bit change per transition).  if you add transition states CT and
> > DT then:
> >
> > A=> B or C or D
> > B=> Ct or Dt
> > Ct=> C
> > Dt=> D
> >
> > then it works out just fine.  Like I said, you need to follow the rules if you
> > want to play the game.
> >
> > A= 000
> > B= 001
> > Ct= 011
> > C= 010
> > Dt = 101
> > D = 100
> 
> --
> 
> Rick Collins
> 
> rick.collins@XYarius.com
> 
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com
Article: 24774
Subject: Re: Xilinx chip not programming correctly
From: Miguel Angel Aguirre <aguirre@esi.us.es>
Date: Fri, 18 Aug 2000 07:04:46 GMT
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------1969A5F51F60221A62EABD26
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

HI:
I've a similar problem. I'm working with OSC4 as well. After generating the .bit file (fully free of warnings) I download the .bit file through JTAG from XCHECKER cable DLC-4. Software (Foundation 2.1i_SP6) says "Downloading process successfully" but XC4010XL-PC84 doesn't say anything ... sometimes.
I've tried it with many different device samples and I'm sure that the device and cable aren't damaged. Suddenly I works fine and I cannot understand what am I doing bad. Possibilities:
    - Common I/O are driven by other chips of the board during config.
    - Absence of pull-up in PROG pin
    - 0.3V in INIT pint during configuration

Any other idea?

Miguel

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--------------1969A5F51F60221A62EABD26--



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