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Messages from 27125

Article: 27125
Subject: Re: Configuring Xilinx FPGA using PIC16F84
From: edick@hotmail.com (Richard Erlacher)
Date: Sat, 11 Nov 2000 22:17:15 GMT
Links: << >>  << T >>  << A >>
On Sat, 11 Nov 2000 00:45:46 GMT, "John Janusson" <null@null.com>
wrote:

>http://www.fpgaconfigurator.com/
>
>I think it uses a PIC.
>
>Independently, I've used a PIC for FPGA configuration, and it works quite
>well, although it's a little slow for serial bit bang operations...
>
>John
>
>Kang Liat Chuan <kanglc@cyberway.com.sg> wrote in message
>news:3a0ad556@news.starhub.net.sg...
>> Hi,
>>
>> Has anyone done it? Is it possible? Target FPGA: Xilinx XC4005E-4
>> I remember reading a web page on using Atmel AT89C2051 to configure the
>> FPGA, but can't find any using PIC.
>>
>> Regards,
>> LC
>> kanglc@agilis.st.com.sg
>>
===============================================================
It's likely you will find the speed of the SCENIX SX <www.scenix.com>
more to your liking.   At their relatively low price, not to mention
their extreme flexibility as opposed to an FPGA, you may find you can
use it IN PLACE of one or more FPGA's. 

 Since they cost <$10 and are not as vulnerable as FPGA's with their
external configuation prom, you may find that several of them can
replace one or more of those >$1k FPGA's you see in the price lists.  

They don't fit every appplication, but if you can partition your tasks
to fit the package and don't object to the high speed and substantial
output drive, you can use these very effectively.  The largest of the
surface-mountable parts is about the size of my thumbnail, including
the required pads.  

Dick



Article: 27126
Subject: Re: Configuring Xilinx FPGA using PIC16F84
From: edick@hotmail.com (Richard Erlacher)
Date: Sat, 11 Nov 2000 22:17:31 GMT
Links: << >>  << T >>  << A >>
On Sat, 11 Nov 2000 00:45:46 GMT, "John Janusson" <null@null.com>
wrote:

>http://www.fpgaconfigurator.com/
>
>I think it uses a PIC.
>
>Independently, I've used a PIC for FPGA configuration, and it works quite
>well, although it's a little slow for serial bit bang operations...
>
>John
>
>Kang Liat Chuan <kanglc@cyberway.com.sg> wrote in message
>news:3a0ad556@news.starhub.net.sg...
>> Hi,
>>
>> Has anyone done it? Is it possible? Target FPGA: Xilinx XC4005E-4
>> I remember reading a web page on using Atmel AT89C2051 to configure the
>> FPGA, but can't find any using PIC.
>>
>> Regards,
>> LC
>> kanglc@agilis.st.com.sg
>>
===============================================================
It's likely you will find the speed of the SCENIX SX <www.scenix.com>
more to your liking.   At their relatively low price, not to mention
their extreme flexibility as opposed to an FPGA, you may find you can
use it IN PLACE of one or more FPGA's. 

 Since they cost <$10 and are not as vulnerable as FPGA's with their
external configuation prom, you may find that several of them can
replace one or more of those >$1k FPGA's you see in the price lists.  

They don't fit every appplication, but if you can partition your tasks
to fit the package and don't object to the high speed and substantial
output drive, you can use these very effectively.  The largest of the
surface-mountable parts is about the size of my thumbnail, including
the required pads.  

Dick



Article: 27127
Subject: Re: CRC, LFSR and scramblers
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Sat, 11 Nov 2000 14:28:33 -0800
Links: << >>  << T >>  << A >>
Is there a way to simplify ( and speed up ) this calculation by using
BlockRAMs as look-up tables?
Today's Virtex offers many 4k-bit dual-ported RAMs ( or call them ROMs ) of
arbitrary aspect ratio, e.g. 256 x 16.
The upcoming Virtex-II has 18 Kb dual-ported BlockRAMs that can be used as 1K
x 18 or 512 x 36 look-up tables. ( And each BlockRAM has two independent
ports, so it can implement the same code conversion or algorithm twice,
simultaneously. )

These RAMs or ROMs are very fast, 1 ns set-up, < 3 ns clock-to-out,
and they are free, if you don't need them for anything better.

Just a half-cooked thought...
Peter Alfke


rickman wrote:

> I have no choice in the polynomial to be used. This is specified in the
> different specs I am working with. I also can not perform the
> calculation serially. We are processing 32 bits of data on each clock
> cycle. So I must perform the calculation on all 32 bits at once. I have
> calculated the logic to do this, but it requires as many as 20 inputs
> for one bit. This uses too many levels of logic in an FPGA to calculate
> in one clock cycle. So I am looking for ways to reduce the complexity of
> the calculation.
>
> I have already rejected pipelining the calculation since we have to have
> the result from one calculation to start the next calculation on the
> next clock cycle.
>
> So I am looking for a way to transform the problem into one I can
> pipeline such as calculating a different CRC which can be divided by a
> polynomial to get the result of the CRC I am looking for. I am not
> trying to solve a single CRC calculation. I am trying to solve the
> general case.
>
> I would be happy to see any CRC URLs that you might have.
>
> Mohammed Ishaq wrote:
> >
> > hi,
> >
> > You have not mentioned which CRC you are using. I guess it is CRC-32. To
> > reduce the complexity of the CRC, you should use a lower order
> > polynomial CRC, say in your case CRC-16 or CRC-CCITT and pass the 32 bit
> > data in serially. I suggest you use CRC-CCITT since it is widely used
> > (serial communications, floppy controller etc) and the psedu-code is
> > also available in the web, if you search for CRC-CCITT.
> >
> > If you are not happy with your search results, I can post the URLs I
> > have.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
>
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
>
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
>
> Internet URL http://www.arius.com


Article: 27128
Subject: Re: CRC, LFSR and scramblers
From: rickman <spamgoeshere4@yahoo.com>
Date: Sat, 11 Nov 2000 23:54:45 -0500
Links: << >>  << T >>  << A >>
Certainly this would work if we were doing a smaller calculation. We
could use the block ram as a lookup table. But we have 32 bits input
with 9 to 16 bits of feedback and 32 bits out. This would need far too
large of a RAM to be practical. 

We also can't use proprietary features. This company wants to be
independant of FPGA vendors so we don't make use of any proprietary
features. Every time they design a new module, they compete price to
pick a vendor. This may be smart or not depending on how much larger of
a part they need to do a given job. But mine is not to reason why...

It is also an interesting problem. I could stand to learn a little more
about modular arithmetic and other such matters. 


Peter Alfke wrote:
> 
> Is there a way to simplify ( and speed up ) this calculation by using
> BlockRAMs as look-up tables?
> Today's Virtex offers many 4k-bit dual-ported RAMs ( or call them ROMs ) of
> arbitrary aspect ratio, e.g. 256 x 16.
> The upcoming Virtex-II has 18 Kb dual-ported BlockRAMs that can be used as 1K
> x 18 or 512 x 36 look-up tables. ( And each BlockRAM has two independent
> ports, so it can implement the same code conversion or algorithm twice,
> simultaneously. )
> 
> These RAMs or ROMs are very fast, 1 ns set-up, < 3 ns clock-to-out,
> and they are free, if you don't need them for anything better.
> 
> Just a half-cooked thought...
> Peter Alfke
> 
> rickman wrote:
> 
> > I have no choice in the polynomial to be used. This is specified in the
> > different specs I am working with. I also can not perform the
> > calculation serially. We are processing 32 bits of data on each clock
> > cycle. So I must perform the calculation on all 32 bits at once. I have
> > calculated the logic to do this, but it requires as many as 20 inputs
> > for one bit. This uses too many levels of logic in an FPGA to calculate
> > in one clock cycle. So I am looking for ways to reduce the complexity of
> > the calculation.
> >
> > I have already rejected pipelining the calculation since we have to have
> > the result from one calculation to start the next calculation on the
> > next clock cycle.
> >
> > So I am looking for a way to transform the problem into one I can
> > pipeline such as calculating a different CRC which can be divided by a
> > polynomial to get the result of the CRC I am looking for. I am not
> > trying to solve a single CRC calculation. I am trying to solve the
> > general case.
> >
> > I would be happy to see any CRC URLs that you might have.
> >
> > Mohammed Ishaq wrote:
> > >
> > > hi,
> > >
> > > You have not mentioned which CRC you are using. I guess it is CRC-32. To
> > > reduce the complexity of the CRC, you should use a lower order
> > > polynomial CRC, say in your case CRC-16 or CRC-CCITT and pass the 32 bit
> > > data in serially. I suggest you use CRC-CCITT since it is widely used
> > > (serial communications, floppy controller etc) and the psedu-code is
> > > also available in the web, if you search for CRC-CCITT.
> > >
> > > If you are not happy with your search results, I can post the URLs I
> > > have.

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 27129
Subject: Re: CRC, LFSR and scramblers
From: Ray Andraka <ray@andraka.com>
Date: Sun, 12 Nov 2000 05:17:55 GMT
Links: << >>  << T >>  << A >>
Here's a case of penny-wise and pound-foolish.  The cost of the larger faster
devices needed to make up for forsaking the device specific features is far
larger than the money saved by going to the lowest bidder each time around. 
Even still, you can design to a 4-LUT, as those are fairly universal now.  Also,
Synplicity is doing a better job than in the past at actually inferring circuits
using the device specific stuff if it is available.

As for the CRC polynomial, do you really need to solve the general case, or is
there a small subset of polynomials that will be sufficient?

rickman wrote:
> 
> Certainly this would work if we were doing a smaller calculation. We
> could use the block ram as a lookup table. But we have 32 bits input
> with 9 to 16 bits of feedback and 32 bits out. This would need far too
> large of a RAM to be practical.
> 
> We also can't use proprietary features. This company wants to be
> independant of FPGA vendors so we don't make use of any proprietary
> features. Every time they design a new module, they compete price to
> pick a vendor. This may be smart or not depending on how much larger of
> a part they need to do a given job. But mine is not to reason why...
> 
> It is also an interesting problem. I could stand to learn a little more
> about modular arithmetic and other such matters.
> 
> Peter Alfke wrote:
> >
> > Is there a way to simplify ( and speed up ) this calculation by using
> > BlockRAMs as look-up tables?
> > Today's Virtex offers many 4k-bit dual-ported RAMs ( or call them ROMs ) of
> > arbitrary aspect ratio, e.g. 256 x 16.
> > The upcoming Virtex-II has 18 Kb dual-ported BlockRAMs that can be used as 1K
> > x 18 or 512 x 36 look-up tables. ( And each BlockRAM has two independent
> > ports, so it can implement the same code conversion or algorithm twice,
> > simultaneously. )
> >
> > These RAMs or ROMs are very fast, 1 ns set-up, < 3 ns clock-to-out,
> > and they are free, if you don't need them for anything better.
> >
> > Just a half-cooked thought...
> > Peter Alfke
> >
> > rickman wrote:
> >
> > > I have no choice in the polynomial to be used. This is specified in the
> > > different specs I am working with. I also can not perform the
> > > calculation serially. We are processing 32 bits of data on each clock
> > > cycle. So I must perform the calculation on all 32 bits at once. I have
> > > calculated the logic to do this, but it requires as many as 20 inputs
> > > for one bit. This uses too many levels of logic in an FPGA to calculate
> > > in one clock cycle. So I am looking for ways to reduce the complexity of
> > > the calculation.
> > >
> > > I have already rejected pipelining the calculation since we have to have
> > > the result from one calculation to start the next calculation on the
> > > next clock cycle.
> > >
> > > So I am looking for a way to transform the problem into one I can
> > > pipeline such as calculating a different CRC which can be divided by a
> > > polynomial to get the result of the CRC I am looking for. I am not
> > > trying to solve a single CRC calculation. I am trying to solve the
> > > general case.
> > >
> > > I would be happy to see any CRC URLs that you might have.
> > >
> > > Mohammed Ishaq wrote:
> > > >
> > > > hi,
> > > >
> > > > You have not mentioned which CRC you are using. I guess it is CRC-32. To
> > > > reduce the complexity of the CRC, you should use a lower order
> > > > polynomial CRC, say in your case CRC-16 or CRC-CCITT and pass the 32 bit
> > > > data in serially. I suggest you use CRC-CCITT since it is widely used
> > > > (serial communications, floppy controller etc) and the psedu-code is
> > > > also available in the web, if you search for CRC-CCITT.
> > > >
> > > > If you are not happy with your search results, I can post the URLs I
> > > > have.
> 
> --
> 
> Rick "rickman" Collins
> 
> rick.collins@XYarius.com
> 
> Ignore the reply address. To email me use the above address with the XY
> removed.
> 
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design
> 
> Arius
> 4 King Ave
> Frederick, MD 21701-3110
> 301-682-7772 Voice
> 301-682-7666 FAX
> 
> Internet URL http://www.arius.com

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 27130
Subject: Easy money for the Holidays!
From: zeynep14@aol.com (ZEYNEP14)
Date: 12 Nov 2000 05:22:21 GMT
Links: << >>  << T >>  << A >>
A little while back, I was browsing through news groups, just like you are now,

and came across an article similar to this that said you could make
thousands of dollars within weeks with only an initial investment of
$6.00! So I thought, "Yeah right, this must be a scam", but
like most of us, I was curious, so I kept reading. Anyway, it said
that you send $1.00 to each of the 6 names and address stated in the
article. You then place your own name and address in the bottom of
the list at #6, and post the article in at least 200 newsgroups.
(There are thousands) No catch, that was it. So after thinking it
over, and talking to a few people first, I thought about trying it. I
figured: "what have I got to lose except 6 stamps and $6.00,
right?" Then I invested the measly $6.00. Well GUESS WHAT!?...
within 7 days, I started getting money in the mail! I was shocked! I
figured it would end soon, but the money just kept coming in. In my
first week, I made about $25.00. By the end of the second week I had
made a total of over $1,000.00! In the third week I had over
$10,000.00 and it's still growing. This is now my fourth week and I
have made a total of just over $42,000.00 and it's still coming in
rapidly. It's certainly worth $6.00, and 6 stamps, I have spent more
than that on the lottery!! Let me tell you how this works and most
importantly, WHY it works... Also, make sure you print a copy of this
article NOW, so you can get the information off of it as you need it.
I promise you that if you follow the directions exactly, that you
will start making more money than you thought possible by doing
something so easy!
Suggestion: Read this entire message carefully! (print it out or
download it.) Follow the simple directions and watch the money come
in!
It's easy. It's legal. And, your investment is only $6.00 (Plus
postage)

IMPORTANT: This is not a rip-off; it is not indecent; it is not
illegal; and it is 99% no risk - it really works!
If all of the following instructions are adhered to, you will receive
extraordinary dividends.

PLEASE NOTE:
Please follow these directions EXACTLY, and $50,000 or more can be
yours in 20 to 60 days. This program remains successful because of
the honesty and integrity of the participants. Please continue its
success by carefully adhering to the instructions.
You will now become part of the Mail Order business. In this business
your product is not solid and tangible, it's a service. You are in
the business of developing Mailing Lists. Many large corporations are
happy to pay big bucks for quality lists. However, the money made
from the mailing lists is secondary to the income which is made from
people like you and me asking to be included in that list.

Here are the 4 easy steps to success:

STEP 1: Get 6 separate pieces of paper and write the following on
each piece of paper "PLEASE PUT ME ON YOUR MAILING LIST."
Now get 6 US $1.00 bills or Canadian Loonie and place ONE inside EACH of
the 6 pieces of paper so the bill or coin will not be seen through the
envelope (to prevent thievery).
Next, place one paper in each of the 6 envelopes and seal them. You should
now
have 6 sealed envelopes, each with a piece of paper stating the above
phrase,
your name and address, and a $1.00 bill or coin. What you are doing is
creating
a service. THIS IS ABSOLUTELY LEGAL! You are requesting a legitimate service
and
you are paying for it! Like most of us I was a little skeptical and a little
worried about the legal aspects of it all. So I checked it out with the Post
Office (1-800-725-2161) and they confirmed that it is indeed legal.
Mail the 6 envelopes to the following addresses:



#1) S. WOOD
9648 WINTER GARDENS BLVD.
APT.#3
LAKESIDE, CA 92040

#2) M. Busch
2106 Woodland Ave.
Raleigh, NC 27608

#3) J. Anderson
2111 Woodland Ave.
Raleigh, NC 27608

#4) C. Smith
P.O. Box 292
Climax, NC 27233

#5) R. Catuccio
108 Gorman St.
Naugatuck, Ct, 06770

#6) H. Kurt
8-04 Melvin Pl.
Fair Lawn, NJ 07410

STEP 2: Now take the #1 name off the list that you see above, move
the other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR
Name as number 6 on the list.

STEP 3: Change anything you need to, but try to keep this article as
close to original as possible. Now, post your amended article to at
least 200 newsgroups. (I think there are close to 24,000 groups) All
you need is 200, but remember, the more you post, the more money you
make! You won't get very much unless you post like crazy. :)
This is perfectly legal! If you have any doubts, refer to Title 18
Sec. 1302 & 1341 of the Postal lottery laws.Keep a copy of these steps
for yourself and, whenever you need money, you can use it again, and again.
PLEASE REMEMBER that this program remains successful because of the
honesty and integrity of the participants and by their carefully
adhering to the directions. Look at it this way. If you are of
integrity, the program will continue and the money that so many
others have received will come your way.

NOTE: You may want to retain every name and address sent to you,
either on a computer or hard copy and keep the notes people send you.
This VERIFIES that you are truly providing a service. (Also, it might
be a good idea to wrap the $1 bill or coin in dark paper to reduce the
risk of mail theft.)So, as each post is downloaded and the directions
carefully followed, six members will be reimbursed for their
participation as a List Developer with one dollar each. Your name will
move up the list geometrically so that when your name reaches the #1
position
you will be receiving thousands of dollars in CASH!!! What an opportunity
for
only $6.00 ($1.00 for each of the first six people listed above) Send
it now, add your own name to the list and you're in business!

---DIRECTIONS ----- FOR HOW TO POST TO NEWSGROUPS------------

Step 1) You do not need to re-type this entire letter to do your own
posting. Simply put your cursor at the beginning of this letter and
drag your cursor to the bottom of this document, and select 'copy'
from the edit menu. This will copy the entire letter into the
computer's memory.

Step 2) Open a blank 'notepad' file and place your cursor at the top
of the blank page. From the 'edit' menu select 'paste'. This will
paste a copy of the letter into notepad so that you can add your name
to the list.

Step 3) Save your new notepad file as a .txt file. If
you want to do your postings in different settings, you'll always have
this file to go back to.

Step 4) Use Netscape or Internet explorer and try searching for
various newsgroups (on-line forums, message boards, chat sites,
discussions.)

Step 5) Visit these message boards and post this article as a new
message by highlighting the text of this letter and selecting paste
from the edit menu. Fill in the Subject, this will be the header that
everyone sees as they scroll through the list of postings in a
particular group, click the post message button. You're done with
your first one! Congratulations...THAT'S IT! All you have to do is
jump to different newsgroups and post away, after you get the hang of
it, it will take about 30 seconds for each newsgroup.

**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU WILL
MAKE! BUT YOU HAVE TO POST A MINIMUM OF 200** That's it! You will begin
receiving money from around the world within days! You may eventually want
to
rent a P.O.Box due to the large amount of mail you will receive. If
you wish to stay anonymous, you can invent a name to use, as long as
the postman will deliver it.

**JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.**

Each of the 5 persons who just sent me $1.00 make the
MINIMUM 200 postings, each with my name at #5 and only 5 persons respond to
each
of the original 5, that is another $25.00 for me, now those 25 each make 200
MINIMUM posts with my name at #4 and only 5 replies each, I will bring in an
additional $125.00! Now, those 125 persons turn around and post the MINIMUM
200
with my name at #3 and only receive 5 replies each, I will make an
additional
$625.00!

OK, now here is the fun part, each of those 625 persons post a MINIMUM
200 letters with my name at #2 and they each only receive 5 replies, that
just made me $3,125.00!!! Those 3,125 persons will all deliver this message
to 200 newsgroups with my name at #1 and if still 5 persons per 200
newsgroups react I will receive $15,625,00! With an original
investment of only $6.00! AMAZING! When your name is no longer on the
list, you just take the latest posting in the newsgroups, and send
out another $6.00 to names on the list, putting your name at number 6
again. And start posting again. The thing to remember is: do you
realize that thousands of people all over the world are joining the
internet and reading these articles everyday?, JUST LIKE YOU are
now!! So, can you afford $6.00 and see if it really works?? I think
so... People have said, "what if the plan is played out and no
one sends you the money? So what! What are the chances of that
happening when there are tons of new honest users and new honest
people who are joining the internet and newsgroups everyday and are
willing to give it a try? Estimates are at 20,000 to 50,000 new
users, every day, with thousands of those joining the actual
internet. Remember, play FAIRLY and HONESTLY and this will really
work.



Article: 27131
Subject: Re: ChipScope
From: "Mark Harvey" <mark.harvey@iol.it>
Date: Sun, 12 Nov 2000 07:53:31 GMT
Links: << >>  << T >>  << A >>
Lawrence,

You don't need an Agilent 16700 to use chipscope, only a PC, a Parallel
download cable (or Multilinx) and access to the chipscope software - that's
what the $495 buys you.


Mark.


Lawrence Peregrim <lperegrim@ksa1.nospam.com> wrote in message
news:3A0B0705.FC585F8D@ksa1.nospam.com...
> I'm thinking about requesting the Xilinx ChipScope
> software & cores for purchase, despite having 16 Virtex
> I/O pins plus clock for LA hookup.  At $495, it seems
> like (relatively) cheap insurance.  Looks like we'd
> have to rent an Agilent 16700 LA to fully use it.
> Anyone have any experience with using ChipScope
> (i.e. would you recommend it)?
>
> A colleague has admonished me to check it out first
> before buying it because of his experience with Intel's
> early generation ICEs.
>
> much TIA.
>
> Lawrence Peregrim
> lperegrim@ksa1.nospam.com



Article: 27132
Subject: manchester decoder
From: htytus@shell1.iglou.com (Hul Tytus)
Date: 12 Nov 2000 09:06:09 -0500
Links: << >>  << T >>  << A >>
comp.arch.fpga
manchester decoder
Anyone know of a text that shows a decoder of Manchester encoded data? 
If so, leaving a note here or sending one to me via email would be much 
appreciated.
Hul		htytus@iglou.com

Article: 27133
Subject: Re: CRC, LFSR and scramblers
From: rickman <spamgoeshere4@yahoo.com>
Date: Sun, 12 Nov 2000 11:48:33 -0500
Links: << >>  << T >>  << A >>
The set of polynomials that need to be addressed is not fully known at
this time. I have identified at least four right now; ATM HEC (CRC-8),
O.191 scrambler (x9+x5+1), CRC-10, CRC-16. I know that we need to work
with others as well, but I don't know what they will be. 

Deciding to forsake the use of device specific features in the HDL code
may or may not be a mistake. I believe that Altera and Xilinx are the
only two vendors under serious consideration at this time and all the
products currently made by this company use parts from these two
vendors. 

However, the products already have a certain amount of excess capacity
built in since they plan on future growth of the product with new
features and higher speeds (wider busses and more gates). So the
difference in part size from not using instantiated features and living
with the inefficiencies of the synthesis tools are not the true cost
driver for these products. 

One of the tool problems we have to live with is a limitation to the
Altera toolset (as I have been told, since I am new to Altera parts). If
you have a wide combinatorial function such as XOR of many inputs, they
don't create a tree structure which will minimize the logic delay.
Instead they create a daisy chain which will minimize the routing delays
by using adjacent Logic Elements. This is fine for two LUT functions and
may still have an advantage with three LUT functions. But it gets bad
very quickly as you get to four LUT and higher (>10 inputs) functions. A
tree structure can accept up to 16 inputs with only two LUT levels while
a daisy chain requires 5 levels. I have not found out yet if there is a
way to get the tool to do what *you* want rather than what *it* thinks
is best for you.



Ray Andraka wrote:
> 
> Here's a case of penny-wise and pound-foolish.  The cost of the larger faster
> devices needed to make up for forsaking the device specific features is far
> larger than the money saved by going to the lowest bidder each time around.
> Even still, you can design to a 4-LUT, as those are fairly universal now.  Also,
> Synplicity is doing a better job than in the past at actually inferring circuits
> using the device specific stuff if it is available.
> 
> As for the CRC polynomial, do you really need to solve the general case, or is
> there a small subset of polynomials that will be sufficient?
> 
> rickman wrote:
> >
> > Certainly this would work if we were doing a smaller calculation. We
> > could use the block ram as a lookup table. But we have 32 bits input
> > with 9 to 16 bits of feedback and 32 bits out. This would need far too
> > large of a RAM to be practical.
> >
> > We also can't use proprietary features. This company wants to be
> > independant of FPGA vendors so we don't make use of any proprietary
> > features. Every time they design a new module, they compete price to
> > pick a vendor. This may be smart or not depending on how much larger of
> > a part they need to do a given job. But mine is not to reason why...
> >
> > It is also an interesting problem. I could stand to learn a little more
> > about modular arithmetic and other such matters.
> >
> > Peter Alfke wrote:
> > >
> > > Is there a way to simplify ( and speed up ) this calculation by using
> > > BlockRAMs as look-up tables?
> > > Today's Virtex offers many 4k-bit dual-ported RAMs ( or call them ROMs ) of
> > > arbitrary aspect ratio, e.g. 256 x 16.
> > > The upcoming Virtex-II has 18 Kb dual-ported BlockRAMs that can be used as 1K
> > > x 18 or 512 x 36 look-up tables. ( And each BlockRAM has two independent
> > > ports, so it can implement the same code conversion or algorithm twice,
> > > simultaneously. )
> > >
> > > These RAMs or ROMs are very fast, 1 ns set-up, < 3 ns clock-to-out,
> > > and they are free, if you don't need them for anything better.
> > >
> > > Just a half-cooked thought...
> > > Peter Alfke
> > >
> > > rickman wrote:
> > >
> > > > I have no choice in the polynomial to be used. This is specified in the
> > > > different specs I am working with. I also can not perform the
> > > > calculation serially. We are processing 32 bits of data on each clock
> > > > cycle. So I must perform the calculation on all 32 bits at once. I have
> > > > calculated the logic to do this, but it requires as many as 20 inputs
> > > > for one bit. This uses too many levels of logic in an FPGA to calculate
> > > > in one clock cycle. So I am looking for ways to reduce the complexity of
> > > > the calculation.
> > > >
> > > > I have already rejected pipelining the calculation since we have to have
> > > > the result from one calculation to start the next calculation on the
> > > > next clock cycle.
> > > >
> > > > So I am looking for a way to transform the problem into one I can
> > > > pipeline such as calculating a different CRC which can be divided by a
> > > > polynomial to get the result of the CRC I am looking for. I am not
> > > > trying to solve a single CRC calculation. I am trying to solve the
> > > > general case.
> > > >
> > > > I would be happy to see any CRC URLs that you might have.
> > > >
> > > > Mohammed Ishaq wrote:
> > > > >
> > > > > hi,
> > > > >
> > > > > You have not mentioned which CRC you are using. I guess it is CRC-32. To
> > > > > reduce the complexity of the CRC, you should use a lower order
> > > > > polynomial CRC, say in your case CRC-16 or CRC-CCITT and pass the 32 bit
> > > > > data in serially. I suggest you use CRC-CCITT since it is widely used
> > > > > (serial communications, floppy controller etc) and the psedu-code is
> > > > > also available in the web, if you search for CRC-CCITT.
> > > > >
> > > > > If you are not happy with your search results, I can post the URLs I
> > > > > have.
> >
> > --
> >
> > Rick "rickman" Collins
> >
> > rick.collins@XYarius.com
> >
> > Ignore the reply address. To email me use the above address with the XY
> > removed.
> >
> > Arius - A Signal Processing Solutions Company
> > Specializing in DSP and FPGA design
> >
> > Arius
> > 4 King Ave
> > Frederick, MD 21701-3110
> > 301-682-7772 Voice
> > 301-682-7666 FAX
> >
> > Internet URL http://www.arius.com
> 
> --
> -Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com  or http://www.fpga-guru.com

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 27134
Subject: Re: PLL vs DLL
From: "Steve Fair" <sfair6@home.com>
Date: Sun, 12 Nov 2000 17:13:37 GMT
Links: << >>  << T >>  << A >>
Peter -

Further clarification:

"Peter Alfke" <peter.alfke@xilinx.com> wrote in message
news:3A0DC343.4B13FB38@xilinx.com...
> Let me correct some misconceptions below:
>
> Steve Fair wrote:  <snip>
>
> > As mentioned, PLLs and DLLs need an accurate source clock in order to
lock -
> > wide ranging source clock PLLs are available but you'll have to go
external
> > to the FPGA world at this time.  One note - PLLs/DLLs will not improve
> > internal timing by a great deal - the dedicated clocks in FPGAs do a
pretty
> > good job of minizing skew.
>
> I disagree. Yes, clock skew is determined ( and kept reasonably low ) by
the
> strong dedicated clock driver tree structure.
> It is the inherent clock DELAY that can be eliminated by a PLL or DLL. And
on
> large chips, eliminating the basic clock delay ( and only having to worry
about
> the much smaller clock skew ) lets you achieve considerably higher
performance.
>

Delay is from the clock pin into the internal logic - that does affect tco
and tsu (my point).
Internal performance (i.e. flop to flop performance) = data delay - clock
skew (between the
two flops).  If all the clock DELAYS into the core match exactly then
internal fmax is purely based on the
internal data delay (regardless of how big or small the clock delay is).
The internal fmax "robber" is
clock SKEW, not clock delay.  So  DLL/PLL's do help remove SKEW, but not
dramatically
from what I've seen in designs I've run (kudo's to the clock tree
designers).  But then again,
a few MHz is sometimes a WONDERFUL thing!!

> > PLLs/DLLs are useful for clock multiplication
> > and division (PLLs rule this area) or improving clock to out (my
favorite
> > use) or internal performance (again, no panacea).
> >
> > If you're really fighting I/O timings, the Altera APEX PLLs have a nice
> > clock skew capability on the output (I don't think the Xilinx part has
this
> > capability??)
>
> Xilinx DLLs have exactly the same capabilty, we call it "clock mirroring".
You
> can use the FPGA to be your zero-delay clock driver. Considering the
multitude
> of I/O standards supported in Virtex FPGAs, this feature can be quite
handy.
>
Can you move the output clock in .5ns increments?? That's the feature I was
referring to in the altera parts (as well as the 90/180/270 adjustments)??
That
goes into the point below about stealing . . .

> > - you can skew the clock to the data or use clock feedback to
> > deskew the board delay.  This can be handy for things like SDRAM
> > interfaces - just realize that nothing's free - you're usually stealing
time
> > from somewhere else if you do this.
>
> You are not stealing anything, you are using a trick, introducing
additional
> delay on a repetitive clock signal, so that it looks as if you reduced the
> delay to nothing ( even to a negative value, if you are clever ).
Obviously,
> this trick works only on a free-running clock.
>
Peter - I was more referring to the fact that delaying a clock in a
synchronous
system will help tsu on the part you're talking to (i.e. the SDRAM case),
but
you have to take it back into account.  I.e. on a 100 MHz synchronous
system,
if you delay an output clock 2ns, then the part better be able to get the
data
back out in 8ns to line up with the master clock (please allow me to leave
all
the other timings out like hold for simplicity's sake).  I should never have
mentioned
the board deskew in the same paragraph as the clock shift / clock delay.  My
bad!
Removing skew, good, adding skew, stealing!  Thanks for clarifying my
muddled
prose.

Appreciate your help.

Steve

> Peter Alfke, Xilinx Applications
>



Article: 27135
Subject: Re: CRC, LFSR and scramblers
From: Mohammed Ishaq <ishaq@my-dejanews.com>
Date: Sun, 12 Nov 2000 17:47:11 GMT
Links: << >>  << T >>  << A >>
In article <3A0EC9E1.1CCD4E19@yahoo.com>,
  rickman <spamgoeshere4@yahoo.com> wrote:
> The set of polynomials that need to be addressed is not fully known at
> this time. I have identified at least four right now; ATM HEC (CRC-8),
> O.191 scrambler (x9+x5+1), CRC-10, CRC-16. I know that we need to work
> with others as well, but I don't know what they will be.

Earlier you said that it was 32 bit data. Are you generating all the the
CRCs (CRC-8, CRC-10, CRC-16 ..)  for the same 32 bit inputs ?

<snip>

>If
> you have a wide combinatorial function such as XOR of many inputs,
they
> don't create a tree structure which will minimize the logic delay.
> Instead they create a daisy chain which will minimize the routing
delays
> by using adjacent Logic Elements.
<snip>

I have faced this problem when I was implementing CRC-16 on an ASIC
using Synopsys. The only way I got around dc_shell do what I wanted, was
by overcontraining dc_shell. Otherwise a daisy chain was inferred. The
second solution is to handcode. Since this is a XOR tree, it should be
fairly easy.

ishaq


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27136
Subject: Re: CRC, LFSR and scramblers
From: hauck@ee.washington.edu (Scott Hauck)
Date: Sun, 12 Nov 2000 21:15:03 GMT
Links: << >>  << T >>  << A >>
I haven't looked at the details of CRC to know how feasible this is, but 
here's an approach you can try:

You are trying to compute functions

result(i) = F1(input(i), feedback(i-1))

feedback(i) = F2(input(i), feedback(i-1))

The feedback is your main concern, since obviously we can pipeline or delay 
the result computation.  So we focus on F2.  Let's hope that F2 is somewhat 
restructurable (if it was associative that would be wonderful, but in general 
it may be somewhat refactorable).  Restructure it so that as much work on the 
input(i) is grouped together.  You'll have something like:

feedback(i) = F3(F4(input(i)), feedback(i-1))

Hopefully F4 will reduce the number of input(i) bits needed by F3 from the 
full 32 to some smaller subset.  Now, put a pipeline stage on the output of F4 
(in fact, you can pipeline F4 arbitrarily, but we'll assume only one delay 
here).  This means that although feedback(i) is computed one cycle later than 
you expected, it is needed one cycle later in the computation.  Also, since 
result(i) can be arbitrarily delayed, it doesn't worry about the delay.

Hope this helps,

Scott

In article <3A0E2295.B48A1066@yahoo.com>, rickman <spamgoeshere4@yahoo.com> 
wrote:
>Certainly this would work if we were doing a smaller calculation. We
>could use the block ram as a lookup table. But we have 32 bits input
>with 9 to 16 bits of feedback and 32 bits out. This would need far too
>large of a RAM to be practical. 
>
>> > I have no choice in the polynomial to be used. This is specified in the
>> > different specs I am working with. I also can not perform the
>> > calculation serially. We are processing 32 bits of data on each clock
>> > cycle. So I must perform the calculation on all 32 bits at once. I have
>> > calculated the logic to do this, but it requires as many as 20 inputs
>> > for one bit. This uses too many levels of logic in an FPGA to calculate
>> > in one clock cycle. So I am looking for ways to reduce the complexity of
>> > the calculation.
>> >
>> > I have already rejected pipelining the calculation since we have to have
>> > the result from one calculation to start the next calculation on the
>> > next clock cycle.
>> >
>> > So I am looking for a way to transform the problem into one I can
>> > pipeline such as calculating a different CRC which can be divided by a
>> > polynomial to get the result of the CRC I am looking for. I am not
>> > trying to solve a single CRC calculation. I am trying to solve the
>> > general case.

<html>
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Article: 27137
Subject: Re: manchester decoder
From: murray@pa.dec.com (Hal Murray)
Date: 12 Nov 2000 21:30:22 GMT
Links: << >>  << T >>  << A >>

> Anyone know of a text that shows a decoder of Manchester encoded data?

I don't know of a good/simple text.  If you have access to a good
technical bookstore, you might try browsing.  I'd look in the index.
It might be called Biphase rather than Manchester.


What speed are you running at?

If you can easily get a 10X clock, then you can build a small
state machine to watch for transitions.  A bit of fiddling around
with paper and pencil should be enough for you to work it out.  Just ignore
the transitions between bit cells and watch for a transition near the middle
of a bit cell.  When you find one, reset the timing and send out a
0 or 1.

If you have a fast data stream, you probably want to use an external
chip with a PLL to do the clock recovery.


You can push the speed some by decoding 2 (or more) bits in parallel.
You need a high speed clock at the front end and the state machine
gets more complicated.


-- 
These are my opinions, not necessarily my employers.  I hate spam.

Article: 27138
Subject: Leon processor core
From: Frank Van de Sande <fvds12@yahoo.com>
Date: Sun, 12 Nov 2000 21:41:43 GMT
Links: << >>  << T >>  << A >>
hi,

has anyone ever used the Sparc prcessor core from ESA (called Leon)?

I'm considering it's use as a softcore in a Virtex, but i'm a bit
worried about development tools (compilers etc)

any experiences about the model and/or the tools?

thanks

Frank Van de Sande
fvds12@yahoo.com


Article: 27139
Subject: HOW TO TURN $6 INTO $6,000!!!!!!
From: woster145@aol.com (WOSTER145)
Date: 12 Nov 2000 22:27:36 GMT
Links: << >>  << T >>  << A >>
HOW TO TURN $6 INTO $6,000!!!!!! 
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to 50,000 new users, every day, with thousands of those joining the actual
internet. 
Remember: play FAIRLY and HONESTLY and this will really work. 

Article: 27140
Subject: Virtex circuit tricks -- add/mux in one LUT per bit
From: "Jan Gray" <jsgray@acm.org>
Date: Sun, 12 Nov 2000 23:26:04 GMT
Links: << >>  << T >>  << A >>
Many datapath circuits consist of an adder followed by a mux:
    o = add ? a + b : c;
    o = add ? a + b : a ~& c;
etc. For example, this structure appears in the PC/adder unit of xr
processors:
    addr_nxt = use_ea ? ea : pc + pc_incr;

I just figured out how to implement this add/mux circuit efficiently, one
LUT per bit, for Virtex family architectures. See
http://www.fpgacpu.org/index.html#001112 for more detail.  (Yes, I'm sure
many of you old hands at Virtex have already figured this out.)

Jan Gray, Gray Research LLC
FPGA CPU News: www.fpgacpu.org




Article: 27141
Subject: Spartan-II with 5V ISA bus
From: haydenso@my-deja.com
Date: Mon, 13 Nov 2000 03:04:30 GMT
Links: << >>  << T >>  << A >>
Hi All,

	I am working on a product that, for various reasons, is stuck with the
legacy ISA bus.  To what I know, ISA bus use a 5V signaling.  We used to
be using the old Altera Flex6k that has 5V I/O by default, so
implementing an ISA tranceiver is an obvious job.  Now that we want to
move forward and use the Spartan-II chip (or Altera ACEX), problems
come...

	All the FPGAs we are considering have 3.3V I/O, and are only "5V
tolerent".  Bridging the FPGA and the ISA BUS is not trivial (need to
drive, receive, PLUS tristate).  Take the Spartan-II as an example, all
the posting on this group has been talking about how a Spartan-II
(Virtex-E) communicates with 5V TTL level or 5V CMOS level devices.  The
bad news is it is "ok" to talk to TTL but not CMOS.  So in my situation,
because I am just plugging my card to a PC, I will have no clue what the
other end(s) are (namly, the ISA controller on MB, or other ISA devices
sharing the bus)...

	Anyone has any insight into this problem?  Anyone knows of any ISA
tranceiver chips out there that can talk to ISA bus on one hand and has
3.3V control on the other side?  Yes, I know implemening ISA protocol in
FPGA is easy, but if there is such tranceiver out there, we can probably
use it, esp for future migration to PCI bus (buying PCI core seems a bit
too expensive for our small startup so far...)



Hayden



Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 27142
Subject: OT but important
From: Nick <nkbrownKNOT@hotmail.com>
Date: Sun, 12 Nov 2000 23:10:01 -0500
Links: << >>  << T >>  << A >>
I know that most of you don't like off topic subjects. However, this is
important
Please check out http://www.votescam.com/frame.html


Article: 27143
Subject: Re: HOW TO TURN $6 INTO $6,000!!!!!!
From: John Larkin <jjlarkin@highlandSNIPTHIStechnology.com>
Date: Sun, 12 Nov 2000 20:17:29 -0800
Links: << >>  << T >>  << A >>
On 12 Nov 2000 22:27:36 GMT, woster145@aol.com (WOSTER145) wrote:

>HOW TO TURN $6 INTO $6,000!!!!!! 


Wait, wait! I think I know this one....

Yes, I have it! Just add $5994!

John

Article: 27144
Subject: Config device for Altera 10K10
From: V Ram <ipickeledthefigsmyself@mrbourns.com>
Date: Mon, 13 Nov 2000 07:33:47 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello!

I would like to find an ISP Serial EEPROM for an Altera 10K10. I currently
have a EPC1LC20, but that requires a seperate programmer. Altera does have
the EPC2 parts but they're pretty expensive (more expensive than the
FPGA!). Any alternatives?

I know Atmel makes parts that work with Xilinx/Altera, but they aren't
JTAG ISP. Would the Xilinx config PROMs work an Altera? I think they're
JTAG ISP... 

Any known working alternatives for the 10K10?

Thanks,
Vasant.

Article: 27145
Subject: Please guide newbies to real PLD ?
From: "Wisut Hantanong" <systemdesign@engineer.com>
Date: Mon, 13 Nov 2000 14:57:20 +0700
Links: << >>  << T >>  << A >>
I want to burn my own PLD (with my universal  programmer ALL 11 from
www.hilosystems.com ), How to begin ?
 I've got some *.vhd and abel  code. How to compile and program it?
Is there use HEX code like in eprom for microprocessor?
I have some vhdl skill, digital circuit design, I can use maxplusII program
from altera (vhdl design course in university but only done with  start
kit).
My first project is DRAM Controller form PAL device.I've get vhld code for
xilinx fpga.
Please tell me good introduction web.




Article: 27146
Subject: Re: Non routable design
From: "fred" <x@y.z>
Date: Mon, 13 Nov 2000 08:01:31 -0000
Links: << >>  << T >>  << A >>
Hi Tim,

Sorry, but I just thought it sounded a bit "have you tried
re-booting" if you know what I mean. I do realise you were
<are> on the right side :)

best,

Dave (fred)

As I re-read my reply
"Tim Jaynes" <tim.jaynes@xilinx.com> wrote in message
news:3A0C2663.DCED549A@xilinx.com...
> Fred,
> You'll note that the key to my arguement is the fact that
I recommended
> the customer contact our _free_ support service to verify
my suggestion.
>
> And it was just that- a suggestion.
> I'm not a salesman- just a support engineer, trying to
give people on
> this news group a hand when I can.
> Regards,
> Tim
>




Article: 27147
Subject: Re: Spartan-II with 5V ISA bus
From: "Harjo Otten" <h.otten@rohill.nospam.nl>
Date: Mon, 13 Nov 2000 09:07:00 +0100
Links: << >>  << T >>  << A >>
Dear Hayden,

We've recently finnished a design with a Spartan-II connected to the ISA
bus. We simply used a 74HCT245D with the /RD signal of the ISA bus to the
'direction' pin. No problem !

 H.

<haydenso@my-deja.com> wrote in message news:8unlnr$tk5$1@nnrp1.deja.com...
> Hi All,
>
> I am working on a product that, for various reasons, is stuck with the
> legacy ISA bus.  To what I know, ISA bus use a 5V signaling.  We used to
> be using the old Altera Flex6k that has 5V I/O by default, so
> implementing an ISA tranceiver is an obvious job.  Now that we want to
> move forward and use the Spartan-II chip (or Altera ACEX), problems
> come...
>
> All the FPGAs we are considering have 3.3V I/O, and are only "5V
> tolerent".  Bridging the FPGA and the ISA BUS is not trivial (need to
> drive, receive, PLUS tristate).  Take the Spartan-II as an example, all
> the posting on this group has been talking about how a Spartan-II
> (Virtex-E) communicates with 5V TTL level or 5V CMOS level devices.  The
> bad news is it is "ok" to talk to TTL but not CMOS.  So in my situation,
> because I am just plugging my card to a PC, I will have no clue what the
> other end(s) are (namly, the ISA controller on MB, or other ISA devices
> sharing the bus)...
>
> Anyone has any insight into this problem?  Anyone knows of any ISA
> tranceiver chips out there that can talk to ISA bus on one hand and has
> 3.3V control on the other side?  Yes, I know implemening ISA protocol in
> FPGA is easy, but if there is such tranceiver out there, we can probably
> use it, esp for future migration to PCI bus (buying PCI core seems a bit
> too expensive for our small startup so far...)
>
>
>
> Hayden
>
>
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



Article: 27148
Subject: Re: Spartan-II with 5V ISA bus
From: "fred" <x@y.z>
Date: Mon, 13 Nov 2000 08:20:15 -0000
Links: << >>  << T >>  << A >>

<haydenso@my-deja.com> wrote in message
news:8unlnr$tk5$1@nnrp1.deja.com...

<snip>
> use it, esp for future migration to PCI bus (buying PCI
core seems a bit
> too expensive for our small startup so far...)
Seen the latest pricing?
3month eval license, fully functional to bitstream level -
sale or return (apparently no strings)
Single use (single project) $1995.

Dave




Article: 27149
Subject: Re: Spartan-II with 5V ISA bus
From: Eric Smith <eric-no-spam-for-me@brouhaha.com>
Date: 13 Nov 2000 00:27:14 -0800
Links: << >>  << T >>  << A >>
haydenso@my-deja.com writes:
> the posting on this group has been talking about how a Spartan-II
> (Virtex-E) communicates with 5V TTL level or 5V CMOS level devices.  The
> bad news is it is "ok" to talk to TTL but not CMOS.  So in my situation,
> because I am just plugging my card to a PC, I will have no clue what the
> other end(s) are (namly, the ISA controller on MB, or other ISA devices
> sharing the bus)...

By definition, the ISA bus uses TTL levels.  The other end may be a
CMOS receiver, but it must have TTL thresholds.  So a 5V-tolerant FPGA
should be fine.

In more detail:  If 5V CMOS drives the bus high, the FPGA input will
be OK (if it's truly 5V-tolerant).  If the FPGA drives the bus high,
it will be over 2 volts, so receivers (CMOS or TTL) using TTL levels
will be satisfied.

However, the bigger problem to be considered is that proper bus drive
requires a lot of mA.  You may want to use an external bus transceiver
anyhow.  74FCT245 and the like should work fine.





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