Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 18350

Article: 18350
Subject: Re: Pull plug quickly!
From: Gary Helbig <"ghelbig"@mailcity(.)com>
Date: Sun, 17 Oct 1999 11:00:02 -0700
Links: << >>  << T >>  << A >>
Hi,

The "wrong" configuration probably turned an input into an output.

Xilinx seems to have a real high current limit on the output drivers -
driving into an off-chip output will make the chip get hot.

Gary.

alfred fuchs wrote:
> 
> FYI I want to state an observation, which I made this morning. Maybe
> people know that already.
> 
> I loaded the configuration file for a Virtex 1000 into a Virtex 400 and
> my LED (connected to DONE) indicated that the chip was properly
> configured. I started to caress the FPGA for that great feature
> (self-resizing bitstream!) when - oops! I burnt my fingers.
> 
> Is there an unknown cooker mode or did I accidentally activate the
> self-destruct option?
> I could not find an answer in the documentation (except that CRC seems
> to be checked only at the very end).
> Nevertheless IMHO that's b......t, an FPGA must never accept a
> configuration, which is not intended for it.
> 
> Alfred Fuchs
> Siemens Austria
Article: 18351
Subject: R: Reading a Lattice ispLSI 1016
From: Mark Harvey <mark.harvey@farsystems.it>
Date: Mon, 18 Oct 1999 08:04:37 +0200
Links: << >>  << T >>  << A >>
We are using the Lattice Daisychain download software ver 7.1  and this wil=
l
defintely read back a programmed device. From the 'Edit' menu, select 'Set
Operations', then 'Read & save'.

Bye,
Mark Harvey.

> -----Messaggio originale-----
> Da:=09X [SMTP:bureauc@hotmail.com]
> Inviato:=09gioved=EC 14 ottobre 1999 6.30
> A:=09comp.arch.fpga@list.deja.com
> Oggetto:=09Reading a Lattice ispLSI 1016
>=20
>  Message from the Deja.com forum:=20
>  comp.arch.fpga
>  Your subscription is set to individual email delivery
> >=20
> This may be a stupid question, but I'm pretty new to the PLD world, so
> here goes:
>=20
> Basically, I have a Lattice in-circuit programmable ispLSI 1016 that
> is not read-protected. I need to read it out and re-write it to
> another identical part in an updated board in order to test my circuit
> changes (to the board, not the PLD programming). The writing part is
> easy, as it's an in-circuit programmable part, and there is a program
> to do that through the PC parallel port on their website, however it
> doesn't seem to have any provisions for reading the chip.=20
>=20
> Thanks in advance.
>=20
> jds
>=20
>=20
>=20
>  _____________________________________________________________
>  Deja.com: Before you buy.
>  http://www.deja.com/
>  * To modify or remove your subscription, go to
>  http://www.deja.com/edit_sub.xp?group=3Dcomp.arch.fpga
>  * Read this thread at
>  http://www.deja.com/thread/%3C380557fd.2378434%40news.se.mediaone.net%3E


 Sent via Deja.com http://www.deja.com/
 Before you buy.
Article: 18352
Subject: Re: Virtex Board
From: gregorstellpflug@my-deja.com
Date: Mon, 18 Oct 1999 06:24:37 GMT
Links: << >>  << T >>  << A >>
Try: http://support.xilinx.com/techdocs/7022.htm


In article <UWdN3.2644$0G2.121324@typ12.nn.bcandid.com>,
  "abdulqadir alaqeeli" <alaqeeli@bobcat.ent.ohiou.edu> wrote:
> Hi,
> Does anyone know where I find a PCI Board with a Virtex Chip?
> I found the following two companies:
> Avnet:  http://www.em.avnet.com/semi/marketing/xlx-19990526semw.html
> Embedded Solutions Ltd  ( RC1000-PP)
>
> I need any helpful information so I can choose a good board.
>
> Abdul
>
>


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18353
Subject: PREP benchmarks
From: knowak@natlab.research.philips.com
Date: Mon, 18 Oct 1999 08:32:29 GMT
Links: << >>  << T >>  << A >>
Hello everybody !

Does someone know something about moving a Web page of the PREP
organization offering FPGA benchmarks to some other place ? My trials to
contact http://www.prep.org have failed (all the time infomation about
the lack of the DNS entry occurs). Where could I find a source code and
description of the mentioned benchmarks ?

Are there any other good benchmark sets for testing FPGAs ?

Thank you in advance for your help.

Kasia Nowak,
Philips Research.


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18354
Subject: Download Ia.n.i.!!! It's free!
From: madQ <madq968@djeksta.comNOSPAM>
Date: 18 Oct 1999 09:32:28 GMT
Links: << >>  << T >>  << A >>

Download Ia.n.i. RemoteControlSystem 1.2 beta. It's free!!!
New site: http://jump.to/IaniProject

Article: 18355
Subject: Re: SRAM FPGA with hardwired 40 MHz AVR RISC processor, memory and peripherals
From: "David Brown" <david.nospam@westcontrol.com>
Date: Mon, 18 Oct 1999 11:59:06 +0200
Links: << >>  << T >>  << A >>
Any ideas as to when this will be available?

Ulf Samuelsson wrote in message ...
>If someone want to have a look at the FPSLIC,
>The FPGA+40 Mhz AVR RISC+Peripherals + Memory chip
>under development at Atmel, Here's the link:
>http://www.atmel.com/atmel/products/prod39.htm
>
>--
>This is a personal view which may or may not be shared
>by my employer         Atmel Sweden
>Ulf Samuelsson         ulf 'a't atmel 'd'o't com
>
>
>
>
>


Article: 18356
Subject: free Online ASIC course
From: Jamil Khaib <Khatib@ieee.org>
Date: Mon, 18 Oct 1999 13:38:45 +0200
Links: << >>  << T >>  << A >>
Free ASIC course from synopsys is available online at

http://www.dacafe.com/DACafe/ASICCOURSE/

use this referral ID when you register IC6916

Jamil Khatib
OpenIP Organization
http://www.openip.org

Article: 18357
Subject: Best FPGA for PCI ?
From: Nicolas Matringe <nicolas@dotcom.fr>
Date: Mon, 18 Oct 1999 14:04:25 +0200
Links: << >>  << T >>  << A >>
Hi all

I remember some discussions about this topic. I thought I had read that
the best chips were Lucent's and Xilinx's but I can't find the message
in Deja News... I can't even find a thread that looks like a comparison.
If someone could give me some hints...

Thanks in advance,
Nicolas MATRINGE           DotCom S.A.
Conception electronique    16 rue du Moulin des Bruyeres
Tel 00 33 1 46 67 51 11    92400 COURBEVOIE
Fax 00 33 1 46 67 51 01    FRANCE
Article: 18358
Subject: Re: PREP benchmarks
From: Brad Ree <brad.ree@programmable-products.com>
Date: Mon, 18 Oct 1999 10:39:19 -0400
Links: << >>  << T >>  << A >>
Now theres a name I haven't herd for a while.  I do not know if they are
still around, but I would have to ask why you would want to find them.  The
benchmarks were extremely flawed.  First, they were based on how many of the
same circuit could be fit into a FPGA.  Second, they did not run the test
themselves, but had the vendors run them.  The problem is that you almost
never have a large design with all the same thing in them.  For example, one
benchmark was based on the number of counters you could fit in the deisgn.
But the real world includes both counters and decoders.  Also, there were
rumers that the vendors would optimize there compilers/routers to be
optimized for one or two of the benchmarks.  The question also was how much
hand optimization was needed to meet the factory benchmark.  After reveiwing
some of the results from PREP, you would find that several vendors were
number 1.  This is true since each vendor's arch. excells with different
applications.

Also, the numbers released from vendors is very misleading.  For example,
Xilinx used to say that Altera's numbers were much larger than they should
be since Altera counted the block RAM as useable gates, but not all designs
used the RAM.  At that time Xilinx only had distributed RAM, and thus the
RAM was either logic or Memory.  Therefore, in a large RAM design, Altera's
numbers were real.  But in a logic only design, Xilinx numbers are real.
However, Xilinx has changed their measurements now that they actually have
both block RAM and distributed RAM.  Now Xilinx numbers are bigger than they
really should be for most designs.

Conclusion: Trust nobodies numbers, but your own.  Analyze the basic
building blocks and see what works best for your application.  You may even
choose a part which is less than optimal, but your company already uses a
lot of them in other designs, and thus the price is better.  If you are a
FPGA manufacture, don't let the marketing folks advertise only the best
case.

knowak@natlab.research.philips.com wrote:

> Hello everybody !
>
> Does someone know something about moving a Web page of the PREP
> organization offering FPGA benchmarks to some other place ? My trials to
> contact http://www.prep.org have failed (all the time infomation about
> the lack of the DNS entry occurs). Where could I find a source code and
> description of the mentioned benchmarks ?
>
> Are there any other good benchmark sets for testing FPGAs ?
>
> Thank you in advance for your help.
>
> Kasia Nowak,
> Philips Research.
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.

Article: 18359
Subject: listing of discretes and list of wafer fabs in US
From: htytus@shell1.iglou.com (Hul Tytus)
Date: 19 Oct 1999 06:09:39 -0500
Links: << >>  << T >>  << A >>
comp.arch.fpgalisting of discretes and list of wafer fabs in US	A couple of questions - 	First, does anyone know of a book with a listing of discrete diodes and transisters for both the Japenese and US devices (2SC..., 2n...., etc.) There have been listings published in the past with just a line of data (Ft, beta, max current, etc.) for each device. 	Second, anyone know of a listing of wafer fabs in the US? The address to a web site with this information or a current book with this data in an ancilary fashion would be fine. Both silicon & GaAr facilities are of interest.Hul		hytuts@iglou.comPath: mindspring!news.mindspring.net!firehose.mindspring.net!news.maxwell.syr.edu!nntp2.deja.com!nnrp1.deja.com!not-for-mail
Article: 18360
Subject: ANNOUNCE: FPGA Starter kit
From: bruno <bruno18@my-deja.com>
Date: Tue, 19 Oct 1999 11:40:14 GMT
Links: << >>  << T >>  << A >>
Hello all,

Just thought you'd like to know about the new FPGA starter kit.

Its a complete development environment introducing FPGA. The kit
provides Industry and Academia with a wealth of VHDL examples* providing
a wide range of projects based around the 40K ATMEL device family. For
more details visit http://www.kanda.com.

Bye

Bryan

*Full version only


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18361
Subject: Question on Jbits(Xilinx product) for Xc4000 series
From: prastogi@my-deja.com
Date: Tue, 19 Oct 1999 13:30:44 GMT
Links: << >>  << T >>  << A >>
Jbits is a Java based Interface to the XC4000 series of FPGAs and allows
the developer to modify the bitstream directly and even try his own PPR.

I have been going through the Jbits example files in the Jbits package
for XC4000 Series. Is it possible to interactively input values into the
Circuit once the bitstream is downloaded using the Jbits interface??
From what I can make out , we will need to supply initial values to the
cores (or bitstream, if handcrafted) and get the result. Then to change
them, use some new values & reconfigure all over again. This seems to be
a costly thing to do as the circuit is sitting on the FPGA once
downloaded. May be there is some interface with IOBs that I am missing.
There is one class that helps interact with IOBs so that I/O may be
possible but there are no examples given. Octal Routing around the FPGA
is also not supported. i.e. API are not available for it.

If someone has played around with Jbits and is aware of this particular
problem, please reply.

Thank you,
Pranav Rastogi
Research Assist.
University of Cincinnati


Sent via Deja.com http://www.deja.com/
Before you buy.
Article: 18362
Subject: Re: Question on Jbits(Xilinx product) for Xc4000 series
From: Ray Andraka <randraka@ids.net>
Date: Tue, 19 Oct 1999 09:55:57 -0400
Links: << >>  << T >>  << A >>
What you seem to be looking for is partial reconfiguration.  The 4K families
do not support that.  Once a bit stream is in the device, there is no way to
modify it because the download is an all or nothing proposition.

prastogi@my-deja.com wrote:

> Jbits is a Java based Interface to the XC4000 series of FPGAs and allows
> the developer to modify the bitstream directly and even try his own PPR.
>
> I have been going through the Jbits example files in the Jbits package
> for XC4000 Series. Is it possible to interactively input values into the
> Circuit once the bitstream is downloaded using the Jbits interface??
> From what I can make out , we will need to supply initial values to the
> cores (or bitstream, if handcrafted) and get the result. Then to change
> them, use some new values & reconfigure all over again. This seems to be
> a costly thing to do as the circuit is sitting on the FPGA once
> downloaded. May be there is some interface with IOBs that I am missing.
> There is one class that helps interact with IOBs so that I/O may be
> possible but there are no examples given. Octal Routing around the FPGA
> is also not supported. i.e. API are not available for it.
>
> If someone has played around with Jbits and is aware of this particular
> problem, please reply.
>
> Thank you,
> Pranav Rastogi
> Research Assist.
> University of Cincinnati
>
> Sent via Deja.com http://www.deja.com/
> Before you buy.



--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://users.ids.net/~randraka


Article: 18363
Subject: Virtex Readback
From: "Gordon Hollingworth" <gsh100@NOSPAMyork.ac.uk>
Date: Tue, 19 Oct 1999 15:12:28 +0100
Links: << >>  << T >>  << A >>
Hi,

I've succesfully implemented a SelectMAP interface to the Virtex chip and
can quickly reconfigure the chip no problem.  When I come to readback I send
the correct commands (copied directly from the xilinx datasheet!) and when i
read all I get is 0xff, 0xf3, 0xf1, 0xf9, 0xf9, 0xf9 ....... for 207900
bytes (V300)

No matter what I do it doesn't seem to help, I originally assumed the bus
was floating and the above was the results of this, but when I look at the
bus it is being driven by these values!!!

Help

Gordon


Article: 18364
Subject: New to FPGA
From: Greg Vanslyke <gvanslyk@is2.dal.ca>
Date: Tue, 19 Oct 1999 13:20:56 -0300
Links: << >>  << T >>  << A >>

I'm a third year electrical engineering student about to venture on my
first of three co-op work terms.  Many of the jobs I've been applying for
may require me to work with/test/design FGPAs.  Basically all I  know is 
that FPGA stands for Field Programmable Gate Array and I have a vague
understanding of what they are used for.  

Can somebody recommend a website, book, newsgroup, etc.  that I can use to
learn the very basics on FPGAs ?

  
Greg VanSlyke
Elec3 DalTech
gvanslyk@is2.dal.ca


Article: 18365
Subject: Re: New to FPGA
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Tue, 19 Oct 1999 09:29:09 -0700
Links: << >>  << T >>  << A >>
I'd like to suggest The Programmable Logic Jump Station at
http://www.optimagic.com/index.shtml.  Specifically, you may want to go
through the FAQ section, which is slightly out of date but covers all the
right ideas.

There are also listings for

* books (http://www.optimagic.com/books.html),
* newsgroups (http://www.optimagic.com/newsgroups.html), and even
* free or low-cost FPGA software (http://www.optimagic.com/lowcost.shtml)

and a host of other FPGA-related topics.

FPGA-related experience is always a good thing to have on your resume or
C.V.
--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------


Greg Vanslyke <gvanslyk@is2.dal.ca> wrote in message
news:Pine.A41.3.95.991019131224.74538B-100000@is2.dal.ca...
>
> I'm a third year electrical engineering student about to venture on my
> first of three co-op work terms.  Many of the jobs I've been applying for
> may require me to work with/test/design FGPAs.  Basically all I  know is
> that FPGA stands for Field Programmable Gate Array and I have a vague
> understanding of what they are used for.
>
> Can somebody recommend a website, book, newsgroup, etc.  that I can use to
> learn the very basics on FPGAs ?
>
>
> Greg VanSlyke
> Elec3 DalTech
> gvanslyk@is2.dal.ca
>
>


Article: 18366
Subject: Re: New to FPGA
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 19 Oct 1999 17:59:09 -0400
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------C311BDC906FB4DA64A6892B3
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Greg:

We offer low-cost Xilinx FPGA-based development systems with tutorials.  Take a look at http://www.xess.com.  We also have an email forum for people who use our boards.



Greg Vanslyke wrote:

> I'm a third year electrical engineering student about to venture on my
> first of three co-op work terms.  Many of the jobs I've been applying for
> may require me to work with/test/design FGPAs.  Basically all I  know is
> that FPGA stands for Field Programmable Gate Array and I have a vague
> understanding of what they are used for.
>
> Can somebody recommend a website, book, newsgroup, etc.  that I can use to
> learn the very basics on FPGAs ?
>
>
> Greg VanSlyke
> Elec3 DalTech
> gvanslyk@is2.dal.ca

--------------C311BDC906FB4DA64A6892B3
Content-Type: text/x-vcard; charset=us-ascii;
 name="devb.vcf"
Content-Transfer-Encoding: 7bit
Content-Description: Card for Dave Vanden Bout
Content-Disposition: attachment;
 filename="devb.vcf"

begin:vcard 
n:Vanden Bout;David
tel;fax:(919) 387-1302
tel;work:(919) 387-0076
x-mozilla-html:FALSE
url:http://www.xess.com
org:XESS Corp.
adr:;;2608 Sweetgum Drive;Apex;NC;27502;USA
version:2.1
email;internet:devb@xess.com
title:FPGA Product Manager
x-mozilla-cpt:;28560
fn:Dave Vanden Bout
end:vcard

--------------C311BDC906FB4DA64A6892B3--

Article: 18367
Subject: Re: New to FPGA
From: jjlarkin@highlandSnipSniptechnology.com (John Larkin)
Date: Wed, 20 Oct 1999 02:49:30 GMT
Links: << >>  << T >>  << A >>
On Tue, 19 Oct 1999 13:20:56 -0300, Greg Vanslyke
<gvanslyk@is2.dal.ca> wrote:

|
|I'm a third year electrical engineering student about to venture on my
|first of three co-op work terms.  Many of the jobs I've been applying for
|may require me to work with/test/design FGPAs.  Basically all I  know is 
|that FPGA stands for Field Programmable Gate Array and I have a vague
|understanding of what they are used for.  
|
|Can somebody recommend a website, book, newsgroup, etc.  that I can use to
|learn the very basics on FPGAs ?
|
|  
|Greg VanSlyke
|Elec3 DalTech
|gvanslyk@is2.dal.ca
|
|

Greg,

The Xilinx Foundation student edition software is pretty good. $99
from Amazon, I believe. It's the same stuff we use, but limited to the
less-than-huge chips.

John

Article: 18368
Subject: load VIRTEX via JTAG
From: "G. Brandenburg" <g.brandenburg@fz-juelich.de>
Date: Wed, 20 Oct 1999 11:01:35 +0200
Links: << >>  << T >>  << A >>
hello
i can not load VIRTEX via JTAG  XCHECKER
i connect TDI TCK TMS always i got theERROR message after start BIT 4 ERROR
on BSCAN
have anybody i tip to solve that problem
thanks

--

    mit freundlichen Gruessen
                __o
              _`\<,_
             (_)/  (_)

    Dipl-Ing G.Brandenburg

    Forschungszentrum Juelich GmbH
    Zentrallabor fuer Elektronik (ZEL)
    Postfach 1913
    D-52425 Juelich, Germany

    Tel     :  (+49)2461 61 5575
             :  (+49)2461 61 5267
    FAX   :  (+49)2461 61 3990
    EMail :  g.brandenburg@fz-juelich.de


Article: 18369
Subject: Re: Interconnecting LUTs on a Virtex
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Oct 1999 09:22:16 GMT
Links: << >>  << T >>  << A >>
On 16 Oct 1999 06:46:37 PDT, Ken McElvain <ken@synplicity.com> wrote:

>The way Ray did it you can simulate.  With your Expr generic method, you
>can't .  A
>compromise is to instantiate the luts directly with the LUT contents as bit
>string generic.
>It is more cryptic but you can simulate it.

agreed; as minor additions, it's worth remembering that:

1) the bit_vector generic doesn't have to be specified directly - one
trick i use is to instead specify an attribute of the component, and
then to use a function elsewhere to calculate a value for the
attribute. this can make the INIT specification a lot more usable. if
you're careful, the function can be arbitrarily complex; it's
effectively treated as a compile-time constant calculation by the
synthesiser. i'm not suggesting that you can turn an EQN into the INIT
value directly, but it may be possible.

2) some synths can have a problem with the INIT specification, so you
need a metacomment to comment out the generic map aspect.

here's an example which i use frequently on another synth (not yours
:)). it's in a 2-level generate, where the INT_INIT attribute is
calculated by a function which turns a set of filter coefficients into
a 16-bit integer to load into a rom element:

      UX : LUT4
-- pragma translate_off
        -- required only for the xilinx simulation model; not in the
        -- synthesisable component
        generic map (
          INIT => bit_vector(to_unsigned(UX'INT_INIT, 16)))
-- pragma translate_on
        port map (
        I0 => ADDR(i*4),   I1 => ADDR(i*4+1),
        I2 => ADDR(i*4+2), I3 => ADDR(i*4+3),
        O  => DATA(i)(j));

evan
Article: 18370
Subject: Seeking for FPGA/CPLD (Starter) kit
From: Marek Ponca <marek.ponca@et.stud.tu-ilmenau.de>
Date: Wed, 20 Oct 1999 12:43:51 +0200
Links: << >>  << T >>  << A >>
Hi,

Hope, that some FPGA expert will spend a minute with this...


I want to lear-try something more about programming and synthesizing 
to programmable logic devices.

Can You recommend some tool (for VHDL synthesis), some design board
(starter kit) ?
(FPGA and CPLD boards too) 

Are there some known problems (especially for beginners) with specific
chips ?


Thanks 


-- 

 Marek Ponca
 
 
 Fak. der Elektrotechnik und Informatik
 FG Mikroelektronische Schaltungen ud Systeme 
 TU Ilmenau
 PF 10 05 65
 986 84 Ilmenau 
 Deutschland

 Tel: 0049 3677 69 1168
 Fax: 0049 3677 69 1163
Article: 18371
Subject: Opportunities for HDL specialists NOW
From: Ops <***ops@doulos.com>
Date: Wed, 20 Oct 1999 14:26:23 +0100
Links: << >>  << T >>  << A >>
Due to continued growth in established and new markets; Doulos, the HDL
Training Company and its partner companies have immediate opportunities
for HDL specialists in the following countries: USA, UK, France, Sweden
and Germany.

If you are skilled in the application of HDLs and enjoy passing on those 
skills, then find out more about these opportunities at www.doulos.com
or email ops@doulos.com

To replay by e-mail remove the *** before the e-mail address
-- 
DOULOS

Church Hatch  22 Market Place  Ringwood  BH24 1AW  Hampshire  UK

Tel: +44 1425 471 223  Fax:  +44 1425 471 573
Email: ***ops@doulos.com  Web:  www.doulos.com

                **   VISIT THE WINNING EDGE     **
                        www.doulos.com
                    for many TIPS and MODELS
                **    for VHDL and Verilog      **      
Article: 18372
Subject: Re: Interconnecting LUTs on a Virtex
From: eml@riverside-machines.com.NOSPAM
Date: Wed, 20 Oct 1999 15:02:49 GMT
Links: << >>  << T >>  << A >>
On Wed, 20 Oct 1999 09:22:16 GMT, eml@riverside-machines.com.NOSPAM
wrote:

>On 16 Oct 1999 06:46:37 PDT, Ken McElvain <ken@synplicity.com> wrote:
>
>>The way Ray did it you can simulate.  With your Expr generic method, you
>>can't .  A
>>compromise is to instantiate the luts directly with the LUT contents as bit
>>string generic.
>>It is more cryptic but you can simulate it.
>
>agreed; as minor additions, it's worth remembering that:
> <snipped>

i must have had brain fade when i wrote this. i can't (yet...?) see
any reason why you can't do RTL simulation on FMAP/EQNs (apart from
the obvious, of course, which is that xilinx doesn't provide the
unisim models). you'd have to add the EQN attribute as a generic to
the EQN entity, and then parse the generic to extract the
functionality. you'd also need to 'translate_off' the generic map
aspect as per my last example, or you wouldn't be able to synthesise
it. presumably simon is already doing this.

evan

Article: 18373
Subject: Re: Seeking for FPGA/CPLD (Starter) kit
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 20 Oct 1999 09:24:14 -0700
Links: << >>  << T >>  << A >>
I have a couple of recommendations.  First, The Programmable Logic Jump
Station at http://www.optimagic.com is a good source for most topics related
to programmable logic.

There is a section that lists various free or low-cost software packages at
http://www.optimagic.com/lowcost.shtml.  Most of these packages do include
design examples and documentation.

Also, there is a list of various development boards, including pre-packages
starter kits at http://www.optimagic.com/boards.html.

For learning VHDL and Verilog, there is a list of tutorials at
http://www.optimagic.com/tutorials.html.

Finally, there is a general Frequently Asked Questions section at
http://www.optimagic.com/faq.html.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Marek Ponca <marek.ponca@et.stud.tu-ilmenau.de> wrote in message
news:380D9CE7.E6A74234@et.stud.tu-ilmenau.de...
> Hi,
>
> Hope, that some FPGA expert will spend a minute with this...
>
>
> I want to lear-try something more about programming and synthesizing
> to programmable logic devices.
>
> Can You recommend some tool (for VHDL synthesis), some design board
> (starter kit) ?
> (FPGA and CPLD boards too)
>
> Are there some known problems (especially for beginners) with specific
> chips ?
>
>
> Thanks
>
>
> --
>
>  Marek Ponca
>
>
>  Fak. der Elektrotechnik und Informatik
>  FG Mikroelektronische Schaltungen ud Systeme
>  TU Ilmenau
>  PF 10 05 65
>  986 84 Ilmenau
>  Deutschland
>
>  Tel: 0049 3677 69 1168
>  Fax: 0049 3677 69 1163


Article: 18374
Subject: Re: Seeking for FPGA/CPLD (Starter) kit
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: Wed, 20 Oct 1999 09:26:55 -0700
Links: << >>  << T >>  << A >>
I have a couple of recommendations.  First, The Programmable Logic Jump
Station at http://www.optimagic.com is a good source for most topics related
to programmable logic.

There is a section that lists various free or low-cost software packages at
http://www.optimagic.com/lowcost.shtml.  Most of these packages do include
design examples and documentation.

Also, there is a list of various development boards, including pre-packages
starter kits at http://www.optimagic.com/boards.html.

For learning VHDL and Verilog, there is a list of tutorials at
http://www.optimagic.com/tutorials.html.

Finally, there is a general Frequently Asked Questions section at
http://www.optimagic.com/faq.html.

Lastly, you can find a series of related books at
http://www.optimagic.com/books.html.  You might investigate the Xilinx
Student Edition as a good place to start.  It comes with software.


--
-----------------------------------------------------------
Steven K. Knapp
OptiMagic, Inc. -- "Great Designs Happen 'OptiMagic'-ally"
E-mail:  sknapp@optimagic.com
   Web:  http://www.optimagic.com
-----------------------------------------------------------



Marek Ponca <marek.ponca@et.stud.tu-ilmenau.de> wrote in message
news:380D9CE7.E6A74234@et.stud.tu-ilmenau.de...
> Hi,
>
> Hope, that some FPGA expert will spend a minute with this...
>
>
> I want to lear-try something more about programming and synthesizing
> to programmable logic devices.
>
> Can You recommend some tool (for VHDL synthesis), some design board
> (starter kit) ?
> (FPGA and CPLD boards too)
>
> Are there some known problems (especially for beginners) with specific
> chips ?
>
>
> Thanks
>
>
> --
>
>  Marek Ponca
>
>
>  Fak. der Elektrotechnik und Informatik
>  FG Mikroelektronische Schaltungen ud Systeme
>  TU Ilmenau
>  PF 10 05 65
>  986 84 Ilmenau
>  Deutschland
>
>  Tel: 0049 3677 69 1168
>  Fax: 0049 3677 69 1163






Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search