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Messages from 28825

Article: 28825
Subject: Re: Advice on FPGA board.
From: Sylvia Tam <sylvia@triscend.com>
Date: Thu, 25 Jan 2001 09:23:21 -0800
Links: << >>  << T >>  << A >>
You might want to try http://www.xess.com. They offer programmable
logic-based development systems for academic use.

jimmy75@my-deja.com wrote:

> Hi Folks,
>
> We have a student project in which it is required to implement some
> image processing operations (e.g. filtering) on an FPGA based board
> connected to a PC. The aim is to assess the suitability of FPGAs in
> Desktop publishing. We still have to decide on the FPGA board to be
> used. We want an FPGA board with a DMA module on board to speed up data
> transfer from host memory to on-board memory. Could you please advice
> us on a commercial FPGA board to purchase??
>
> Cheers,
>
> PS. Our purchase budget is 3000$
>
> Sent via Deja.com
> http://www.deja.com/

--

--------------------------------------------------------------------------------

Sylvia Tam
Triscend Corporation
301 N. Whisman Rd.
Mountain View, CA  94043  USA
TEL: 650-968-8668 x-144, FAX: 650-934-9389
sylvia@triscend.com, http://www.triscend.com

        /\      Triscend Corporation
    /\/   \     Configurable System-on-Chip for Communications
 /\/ /     \
/ / /       \
--------------------------------------------------------------------------------




Article: 28826
Subject: Re: Encryption is supported in new Virtex II but.....
From: Falk Brunner <Falk.Brunner@gmx.de>
Date: Thu, 25 Jan 2001 18:58:27 +0100
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:
> 
> The internal back-up memory in Virtex-II consumes 100 ( really 1000 ) times
> less current, and consumes this current only when Vcc is not present.

Why not using wrist watch technology like solar cells / automatic drive
to charge a rechargable battery or a super cap when the power is off . .
. ;-)))

-- 
MFG
Falk

Article: 28827
Subject: Re: really fast counter in SpartanXL?
From: "Scott Taylor" <staylor@dspsystems.com>
Date: Thu, 25 Jan 2001 10:01:14 -0800
Links: << >>  << T >>  << A >>
Does anyone have an example of a ripple counter in VHDL? I need to divide a 100MHz clock down to under 10Hz (non-critical). I only need the final output. No intermediate stages will be used for any purpose.

Thanks.
Article: 28828
Subject: Re: Advice on FPGA board.
From: Dave Vanden Bout <devb@xess.com>
Date: Thu, 25 Jan 2001 13:19:25 -0500
Links: << >>  << T >>  << A >>
> You might want to try http://www.xess.com. They offer programmable
> logic-based development systems for academic use.

None of our boards will fit this particular application.  A board with a PCI bus
interace is needed for the high-speed transfers between the FPGA board memory and
the PC running the desktop publishing app.  All our boards interface through the
parallel port which is too slow for this type of application.

>
>
> jimmy75@my-deja.com wrote:
>
> > Hi Folks,
> >
> > We have a student project in which it is required to implement some
> > image processing operations (e.g. filtering) on an FPGA based board
> > connected to a PC. The aim is to assess the suitability of FPGAs in
> > Desktop publishing. We still have to decide on the FPGA board to be
> > used. We want an FPGA board with a DMA module on board to speed up data
> > transfer from host memory to on-board memory. Could you please advice
> > us on a commercial FPGA board to purchase??
> >
> > Cheers,
> >
> > PS. Our purchase budget is 3000$
> >
> > Sent via Deja.com
> > http://www.deja.com/
>
> --
>
> --------------------------------------------------------------------------------
>
> Sylvia Tam
> Triscend Corporation
> 301 N. Whisman Rd.
> Mountain View, CA  94043  USA
> TEL: 650-968-8668 x-144, FAX: 650-934-9389
> sylvia@triscend.com, http://www.triscend.com
>
>         /\      Triscend Corporation
>     /\/   \     Configurable System-on-Chip for Communications
>  /\/ /     \
> / / /       \
> --------------------------------------------------------------------------------

--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 28829
Subject: Re: xilinx cpld
From: Leon Heller <leon_heller@hotmail.com>
Date: Thu, 25 Jan 2001 18:22:32 GMT
Links: << >>  << T >>  << A >>
In article <94klb4$ev3$1@eol.dd.chalmers.se>,
  "Daniel Nilsson" <danielnilsson@REMOVE_THIShem3.passagen.se> wrote:
> Hi.
> I´have just got my jtag programmer functioning, and now I want to test
> something simple with it.
> I am completely new to programmable logic, so I need some info about
how to
> connect it... I guess I will need a global clock, but what else will
I need?
> All I want to do is get some led's blinking. My device is a xilinx
XC9572
> PC44.

I've got something simple for the 9536 on my web site.

Leon


--
Leon Heller, G1HSM Email: leon_heller@hotmail.com
Tel: (Home) +44 1327 359058 (Work) +44 1327 357824
Work WWW: http://www.irisys.co.uk
Personal WWW: http://www.geocities.com/leon_heller


Sent via Deja.com
http://www.deja.com/

Article: 28830
Subject: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
From: Newsbrowser@Newsbrowser.com (Newsbrowser)
Date: Thu, 25 Jan 2001 20:32:33 GMT
Links: << >>  << T >>  << A >>
This compilation takes a loooooooooooong time. 

It stalls at  the compilation of a dual port 2048x12 sram. 

I have a feeling that this software is going through creating this
memory 1 cell at a time. 

Anybody know how to speed things up. 

I run a script everytime that goes through and compiles all of the
vhdl code every time.


Ralph Watson 
Return Email Address is: 
ralphwat dot home at excite dot com 
just type the address in like it should look like

Article: 28831
Subject: Re: Encryption is supported in new Virtex II but.....
From: "Simon Bacon" <simonb@tile.demon.co.cuthis.uk.>
Date: Thu, 25 Jan 2001 20:37:04 -0000
Links: << >>  << T >>  << A >>
Is there an integrated solution which will do the whole
job - charge the cell/battery, prevent overcharging, regulate
output?

For extra credit it could flag when the cell/battery is getting
low and even provide a few bytes of RAM.





Article: 28832
Subject: Re: XC7272 vers XC9272.
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 25 Jan 2001 14:05:27 -0700
Links: << >>  << T >>  << A >>
RDR wrote:
> 
> Bonjour,
> 
>         Y a t il  une demarche particuliere pour porter un design de xc7272
> vers xc9272 ?
>         Y a t il des pin a double utilisation (exple : jtag)?
>         Y a t il un "convertisseur", une "passerelle" pour convertir les
> fichiers de l'un vers l'autre?

My French is very limited, but what I think he's saying is: what's
involved with porting a 7272 design to the 9572?

I keep thinking about porting some 7372 designs to the 9572, and it's
mostly pin compatible (power-supply pins are in the same place, so are
global clock pins, etc.) but the JTAG pins must be used for JTAG only,
so you're hosed if the previous design used the JTAG pins for regular
I/O.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28833
Subject: Re: Encryption is supported in new Virtex II but.....
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 25 Jan 2001 14:07:21 -0700
Links: << >>  << T >>  << A >>
Austin Lesea wrote:
> 
> Dan,
> 
> They fall out of their sockets.  They are heavy.
> 
> Never let an electronic engineer design the mechanics.

Never let a mechanical engineer design the electronics.

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28834
Subject: Re: Encryption is supported in new Virtex II but.....
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Thu, 25 Jan 2001 14:09:21 -0700
Links: << >>  << T >>  << A >>
Falk Brunner wrote:
> 
> Peter Alfke schrieb:
> >
> > The internal back-up memory in Virtex-II consumes 100 ( really 1000 ) times
> > less current, and consumes this current only when Vcc is not present.
> 
> Why not using wrist watch technology like solar cells / automatic drive
> to charge a rechargable battery or a super cap when the power is off . .
> . ;-)))

Oh, you electrical engineers always think things have to have
electricity to be useful!  Such narrowmindedness and always unwilling to
"think outside the box!"

I've got a Seiko automatic (self-winding) jewelled-movement watch.  Very
nice.  No batteries, no winding.  Doesn't die since I wear it all the
time.

Nope, it's not one of the "kinetic" watches, either.

-- andy
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

"It is better to be silent and thought a fool, 
 than to send an e-mail to the entire company
 and remove all doubt."

Article: 28835
Subject: Re: Advice on FPGA board.
From: jimmy75@my-deja.com
Date: Thu, 25 Jan 2001 23:27:00 GMT
Links: << >>  << T >>  << A >>

> None of our boards will fit this particular application.  A board
> with a PCI bus interace is needed for the high-speed transfers
> between the FPGA board memory and the PC running the desktop
> publishing app.  All our boards interface through the
> parallel port which is too slow for this type of application.

Yep. We need a PCI board for our purpose preferably with a DMA
controller and a Xilinx Virtex chip(s) and lots of memory. If only we
could make one on our own!
I had a look on the web and didn't find all these features altogether
in one board. We were hoping that somebody out there could help us.

-- Jim


Sent via Deja.com
http://www.deja.com/

Article: 28836
Subject: Re: looping and ranges
From: Paul Campbell <paul@verifarm.com>
Date: Fri, 26 Jan 2001 00:08:30 +0000
Links: << >>  << T >>  << A >>
Rick Collins wrote:

> So I wanted to change it to a loop, like this.
> 
> integer j;
> 
> always @(bar)
>   for (j=1; j<14; j=j+1)
>     foo[j] <= bar[423-((13-j)*8):423-((13-j)*8)-7];
> 
> The ModelSim simulator compiler complains that the range of bar has to
> be a constant. A coworker tells me that the real problem is that verilog
> won't let you use a loop variable in a range while it will let you use
> the loop variable for a single array element.
> 
> So I wanted to try a different approach where I use the loop variable to
> assign the bits one at a time, but I could not figure out how to refer
> to the individual bits of foo[j]. foo[j][k] did not work.

OK - there are two problems here (both solved in Verilog 2000 by the way).

1) you can't index a range of a vector, just a bit (basicly because the 
size of the result has to be fixed at compile time for the compiler)

2) you can't both index an array of vectors and a bit from it at the same 
time

Anyway while you're waiting for v2k what you can do is variable bit indexes 
and then concat them together:

        integer j;
        always @(bar)
                for (j = 1; j < 14; k=j+1)
                        foo[j] <= {bar[423-((13-j)*8)],
                                   bar[423-((13-j)*8)-1],
                                   bar[423-((13-j)*8)-2],
                                   bar[423-((13-j)*8)-3],
                                   bar[423-((13-j)*8)-4],
                                   bar[423-((13-j)*8)-5],
                                   bar[423-((13-j)*8)-6],
                                   bar[423-((13-j)*8)-7]};

not as pretty as you might like but it will get the job done

        Paul Campbell
        paul@verifarm.com



Article: 28837
Subject: choose device
From: "yaohan" <yaohan@tm.net.my>
Date: Fri, 26 Jan 2001 08:16:56 +0800
Links: << >>  << T >>  << A >>
Hi, i have to do a decision to choose between FGPA from
Altera or Xilinx. Is there any comparison or compilation of
specification for both company at one place.
What is your opinion for their devices?
Thank you.

regards,
yaohan.



Article: 28838
Subject: Re: really fast counter in SpartanXL?
From: Peter Alfke <peter.alfke@xilinx.com>
Date: Thu, 25 Jan 2001 16:20:45 -0800
Links: << >>  << T >>  << A >>


Scott Taylor wrote:

> Does anyone have an example of a ripple counter in VHDL? I need to divide a 100MHz clock down to under 10Hz (non-critical). I only need the final output. No intermediate stages will be used for any purpose.
>

Simplest and lowest-power solution:
2-bit Johnson counter ( 2-bit shift register ring with one inversion) in each slice.
Cascaded by having one of the two Qs being the clock of the next. You need 24 bits = 12 slices.
I am not the source for VHDL.

Peter Alfke


Article: 28839
Subject: Re: Advice on FPGA board.
From: NO3ackNnak5SPAM@7hotmail.com (-ackNnak-)
Date: Fri, 26 Jan 2001 01:34:22 GMT
Links: << >>  << T >>  << A >>
I just attended the Xilinx "Xtreme DSP" seminar introducing the
Virtex-II architecture and applications for DSP.  With the new
integral 18x18 multiplier blocks in the logic fabric they claim the
largest part (~10M gates) could perform 600 billion (8x8)MAC's/sec.
It also incorporates what they call "SelectIO" which appears to
support just about any IO type under the sun.  Couple that with the
digitally controlled out impedance blocks and your board with a single
FPGA.  You could probably piece together a good bit of it from the
free "LogiCore" IP.   No, I don't work for Xilinx.

-Noel


On Thu, 25 Jan 2001 23:27:00 GMT, jimmy75@my-deja.com wrote:

>
>> None of our boards will fit this particular application.  A board
>> with a PCI bus interace is needed for the high-speed transfers
>> between the FPGA board memory and the PC running the desktop
>> publishing app.  All our boards interface through the
>> parallel port which is too slow for this type of application.
>
>Yep. We need a PCI board for our purpose preferably with a DMA
>controller and a Xilinx Virtex chip(s) and lots of memory. If only we
>could make one on our own!
>I had a look on the web and didn't find all these features altogether
>in one board. We were hoping that somebody out there could help us.
>
>-- Jim
>
>
>Sent via Deja.com
>http://www.deja.com/


Article: 28840
Subject: Re: Encryption is supported in new Virtex II but.....
From: NO3ackNnak5SPAM@7hotmail.com (-ackNnak-)
Date: Fri, 26 Jan 2001 01:41:46 GMT
Links: << >>  << T >>  << A >>
Check out the TI (formerly Benchmarq) "Gas Gauge" IC's 


On Thu, 25 Jan 2001 20:37:04 -0000, "Simon Bacon"
<simonb@tile.demon.co.cuthis.uk.> wrote:

>Is there an integrated solution which will do the whole
>job - charge the cell/battery, prevent overcharging, regulate
>output?
>
>For extra credit it could flag when the cell/battery is getting
>low and even provide a few bytes of RAM.
>
>
>


Article: 28841
Subject: Re: Advice on FPGA board.
From: pratipm@hotmail.com (Pratip Mukherjee)
Date: Fri, 26 Jan 2001 03:36:38 GMT
Links: << >>  << T >>  << A >>
A near fit would be http://technology.celoxica.com/boards/boards_001.asp

In article <94qcnq$d46$1@nnrp1.deja.com>, jimmy75@my-deja.com wrote:
>
>> None of our boards will fit this particular application.  A board
>> with a PCI bus interace is needed for the high-speed transfers
>> between the FPGA board memory and the PC running the desktop
>> publishing app.  All our boards interface through the
>> parallel port which is too slow for this type of application.
>
>Yep. We need a PCI board for our purpose preferably with a DMA
>controller and a Xilinx Virtex chip(s) and lots of memory. If only we
>could make one on our own!
>I had a look on the web and didn't find all these features altogether
>in one board. We were hoping that somebody out there could help us.
>
>-- Jim
>
>
>Sent via Deja.com
>http://www.deja.com/

Article: 28842
Subject: Re: grey code counters
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Thu, 25 Jan 2001 23:26:50 -0500
Links: << >>  << T >>  << A >>
Nial Stewart wrote:
> 
> Peter Alfke wrote:
> >
> > Theoretically correct,
> > but in reality it depends on the complexity of the Grey-control logic.
> > In the design I am touting, there is actually a binary counter enclosed.
> > Bye-bye power saving.
> >
> > Peter Alfke
> >
> > Theron Hicks wrote:
> >
> > > Also, the switching noise may be substantially less as only one bit is changing
> > > at a time.
> > >
> 
> But it could be a usefule technique if driving the address
> lines of a bank of external parrallel memory devices.
> 
> Nial.

I don't know that the power savings is tremendous. On the average a
binary counter has two bits changing on each clock cycle. The lsb
changes on every cycle, then next bit changes on every other, the next
every fourth,... This series approaches 2 as the number of bits gets
large. The Gray code counter has one bit changing on each clock. So the
difference is a factor of two, useful, but not huge. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com

Article: 28843
Subject: Re: VirtexII and high speed counter
From: Phil Hays <spampostmaster@home.com>
Date: Fri, 26 Jan 2001 06:37:59 GMT
Links: << >>  << T >>  << A >>
Theron Hicks wrote:

> Thus the VirtexII is a very good
> technology.  Is it going to be packaged such that small users (>50
> pieces) can utilize it in the smallest device size?  This means can a
> good solderer hand solder the package.

I'd expect some small boards with VirtexII parts already mounted to be sold by
the usual suspects shortly after they can get the parts.

http://www.optimagic.com/
(then click on "boards")


-- 
Phil Hays

Article: 28844
Subject: Re: how to reduce number of gates in xor reducing in crc computing?
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Fri, 26 Jan 2001 01:41:57 -0500
Links: << >>  << T >>  << A >>
Iman SedehZadeh wrote:
> 
> Does any body know how to reduce number of clbs
> required to implement an XOR reduce tree especially
> for XC4010E?
>  I have written a synthesizable VHDL code for a
> programmable crc engine which accepts generator
> polynomials with degree up to 64 in two separate 16
> bit wide channels which can be added to each other to
> build one 32 bit wide channel. Now I want to implement
> that on a XS40-010 board with a XC4010E fpga on it.
> Leonardo synthesis tool reports clb usage of about
> 700% for that FPGA. I tried direct instantiation of
> xor5 but it didn’t improve the usage.  Also I changed
> xor computations with lookup to a table but didn’t
> have any improvement.
> This is as part of my MS-thesis and I appreciate any
> comments about that.

You may be in trouble depending on what you are trying to do. If your
problem is a matter of reducing the XOR gates by logic minimization, you
may have a real problem. XOR calculations are not gate limited in a LUT
technology. They are IO limited. LUTs can implement any function of N
inputs. So there is no way to reduce a 16 input XOR function using
standard logic minimization techniques. 

However, if you are trying to minimize the logic required for a CRC
calculation, you should find that you can "share" XOR terms between the
different bits. I am not clear with your terms 16 bit wide channel. But
I assume that you are trying to calculate a CRC, 16 bits at a time. In
this case, I expect you will find a lot of commonality in the equations
for the different bits being calculated. This is what I found when I
looked at a 32 bit wide solution. This can cut the amount of logic
required in half. 

But I don't think you are going to find your 7:1 reduction that you
need. I suggest a larger part. 


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com

Article: 28845
Subject: CORDIC ALGORITHM
From: Saqib <saqib_03@hotmail.com>
Date: Fri, 26 Jan 2001 06:45:29 GMT
Links: << >>  << T >>  << A >>
 Hi!
The CORDIC algorithm seems to implement a lot of functions just by
iterative add-shift procedure but at the same time there are some
points that remain unclear...specially in the Linear and Hyperbolic
modes...can anybody help me to get more Theoritical details on these
CORDIC algorithm modes?


Thanx
--
--saqib yaqub--


Sent via Deja.com
http://www.deja.com/

Article: 28846
Subject: Re: Synthesizing Virtex Block Memories with Leonardo v1999.1i = Slooow
From: Phil Hays <spampostmaster@home.com>
Date: Fri, 26 Jan 2001 06:53:04 GMT
Links: << >>  << T >>  << A >>
Newsbrowser wrote:

> Anybody know how to speed things up.

Get a trial licence for Synplify.

www.synplicity.com


-- 
Phil Hays

Article: 28847
Subject: Re: Foundation FPGA Editor hard macros in VHDL
From: mrandelzhofer@my-deja.com
Date: Fri, 26 Jan 2001 07:04:22 GMT
Links: << >>  << T >>  << A >>
this is quite an interesting issue, wonder why nobody else is familiar
with hardmacros.
maybe some simple tasks would become much more easier or faster.

I loved the old xact 6.xx fpga editor, which was originally better than
the neocad editor.
our team has done lots of successful xc3000/xc4003 designs just at the
chip level.
of course this was done mainly because of the lack of fpga resources
and the need for speed.
now xilinx enhanced the fpga editor, and i'd like to experience some
small virtex designs just in the lowest design level. (No doubt, the
high level design strategy is the more efficient way for higher
integrated devices).

here are some of my assumptions on hardmacros:
- I think the xilinx pci cores (and maybe others) uses hard-macros
heavily.
- all the device specific stuff can be used, or used easier as in any
hdl.
- you get the highest speed and area optimization out of the logic
- they are only useful for the fpga family they are designed for, and
only for one special size of fpga
- good for ip-property protection
- only used by the hardliners, a hardmacro can take lots of time and
know how
- its the only way to access the special virtex trdy/irdy logic ?

interesting question is also if there can be prerouted nets. if not, the
usage of rlocs, muxcy's, xorcy's and clbmaps etc. should do the same.
but this isn't supportet by all the vhdl/verilog compilers isn't it ?

Most of my new designs are foundation express vhdl, max clock is about
50MHz in spartan2, and i'm basically not really forced to use
subsubleveldesign.
but e.g.  if you want access to all of the carry outputs of an alu in
vhdl, you can spend hours or days to find a solution. this maybe could
be done simpler at the lowest chip-level (with the xb and yb outputs of
the virtexclb's).

also for testing in the lab, its often helpful to know everything about
the fpga-editor, so you don't need to recompile the design.

an appnote about all these fpga pip, net, block, etc hackings would be
great !


In article <94jqd7$ilp$1@nnrp1.deja.com>,
  sulimma@my-deja.com wrote:
> Does anybody know, where I can find documentation about
> using hard macros created with the FPGA editor of Xilinx
> foundation software
>
> a) In a schematic
> b) In a VHDL design
>
> Thanx,
> 	Kolja
>
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Article: 28848
Subject: looping and ranges
From: Rick Collins <spamgoeshere4@yahoo.com>
Date: Fri, 26 Jan 2001 02:36:24 -0500
Links: << >>  << T >>  << A >>
I was trying to improve the maintainability and readability of a bit of
verilog code and ran into a problem. I am not a "verilog" guy, more of a
VHDL sort. So any help is welcome. 

Here is the code I want to change. 

input[53*8-1:0] bar;

reg[7:0] foo[1:13];

always @(bar)
 begin
  foo[1] <= bar[327:320];
  foo[2] <= bar[335:328];
  ...
  foo[13] <= bar[423:416];
 end

The repetitive statements require a lot of editing when the size of the
array changes. The way that the elements need to match up makes this
worse. So I wanted to change it to a loop, like this. 

integer j;

always @(bar)
  for (j=1; j<14; j=j+1)
    foo[j] <= bar[423-((13-j)*8):423-((13-j)*8)-7];

The ModelSim simulator compiler complains that the range of bar has to
be a constant. A coworker tells me that the real problem is that verilog
won't let you use a loop variable in a range while it will let you use
the loop variable for a single array element. 

So I wanted to try a different approach where I use the loop variable to
assign the bits one at a time, but I could not figure out how to refer
to the individual bits of foo[j]. foo[j][k] did not work. 

Anyone know how to make either of these two solutions work? Or am I
going to have to actually pick up a book and read?


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX
URL http://www.arius.com

Article: 28849
Subject: Re: XC7272 vers XC9272.
From: "RDR" <rdruesne@prosyst.fr>
Date: Fri, 26 Jan 2001 09:56:32 +0100
Links: << >>  << T >>  << A >>
Merci beaucoup,
    My english is also "limited"... ;-)

But .... Thank you .

Can i ? use the old file "jedec" for put in the "new" component ?

A+
RDR


"Andy Peters n o a o [.] e d u>" <"apeters <"@> a écrit dans le message
news: 94q4fh$crh$2@noao.edu...
> RDR wrote:
> >
> > Bonjour,
> >
> >         Y a t il  une demarche particuliere pour porter un design de
xc7272
> > vers xc9272 ?
> >         Y a t il des pin a double utilisation (exple : jtag)?
> >         Y a t il un "convertisseur", une "passerelle" pour convertir les
> > fichiers de l'un vers l'autre?
>
> My French is very limited, but what I think he's saying is: what's
> involved with porting a 7272 design to the 9572?
>
> I keep thinking about porting some 7372 designs to the 9572, and it's
> mostly pin compatible (power-supply pins are in the same place, so are
> global clock pins, etc.) but the JTAG pins must be used for JTAG only,
> so you're hosed if the previous design used the JTAG pins for regular
> I/O.
>
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u
>
> "It is better to be silent and thought a fool,
>  than to send an e-mail to the entire company
>  and remove all doubt."





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