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Take a look at http://www.xess.com/ho04000.html Jorge Neves wrote: > Hi! I have woked with Xilinx XC4010E and wish to get a development kit, > for prototyping, but i dont seem to find one at afair price! If you can > help-me ? thank you! -- ***************************** Anna M. Acevedo Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 879-4780 Email: anna.acevedo@xilinx.com http://www.xilinx.com/programs/univ.htm *****************************Article: 29176
<kolja@prowokulta.org> wrote in message news:95pa52$bv1$1@nnrp1.deja.com... > Yes. You need just one extra LUT. > > -A = (not A)+1 > therefore > > -A-B = (-A) + (-B) = (not A) + (not B) + 2; > > So, you need to handle the first two bits seperately. With three luts > you can determine sum(0), sum(1) and carry(1). Carry(1) is then fed > into a (n-2)-bit adder with inverted inputs. Let's consider the case A=B=0. If n=8, this give us (in binary) 11111111 + 11111111 + 10. The desired answer is 00000000 after dropping the msb carry bit. Processing the first two bits gives: Sum(0) = 0, Carry(0) = 1. Sum(1) = 0, Carry(1) = 2. You need two carry bits. Even if you process additional bits, you still need two carries. Daniel LangArticle: 29177
> L.C. <cupido@mail.ua.pt> a écrit dans le message : > 95t9fs$gnl$1@venus.telepac.pt... > > Hello, > > > > I would like to find information on how to program the 7000's from > > ALTERA (the old non JTAG versions) without having to buy > > an expensive programmer. > > I can apply a little development effort on this but I dont find the > > programming > > info on any of the datasheets. Does anybody > > has info on this ? Or have a programming technique that doesn't require a > > very $$$ programmer ? > > > > I would like to use a box of devices I have... if not... better get new > > JTAG compliant devices rather than buying an expensive programmer. > > > > Please let me know to cupido@mail.ua.pt > > L Cupido. Unfortunately, the older Max 7000 devices require a special programmer and Altera does not give out the programming information for these devices. Unless you have a lot of higher end devices it is probably cheaper to buy the newer devices with the JTAG pins. The 7000S, 7000A, 7000B, and 3000A devices all have the JTAG pins. You may want to consider using the 3000A devices as they are much cheaper. Daniel LangArticle: 29178
Peter Alfke wrote: > serebr@my-deja.com wrote: > > > > And regarding availability: > Please don't give all of Xilinx a black eye for the very special situation with > Spartan-II. We expect that to clear up very soon. Let me tell you, there is no > lack of attention on this case ! > > Peter Alfke Peter, One day, when the wounds have all healed & the guilty parties retired, could you bring yourself to tell us the full Spartan-II saga from the inside ?Article: 29179
"Jan Gray" <jsgray@acm.org> writes: > Request: For those of us with fast net connections, it would be nice if > there were an optional set of "monster PDFs", to download the entire data > sheet, and the entire user's handbook, in one or two files. Agreed, that would be very handy.Article: 29180
Jan Gray wrote: > Request: For those of us with fast net connections, it would be nice if > there were an optional set of "monster PDFs", to download the entire data > sheet, and the entire user's handbook, in one or two files. Yes, please Xilinx, add an optional set of full data sheets. -- Phil HaysArticle: 29181
Peter Alfke <peter.alfke@xilinx.com> writes: > Please don't give all of Xilinx a black eye for the very special > situation with Spartan-II. We expect that to clear up very soon. Let > me tell you, there is no lack of attention on this case ! I will be really impressed if you get them into stock at Digikey. :-)Article: 29182
I'm using the Virtex XCV300. When trying to Implement (running flow engine in the Design Manager), it fails in the last step, Configure. It says Bitgen only supports DRC for the particular device, so what should I do to get it to generate bitfile? Eddy. ================================================ bitgen ds104.ncd -l -w -f bitgen.ut Loading device database for application Bitgen from file "ds104.ncd". "ds104" is an NCD, version 2.27, device xcv300, package bg352, speed -4 Loading device for application Bitgen from file 'v300.nph' in environment d:/xilinx. Opened constraints file bigand.pcf. BITGEN: Xilinx Bitstream Generator M1.5.19 Copyright (c) 1995-1998 Xilinx, Inc. All rights reserved. Thu Feb 08 18:46:36 2001 Running DRC. DRC detected 0 errors and 0 warnings. WARNING:basbs:134 - bitgen only supports DRC on this device.Article: 29183
Rick Filipkiewicz wrote: > Peter Alfke wrote: > > > serebr@my-deja.com wrote: > > > > > > > And regarding availability: > > Please don't give all of Xilinx a black eye for the very special situation with > > Spartan-II. We expect that to clear up very soon. Let me tell you, there is no > > lack of attention on this case ! > > > > Peter Alfke > > Peter, > > One day, when the wounds have all healed & the guilty parties retired, could you > bring yourself to tell us the full Spartan-II saga from the inside ? --------- You might have to wait quite a while before getting an answer from the source ... In the meantime, from a small volume user point of view, it looks like the specs gap between Virtex and Spartan II was so small that xilinx marketing was afraid many Virtex customers would retarget for the much cheaper spartan II, hurting Xilinx's bottom line badly. Now that Virtex II is out, there is a sizeable gap between the "high end" and the "low cost" again, and Spartan II actual chips can be expected anytime soon. OTOH, it's availiable for high volume applications where it's competing against ASIC, not Virtex ... Any other reasons ? Eric.Article: 29184
Rick Filipkiewicz wrote: > Peter Alfke wrote: > > > serebr@my-deja.com wrote: > > > > > > > And regarding availability: > > Please don't give all of Xilinx a black eye for the very special situation with > > Spartan-II. We expect that to clear up very soon. Let me tell you, there is no > > lack of attention on this case ! > > > > Peter Alfke > > Peter, > > One day, when the wounds have all healed & the guilty parties retired, could you > bring yourself to tell us the full Spartan-II saga from the inside ? ----------- You might have to wait quite a while before getting an answer from the source ... In the meantime, from a small volume user point of view, it looks like the specs gap between Virtex and Spartan II was so small that xilinx marketing was afraid many Virtex customers would retarget for the much cheaper spartan II, hurting Xilinx's bottom line badly. Now that Virtex II is out, there is a sizable gap between the "high end" and the "low cost" again, and Spartan II actual chips can be expected anytime soon. OTOH, it's available for high volume applications where it's competing against ASIC, not Virtex ... Any other reasons ? Eric.Article: 29185
Hi? I am newbie. How can I make control signal for ADS7843. I should use XCS20VQ100(XILINX). Is there any example? Please help me. Thanks in advance.Article: 29186
Record 4296 in the Answer Database states that newer devices after the 4000 series are not able to control their own reconfiguration due to other requirements on the PROGRAM pin. However, the Virtex series conforms to the 300 ns requirement on the PROGRAM pin, so does anyone know if it is possible to safely initiate a reconfiguration by pulling the PROGRAM pin low with its own logic? Best Regards, /Henrik BohreArticle: 29187
Does anybody have this symbol for Orcad capture? Thanks very much in advance. Gil GolovArticle: 29188
Please check at the Exemplar web-site where you'll find a Appnote describing exactly how to do it. www.exemplar.com -> support -> app notes Best Regards Håkan "Harjo Otten" <h.otten@rohill.geen.spam.nl> wrote in message news:rsau59.4el.ln@svr004.rohill.nl... > Hello, > > In a few weeks we will be starting our first PCI project, and we are going > to use a Xilinx PCI core. We bought ourselfs an Insight evaluation board to > get to know the PCI core, and do some testing. Since we've never done > anything with the PCI bus and we don't have that much experience with FPGA > desing, I'm asking for some starter-tips. > We're using Ease/Eale, Leonardo Spectrum and Modelsim. Are there some "dos" > and "don'ts", tips, guides... anything is welcome. > > Regards, > > H. Otten. > >Article: 29189
I am interested in learning the Verilog language. Could someone advise me a good book on Verilog like the one of Ashenden on VHDL? Thank you. -- Arthur Aghababyan DESY, MVP Notkestrasse 85 22607 Hamburg Germany e-mail: arthura@sun52a.desy.de tel: +49 40 8998 4554 fax: +49 40 8998 4448Article: 29190
Does anyone know if Synplify runs on Windows 2000? Cheers, RichArticle: 29191
I am looking to get started with designing my own pseudo ic using fpga or cpld or pld or gal or...? maybe even some fift thing. The trouble is that i have a little problems seeing the exactl difrence between theese. At first i thought it was created in the order gal, pld, clpd and finally fpga, now i am not so sure. Seems like fpga reads its "code" from a serial eeprom whereas a cpld does from internal eeprom. This in my eyes make the cpld a bit smarter since it can function as an alone component, but is this the whole difrence and if so then why use fpga at all? And what is it with pld and gal? What exactly are those? Still components programmable by vhdl syntesis or..? My primary goal with using gate arrays is to make small and fast custom ic for addon units i am building for my current embeded digital elctronics. At first it will be nice to be able to reprogram the gate array any number of times till the design is done, and then it would be nice with a selccontained unit which is cheap but doesnt HAVE to be reprogrammable.. just to stuff the finished design on. What would be best suited for me there? If we look aside the difrent number of gates on the devices, can any vhdl design for any one of them run as well (though maybe slower) on the other devices? provided i have the correct synthesis tool ofcourse. I know theese are pretty basic questions, but i havent really seen any info on all of theese in comparison..Article: 29192
Hi Brian Thanks for this useful tip! I think this might the soulution to my problem. >Most likely, you will have to hand create this structure as I am not sure >if any synthesis tools currently infer this structure. Maybe in the near >future though... So how do think such a design could be implemented, if the design tools cannot infere it? Im using Xilinx Foundation 3.1i, the design is coded in VHDL. Somehow I would need complete acces to the FPGA elements, such as LUTs and carry chains. Is there a way to acces these directly? From the Xilinx Library Guide I've seen, that components ADD16 and OR16 work exactly like this, but since these are marcos I cannot extend them to my needs. ChrisArticle: 29193
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I really dont't want to get into this again, but just for arguments sake;-
If you are so sure that the software implements that
stinking attribute then why is it that the timing analyser
shows me a setup time of 9ns and why did you say
in one of your replays that , and I quote:
"I have discovered that the timing report will not give a very clear picture
as to whether the NODELAY attribute took effect.".............. How can that
be????. The timing analyser is not working or the attribute did not take
effect???Which one is it?
Best regards,
jakab
Kamal Patel wrote:
> Since I was the engineer working on this case I would like to
> clear things up. I apologize, Jakab, for not being able to find
> out what the issue with your software was, but after verifying
> that the constraint was accepted in your design on my machine,
> I can state for sure that the Alliance tool does not refuse to
> implement this attribute. You will see the NODELAY attribute
> for the register in your MAP report as you say you did. To verify
> it was indeed implemented, you can look into the IOB in FPGA
> Editor to see if the signal is routed through a delay element or not.
>
> I offered you the opportunity for me to guide you through the steps,
> and only closed the case upon your request. I can re-open it for
> you at any time if you are not satisfied with my service. Please
> do not let our miscommunication reflect on all of Xilinx Support.
>
> Thank you for your time.
>
> Jakab Tanko wrote:
>
>> Just a note on Xilinx support;- I had a problem recently with
>> an 4000xla type device NODELAY attribute for some critical
>> inputs on my design. The problem was (and still is) that the Alliance
>> tool refuses to implement this attribute; it is all good up to the
>> mapper
>> but on the next step which is the PAR, the attribute is not there
>> anymore.
>> Now, you would think that this is a pretty-strait-forward, specific
>> problem
>> that should be a no-brainer for a Xilinx application engineer..
>> but not so fast;- after 4 days of trying to get the Xilinx support to
>> give me
>> an answer I simply gave up...It seems to me that they have a two-tier
>> system
>> where you get the top-notch support if you pay for it, but if you
>> just "another
>> customer" then you get the co-op student to solve your problems and
>> you might as well
>> try to solve them yourself,
>> But again this is just my oppinion and I could be wrong,
>> jakab
>>
>> Peter Alfke wrote:
>>
>>> serebr@my-deja.com <mailto:serebr@my-deja.com> wrote:
>>>
>>>> It's permanent trade-off: Xilinx provides instant and very high quality
>>>> support but Altera's devices are mostly available in stock
>>>> (I mean in comparison with the Spartan-II availability).
>>>>
>>>
>>> Thanks for the friendly words about Xilinx support.
>>> And regarding availability:
>>> Please don't give all of Xilinx a black eye for the very special situation with
>>> Spartan-II. We expect that to clear up very soon. Let me tell you, there is no
>>> lack of attention on this case !
>>>
>>> Peter Alfke
>>>
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<html><head></head><body>I really dont't want to get into this again, but just for arguments sake;-<br>
If you are so sure that the software implements that<br>
stinking attribute then why is it that the timing analyser<br>
shows me a setup time of 9ns and why did you say<br>
in one of your replays that , and I quote:<br>
"I have discovered that the timing report will not give a very clear picture<br>
as to whether the NODELAY attribute took effect.".............. How can that<br>
be????. The timing analyser is not working or the attribute did not take <br>
effect???Which one is it?<br>
Best regards,<br>
jakab<br>
<br>
Kamal Patel wrote:<br>
<blockquote type="cite" cite="mid:3A82FC4D.8AF4B1D6@xilinx.com">
Since I was the engineer working on this case I would like to
<br>
clear things up. I apologize, Jakab, for not being able to find
<br>
out what the issue with your software was, but after verifying
<br>
that the constraint was accepted in your design on my machine,
<br>
I can state for sure that the Alliance tool does not refuse to
<br>
implement this attribute. You will see the NODELAY attribute
<br>
for the register in your MAP report as you say you did. To verify
<br>
it was indeed implemented, you can look into the IOB in FPGA
<br>
Editor to see if the signal is routed through a delay element or not.
<p>I offered you the opportunity for me to guide you through the steps,
<br>and only closed the case upon your request. I can re-open
it for
<br>you at any time if you are not satisfied with my service. Please
<br>do not let our miscommunication reflect on all of Xilinx Support.
</p>
<p>Thank you for your time.
</p>
<p>Jakab Tanko wrote:
</p>
<blockquote type="CITE">Just a note on Xilinx support;- I had a problem recently
with
<br>an 4000xla type device NODELAY attribute for some critical
<br>inputs on my design. The problem was (and still is) that the Alliance
<br>tool refuses to implement this attribute; it is all good up to the
mapper
<br>but on the next step which is the PAR, the attribute is not there anymore.
<br>Now, you would think that this is a pretty-strait-forward, specific
problem
<br>that should be a no-brainer for a Xilinx application engineer..
<br>but not so fast;- after 4 days of trying to get the Xilinx support
to give me
<br>an answer I simply gave up...It seems to me that they have a two-tier
system
<br>where you get the top-notch support if you pay for it, but if you just
"another
<br>customer" then you get the co-op student to solve your problems
and you might as well
<br>try to solve them yourself,
<br>But again this is just my oppinion and I could be wrong,
<br>jakab
<p>Peter Alfke wrote:
</p><blockquote type="cite" cite="mid:3A82CB21.6808D98A@xilinx.com"><pre wrap=""><a href="mailto:serebr@my-deja.com" class="moz-txt-link-abbreviated">serebr@my-deja.com</a> wrote:<br><br></pre><blockquote type="cite"><pre wrap="">It's permanent trade-off: Xilinx provides instant and very high quality<br>support but Altera's devices are mostly available in stock<br>(I mean in comparison with the Spartan-II availability).<br><br></pre></blockquote><pre wrap=""><!----><br>Thanks for the friendly words about Xilinx support.<br>And regarding availability:<br>Please don't give all of Xilinx a black eye for the very special situation with<br>Spartan-II. We expect that to clear up very soon. Let me tell you, there is no<br>lack of attention on this case !<br><br>Peter Alfke<br><br></pre></blockquote></blockquote>
</blockquote>
<br>
</body></html>
--------------090000030308000608080601--
Article: 29194Yes. I ran it on a PIII-800 w/Win2k with no problems, and it was about 1% faster than on a Sun Ultra-80 (UltraSparcII-450). (Though it's running under MainWin on Solaris.) -cb -- Chris Briggs Nauticus Networks cbriggs@nauticusnet.com Richard Wilkinson wrote: > Does anyone know if Synplify runs on Windows 2000? > > Cheers, > > RichArticle: 29195
Hello, Say we want to implement a binary counter but with offset i mean a counter from (offset+0)------->(2^N+Offset) the obvious solution is a simple ordinary binary counter (0-->2^N)+ an adder with "offset" as operand value, but is it really the optimal way ? --Regards Sent via Deja.com http://www.deja.com/Article: 29196
Hi, I'm currently working on a design that has 5 clock domains (33, 66, 104, 110 and 133) but unfortunately, only 4 global clock routing resources are available. I thought about moving the 33 MHz clock to the low skew lines using the "USELOWSKEWLINES" in the UCF file but it does not seem to work because the mapper still report that 5 out of 4 global clock routing resources are used. This 33MHz clock is used only in the PCI clock (32 bits, 33MHz). I know that it's not recommended to do this but I've got nothing to loose to try it... Anyone knows how to do this or has tried it? (the PCI_CLK input is on a GLCKIOB. Could it be why it can not be routed on the local low skew lines? Thanks! MartinArticle: 29197
On Fri, 09 Feb 2001 10:39:14 +0000, Richard Wilkinson <richard.wilkinson@csr.com> wrote: >Does anyone know if Synplify runs on Windows 2000? I'm running SynplifyPro on a ThinkPad A21p with Win2000. It's working fine except for an intermittent license problem. Every once in a while it loses its license and dies a horrible death (lost file changes - need to reboot to get SynplifyPro back). I have a ticket open with Synplicity to resolve this, but it's slow going because it is so intermittent. I'm beginning to think it's a ThinkPad power management issue, but haven't tracked it down. I wish Synplify's license management were as unobtrusive as ModelSim's. ---- KeithArticle: 29198
Sorry if this comes out completely wrong - but I am also a newbie to this. If the offset is given at count start-time and never changed, couldn't you then make a presetable counter, something like this: count(count'range) <= offset; ..... count := count + 1; .... / Daniel NilssonArticle: 29199
Hi Philip The difference is in the internal architecture. CPLD has the more basic structure, it is build from two main matrixes, the first is a NAND matrix that gives you products y1=not (A*B2*d3) y2=not(B3*C1.....) The second matrix gives you the sum of the products resualt1=y1+y2+y5 and so on. It is possible to feed back the result to the NAND matrix and so you can create any logical combination. FPGA is build from small units that each of them can perform a function and every basic block is connected to a neighbor one so it gives a huge flexibility in implementation of logical functions. CPLD have some clock skews advantages but FPGA in normally in much larger device. For your purpose: if your design is small, lets say only a few hundreds of gates/ff, maybe you should go for a CPLD which can be cheaper than a FPGA. If you are thinking on a large or you intend to to expend your design to a large one in the future you should go for a FPGA. Serial eprom: depends on the vendor and the type, you can see FPGAs with an internal EPROM or based on anti fuse technology. Basically if the device is large and fast enough, a proper synthesis tool can take your VHDL code and implement is on a CPLD or a FPGA. Good lock Gil. PhilipKD wrote: > I am looking to get started with designing my own pseudo ic using fpga or > cpld or pld or gal or...? maybe even some fift thing. > The trouble is that i have a little problems seeing the exactl difrence > between theese. > At first i thought it was created in the order gal, pld, clpd and finally > fpga, now i am not so sure. > > Seems like fpga reads its "code" from a serial eeprom whereas a cpld does > from internal eeprom. This in my eyes make the cpld a bit smarter since it > can function as an alone component, but is this the whole difrence and if so > then why use fpga at all? > And what is it with pld and gal? What exactly are those? Still components > programmable by vhdl syntesis or..? > > My primary goal with using gate arrays is to make small and fast custom ic > for addon units i am building for my current embeded digital elctronics. At > first it will be nice to be able to reprogram the gate array any number of > times till the design is done, and then it would be nice with a > selccontained unit which is cheap but doesnt HAVE to be reprogrammable.. > just to stuff the finished design on. > > What would be best suited for me there? > > If we look aside the difrent number of gates on the devices, can any vhdl > design for any one of them run as well (though maybe slower) on the other > devices? provided i have the correct synthesis tool ofcourse. > > I know theese are pretty basic questions, but i havent really seen any info > on all of theese in comparison..
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Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z