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There are several schematic entry systems that can write VHDL or Verilog netlists. Just include that generated HDL with the HDL for the subblocks and I think you have what you asked for. Look at Aldec for an example. In Europe, there is a tool called EASE from Translogic that generates VHDL. I think these tools also have state machine tools as well. "Keith R. Williams" wrote: > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > Noddy wrote: > > > > > > This brings me to my question? Should I rather be > > > attempting to implement my designs in VHDL instead? > > > > Mix it ! > > A top level schematic, the units below in VHDL, Verilog, etc.. > > It's amazing, already magic how easy it is to explain what you're doing > > to somebody else, when you can see all functional units, data flow on > > one sheet. > > And, sometimes you see your own design more clearly ;-) > > That certainly would be an advantage. However, I understand that > synthesis in a mixed environment doesn't work well. The redundancy > isn't squished out beyond the black boxes. > > > when you like to go to HDL only, just replace one sheet to a text page. > > If I could do both schematics and (V)HDL with the same toolset with the > flattening occurring before the "real" synthesis this would be nice. > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > wile remaining productive. Listening Synplicity? ;-) > > ---- > Keith -- Ken McElvain, CTO Synplicity Inc. (408)215-6060Article: 33051
In article <3B53305B.68C195A5@synplicity.com>, ken@synplicity.com says... > There are several schematic entry systems that can write VHDL or > Verilog netlists. Just include that generated HDL with the > HDL for the subblocks and I think you have what you asked for. > > Look at Aldec for an example. In Europe, there is a tool called > EASE from Translogic that generates VHDL. I think these tools > also have state machine tools as well. I don't know if this is the same thing. Synplicity, for instance, does a lot of work optimizing the logic for the target architecture. It obviously can't see what it didn't generate so there may not be any optimizations across black boxes (even if two block boxes are adjacent in real life). In fact I don't think there are any optimizations attempted across black boxes. Anyway, I'm nervous adding more tools to the chain. If the tools did schematic in the hierarchy, fine. I agree that schematic is more "natural" for the high-level design and documentation. ---- Keith > "Keith R. Williams" wrote: > > > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > > Noddy wrote: > > > > > > > > This brings me to my question? Should I rather be > > > > attempting to implement my designs in VHDL instead? > > > > > > Mix it ! > > > A top level schematic, the units below in VHDL, Verilog, etc.. > > > It's amazing, already magic how easy it is to explain what you're doing > > > to somebody else, when you can see all functional units, data flow on > > > one sheet. > > > And, sometimes you see your own design more clearly ;-) > > > > That certainly would be an advantage. However, I understand that > > synthesis in a mixed environment doesn't work well. The redundancy > > isn't squished out beyond the black boxes. > > > > > when you like to go to HDL only, just replace one sheet to a text page. > > > > If I could do both schematics and (V)HDL with the same toolset with the > > flattening occurring before the "real" synthesis this would be nice. > > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > > wile remaining productive. Listening Synplicity? ;-) > > > > ---- > > Keith > >Article: 33052
"Rotem Gazit" <rotemg@mysticom.com> wrote in message news:86b060d0.0107160944.73e343@posting.google.com... > Hi, > Is there a simple way to fix manual or automatic routing so that on > the next PR cycle it would not change ? > The only way I know to do this is by instantiating predefined macro > and I am looking for an easier way. > Thanks, > > Rotem. > > Rotem Gazit > MystiCom LTD > mailto:rotemg@mysticom.com > http://www.mysticom.com/ > If you are done with your code and only playing with P&R, you can freeze the design with the floorplanner and have the tools use that placement for subsequent P&R iterations. there's various options dialog boxes, depending on which flavour of tools you are using. If you are have not finalized your HDL and need to resynthesize, you're in trouble. As a FAE explained to me (and correct me if I'm wrong) the P&R tools use a random seed to start mapping the design into the chip following translation. even if you did freeze the P&R w/floorplanner, resynthesis renames nets and there's the source of the problem with that approach. If your HDL is solid, some judicious use of constraints in the UCF can be very helpful. regards, jeff *********************************************** Jeffrey Vallier Sr. FW Engineer Gibson Guitar Corp. GMICS Division 1283 F Old Mtn View/Alviso Rd. Sunnyvale, CA 94089 408 734 4394 ***********************************************Article: 33053
You can freeze placement, but not routing. To specify routing, you are unfortunately stuck with either using hrad (fpga editor) macros or using Jbits. Sorry, no easy solutions here. Rotem Gazit wrote: > Hi, > Is there a simple way to fix manual or automatic routing so that on > the next PR cycle it would not change ? > The only way I know to do this is by instantiating predefined macro > and I am looking for an easier way. > Thanks, > > Rotem. > > Rotem Gazit > MystiCom LTD > mailto:rotemg@mysticom.com > http://www.mysticom.com/ -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33054
Hi, There is a way to do what you want, but it will require some time investment (perhaps more than is warranted by your design). So it does not qualify as "easier". We use this technique to lock routes in the Xilinx PCI products to guarantee performance. If you are using an HDL synthesis tool, forget it... If you are looking to simply preserve as much of the placement and routing between design iterations, I suggest you try using guide mode in PAR. par -gm exact -gf previously_routed_design.ncd or par -gm leverage -gf previously_routed_design.ncd You can read the Xilinx software manuals online to understand the difference between exact and leverage modes. Long Live Viewdraw, Eric Rotem Gazit wrote: > Hi, > Is there a simple way to fix manual or automatic routing > so that on the next PR cycle it would not change? The only > way I know to do this is by instantiating predefined macro > and I am looking for an easier way. > Thanks, > RotemArticle: 33055
Falk Brunner wrote: > Ray Andraka schrieb: > > > > but including Spartan II doesn't make sense. For new designs, if you are > > I think it makes sense, since the Spartan-II devices are cheaper. My point is that for designs that fit the XC2S, virtex and XC2S are interchangeable (same bitstream), so you have a low cost target for the virtex architecture (the virtex E architecture is essentially the same with a few enhancements). You are correct, I would not recommend Virtex for a new design unless it was a QPRO application. In any event it is a nitpick. > > > > not in the Spartan II, I would go with the Virtex E right now. The Virtex > > As I said. > > > design into space, you're stuck with Virtex. Personally, I'd forgo the > > 4K/Spartan (original) architecture for new designs, as the cost per gate and > > speeds are better for the later families, and the later families have a > > Yes, but there are lots of applications that dont need the Multi-million > gate FPGAs. If you have some small on-on boards which needs just some > glue logic, small fifos, some uC registers etc., Spartan(XL) is just > fine and cheap. Not everyone is working everyday on cutting edge, > breakthrough designs. ;-) > Price and capability makes SpartanII much more attractive than Spartan. I would not recommend the original spartan for a new design in most cases. The exception would be when you already have a substantial part of the design that is tailored or targeted to a 4K architecture. single unit pricing From www.avnetmarshall.com/dynamic/search: XC2S15-5VQ100 $8.96 XCS10XL-4VQ100 $12.76 These are the cheapest I saw for each part. The XC2S15 gives you 384 LUTs plus 4 block RAMs at 3/4 the price of the XCS10, which has 392 LUTs. You give up all of 8 LUTs, but gain 4 block RAMs, SRL16 capability (which is big in my book), faster clocks, later technology and a longer time horizon. I'll give up the 8 LUTs for all that, especially considering the price difference. Besides, I can use the 4 dual port block rams as 8 big LUTs if I wanted to. -- -Ray Andraka, P.E. President, the Andraka Consulting Group, Inc. 401/884-7930 Fax 401/884-7950 email ray@andraka.com http://www.andraka.comArticle: 33056
Morgan Kaufmann Publishers - New Title Announcement Readings in Hardware/Software Co-design by Giovanni De Micheli, Rolf Ernst, Wayne Wolf http://www.mkp.com/books_catalog/catalog.asp?ISBN=1-55860-702-1 Part of the Morgan Kaufmann Series in Systems on Silicon http://www.mkp.com/sos/ Embedded system designers are constantly looking for new tools and techniques to help satisfy the exploding demand for consumer information appliances and specialized industrial products. One critical barrier to the timely release of embedded system products is integrating the design of the hardware and software systems. Hardware/software co-design is a set of methodologies and techniques specifically created to support the concurrent design of both systems, effectively reducing multiple iterations and major redesigns. In addition to its critical role in the development of embedded systems, many experts believe that co-design will be a key design methodology for Systems-on-a-Chip. Readings in Hardware/Software Co-Design presents the papers that have shaped the hardware/software co-design field since its inception in the early 90s. Field experts -- Giovanni De Micheli, Rolf Ernst, and Wayne Wolf -- introduce sections of the book, and provide context for the paper that follow. This collection provides professionals, researchers and graduate students with a single reference source for this critical aspect of computing design. _______________________________________________________________ Morgan Kaufmann Publishers San Francisco, California http://www.mkp.com orders@mkp.comArticle: 33059
I actually had good success a while back with nets defined in my guide file for a Spartan-II design (Virtex architecture). I got rid of the nets I didn't care about with the FPGA editor and manually routed the net I wanted. The results were pretty consistent for this critical net. Newer service packs have eliminated the need for this particular net's hand routing, producing better results all around. The only big troubles I could see is if the synthesis tool used renames elements in the guide file. This is the biggest problem in getting a "minimum change" design. If all I want is to add two test points I end up with 20% of my edif elements renamed. I hate it when that happens! - John Ray Andraka wrote: > You can freeze placement, but not routing. To specify routing, you are > unfortunately stuck with either using hrad (fpga editor) macros or using > Jbits. Sorry, no easy solutions here. > > Rotem Gazit wrote: > > > Hi, > > Is there a simple way to fix manual or automatic routing so that on > > the next PR cycle it would not change ? > > The only way I know to do this is by instantiating predefined macro > > and I am looking for an easier way. > > Thanks, > > > > Rotem. > > > > Rotem Gazit > > MystiCom LTD > > mailto:rotemg@mysticom.com > > http://www.mysticom.com/ > > -- > -Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.comArticle: 33060
John_H <johnhandwork@mail.com> > HDL, not schematics, yes! yes! > Verilog and VHDL are both appropriate to the task. > It's a little like the age old question (probably still valid in > your corner of this world: "Coke or Pepsi?" At the risk of starting a long religious debate, my experience has been that VHDL is better suited for high speed FPGA design. To push an FPGA to the edge, you pretty much need attributes to control mapping and placement, and Verilog doesn't (yet) have a standard way to implement attributes. Also, VHDL's "generate" construct is almost necessary for attaching attributes when using wide busses. I'm not a big fan of VHDL either. I keep hoping that some day someone will invent a *good* HDL.Article: 33061
OK, After spending 3 hours in the biggest bookshops in town (the world-famous Foyles, Waterstones and some new joint), I managed to find the following two titles, which I bought: Yalamanchili, Sudhakar (2001) "Introductory VHDL: From Simulation to Synthesis" includes Xilinx Student Edition 2.1i - Only £25! (about $37) It seems a pretty good book too. Zwolinski, Mark (1997) "Digital System Design with VHDL" - £30 (about $45) Good because it stradles the digital systems and VHDL borders, explaining both. I was surprised how little there was available. There were quite a few research-oriented Titles by Kluwer Press, but with prices like £90 (about $135), and being quite old, forget it. The Yalamanchili book popped out of nowhere in a smaller bookshop with only one shelf on electronics. While the 7 or 8 shelves at Foyles were full of stuff on CMOS, Digital IC design and lots of old titles. Anyway, I'll let you all know how I get on with these titles. I'll have a look at the Xilinx stuff too. Thanks all.Article: 33062
Hello: I'm a student from Chile starting an FPGA project. I need to get the Xilinx Foundation Pro and I cant effort it(it is very expensive). If somebody can tell me where i can get that software or a similar, please write me. Sincerily Yoram Rovner yoram@puc.cl Santiago de ChileArticle: 33064
Hi, SAF wrote: > > OK, > > After spending 3 hours in the biggest bookshops in town (the > world-famous Foyles, Waterstones and some new joint), I managed to > find the following two titles, which I bought: > > Yalamanchili, Sudhakar (2001) "Introductory VHDL: From Simulation to > Synthesis" includes Xilinx Student Edition 2.1i - Only £25! (about > $37) It seems a pretty good book too. Is it this one (ISBN: 0130809829)? http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0130809829/contents/ref=pm_dp_ln_b_2/104-5678861-7531964 > > Zwolinski, Mark (1997) "Digital System Design with VHDL" - £30 (about > $45) Good because it stradles the digital systems and VHDL borders, > explaining both. Is it this book (ISBN: 0201360632)? http://www.amazon.com/exec/obidos/tg/stores/detail/-/books/0201360632/contents/ref=pm_dp_ln_b_2/104-5678861-7531964 > You got them really cheap! Good for you!Article: 33065
I tried out a simple counter design and it programmed and worked ok. Only general IO pins had active signals from the dsp upon them. Martin Schoeberl wrote: > > Sould be no problem if the dsp has no problems with tri state pins. > But how are the config pins driven on the board original? > You could get a contention with the byte blaster. > > Martin > -- > Whant to see the evolution of a Java processor? > > http://www.jopdesign.com > > "Russell Shaw" <rjshaw@iprimus.com.au> schrieb im Newsbeitrag > news:3B4D8E87.31046A07@iprimus.com.au... > > Hi all, > > > > I've got a dsp driving an altera ep1k30, and was wondering if its > > ok to reprogram that chip even tho the dsp is still driving it. > > I've got a byteblaster connected to it. I read somewhere that > > all(?) the pins go to tri-state when programming (passive serial). > >Article: 33066
"Keith R. Williams" wrote: > > In article <3B53305B.68C195A5@synplicity.com>, ken@synplicity.com > says... > > There are several schematic entry systems that can write VHDL or > > Verilog netlists. Just include that generated HDL with the > > HDL for the subblocks and I think you have what you asked for. > > > > Look at Aldec for an example. In Europe, there is a tool called > > EASE from Translogic that generates VHDL. I think these tools > > also have state machine tools as well. > > I don't know if this is the same thing. Synplicity, for instance, does > a lot of work optimizing the logic for the target architecture. It > obviously can't see what it didn't generate so there may not be any > optimizations across black boxes (even if two block boxes are adjacent > in real life). In fact I don't think there are any optimizations > attempted across black boxes. > > Anyway, I'm nervous adding more tools to the chain. If the tools did > schematic in the hierarchy, fine. I agree that schematic is more > "natural" for the high-level design and documentation. Synplify would see the generated(from the schematic) top level VHDL/verilog because you would include it in the Synplify project. The lower level VHDL/Verilog files would then be optimized together. You don't need to make the submodules black boxes. > > ---- > Keith > > > "Keith R. Williams" wrote: > > > > > > In article <3B5053B0.8E3FF4D2@ecubics.com>, emu@ecubics.com says... > > > > Noddy wrote: > > > > > > > > > > This brings me to my question? Should I rather be > > > > > attempting to implement my designs in VHDL instead? > > > > > > > > Mix it ! > > > > A top level schematic, the units below in VHDL, Verilog, etc.. > > > > It's amazing, already magic how easy it is to explain what you're doing > > > > to somebody else, when you can see all functional units, data flow on > > > > one sheet. > > > > And, sometimes you see your own design more clearly ;-) > > > > > > That certainly would be an advantage. However, I understand that > > > synthesis in a mixed environment doesn't work well. The redundancy > > > isn't squished out beyond the black boxes. > > > > > > > when you like to go to HDL only, just replace one sheet to a text page. > > > > > > If I could do both schematics and (V)HDL with the same toolset with the > > > flattening occurring before the "real" synthesis this would be nice. > > > This soul also allow us old fuddy-duddy schematic wonks pick up on HDLs > > > wile remaining productive. Listening Synplicity? ;-) > > > > > > ---- > > > Keith > > > >Article: 33067
yoram@puc.cl (Yoram Rovner) writes: > I'm a student from Chile starting an FPGA project. I need to get the > Xilinx Foundation Pro and I cant effort it(it is very expensive). If > somebody can tell me where i can get that software or a similar, Can you get your University to buy it? Perhaps Xilinx has special deals for educational institutions. I'm not sure about "Foundation Pro", but if you think you need such a thing presumably you've already determined that you can't get by with WebPack ISE (free download from www.xilinx.com) or the student edition of Foundation (inexpensive, can be purchased in bookstores including amazon.com). I'm somewhat surprised because WebPack ISE can handle fairly large designs (up to XC2S200, XCV300E, and XC2V250), but if your design really won't fit into one of those, and you can't partition it for multiple designs, you're probably out of luck. Maybe if you told us more about your project we could offer more advice? Best regards, EricArticle: 33068
Alex, You are right on the 2.1i, it might has problem as you said! Just a reference, the 3.3i works fine what you try to do "BUS". However, to workaround it (2.1i), you could try the Foundation logiBLOX/Macro program, it might works? The difference is that the compiler might not run DRC in the FPGA primitive converting process (EDIF writer). For example, try to open BUFT in symbol-editor, you might see I/O's types are funny like I=in ,T=input and O=output. The O=output type is wrong, it should be 3 state or tristate type. This is explained where the problem comes from, of course, SW wouldn't be happy in compilation when must we tie all outputs together in BUS circuitry , which is supposed to be 3 state, it is failed DRC! BUGGY!!! To answer about Other tool solution is that you can use the EDIF/XNF (primitive) files from Orcad/viewlogic schematic (if you own one). Hope this helps, HongArticle: 33070
Hi, I have a problem. I want to work Xilinx Foundation under Windows 2000, but program lmutil.exe return bad hostid. I have license on my net card but lmutil return no correct net card number. I worked under WinNT and everything was OK. What can I do to run Xilinx Foundation? TomArticle: 33071
Hello: This is my first time posting to this newsgroup. If this is not an appropriate post, my apologies. Anyway, here goes: Does anyone know of a public domain Extended Utopia core? There, I did it. Thanks! Craig A.Article: 33072
Brian Philofsky wrote: > > John, > > If you are planning to target a Xilinx FPGA, there is a list of > free and pay-for uP cores on the Xilinx website in the Processor > Central sections: And here is a core for Altera FPGA's. Still untested but gives idea of the size of FPGA's needed for small cpu designs. "Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk Now with schematics. Ben.Article: 33074
Hi all, I am just starting with FPGAs am very puzzled by behivour of my
development board. I am using ATSK40 with Atmel's AT4K chip on it.
The board has several buttons, manual clock and a 32khz clock input.
My test design is a series of flip-flops which form a counter. When I hook
up the clock input of the counter to the buttons (which are not debounced)
I get expected behaviour - counter is incremented by 1 when the button is
pressed. (though I am wondering how come this is happening as buttons are
not debounced..) However when I hook up to clock io pad I get random values.
I have a suspicion that using clock pad somehow changes the circuit (maybe
flip flops get their clock inputs reassigned ?), but I dont' know where in
options to change that (Figaro), nor how to see what gets assigned to clock
inputs.
thanks
Vladimir Dergachev
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