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Messages from 33100

Article: 33100
Subject: regarding the constraints while writing VHDL code
From: sandeep_shastri@yahoo.com (sandeep)
Date: 17 Jul 2001 11:45:05 -0700
Links: << >>  << T >>  << A >>
Hello everybody, 
              Myself is Sandeep,and is a Post Graduate student and
doing dissertation in JPEG baseline image compression using VLSI.
I have written a code for 2-D DCT using VHDL and simulated it, but hte
problem is that it is not fitting in any of the CPLD or FPGA. I have
used Xilinx 2.1 tool.Is there any solution to this problem?????????/
My doubt is that while writing the code is it necessary to take in to
consideration the internal architecture of the FPGA or CPLD??? If yes
then in which manner???????/


Thanking you in anticipation


Yours 
sandeep

Article: 33101
Subject: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
From: Tom Dillon <tdillon@dilloneng.com>
Date: Tue, 17 Jul 2001 19:15:38 GMT
Links: << >>  << T >>  << A >>
Does Linux offer better performance than Win2000 for large designs?



>>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<

On 7/17/2001, 10:10:08 AM, Paul Graham <grahamp@ee.byu.edu> wrote regard=
ing=20
Using the Xilinx Alliance 3.1i/3.3i Tools under Linux:


> I have created a Web page describing how to use the Xilinx Alliance
> 3.1i/3.3i tools under Linux using Wine.  The URL is:

> http://splish.ee.byu.edu/tutorials/linux-alliance/linux-alliance.html=


> This publicly available Web page describes the complete installation
> process as well as how to set up users' environments to run the tools.=

> I also have included sections on how to run the Xilinx tools under
> Wine and some of the caveats and work-arounds I have encountered.

> The great news is that the Xilinx Alliance tools install nicely under=

> Wine now as do the Service Packs and Device Updates, so creating and
> maintaining the installations has become much easier.

> If you encounter any problems with my instructions, let me know.  I
> have tried to be as complete as possible and have tested the
> instructions fairly well, but there is always room for improvement.

> Enjoy,

> Paul
> =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=
=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D
> Paul Graham (grahamp@ee.byu.edu)
> 459 CB, Electrical Engineering Dept.
> Brigham Young University
> Provo, Utah 84602

Article: 33102
Subject: Re: Xilinx .bit file format
From: Neil Franklin <neil@franklin.ch.remove>
Date: 17 Jul 2001 21:41:31 +0200
Links: << >>  << T >>  << A >>
"Dave Brown" <dbrown@novatel.ca> writes:

> I have a .bit file that I converted to a .hex file with PromGEN. When I look
> at this .hex file, I noticed there is only one 32 bit dummy word before the
> syncronization word. I read in XAPP176 (from the Xilinx website) that there
> are supposed to be 2 32 bit dummy words. Has anyone else had similar
> problems? Just curious, because we can't get this .bit file to load into the
> FPGA. Is there a definitive description somewhere of the header that a .bit
> file should have for a Spartan II?

Try XAPP151. It only says Virtex/Virtex-E/Virtex-EM in it, but
Spartan-II are identical to smaller Virtex.


--
Neil Franklin, neil@franklin.ch.remove http://neil.franklin.ch/
Hacker, Unix Guru, El Eng HTL/BSc, Sysadmin, Archer, Roleplayer
- Intellectual Property is Intellectual Robbery

Article: 33103
Subject: Working Design - Anyone
From: "David Wright" <dwright@srtorque.com>
Date: Tue, 17 Jul 2001 14:58:06 -0500
Links: << >>  << T >>  << A >>
Has anyone had a working logic design in VHDL other than a few Cypress and
Xilinx insiders?

Logic was never this complicated before!

What a total waste of human intelligence.

It is far easier to build with discrete MSI/LSI parts or code in computer
language than get even something simple into a small CPLD or FPGA.





Article: 33104
Subject: Re: Working Design - Anyone
From: Dave Vanden Bout <devb@xess.com>
Date: Tue, 17 Jul 2001 16:11:16 -0400
Links: << >>  << T >>  << A >>
David Wright wrote:

> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?
>
> Logic was never this complicated before!
>
> What a total waste of human intelligence.
>
> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.

You might try looking at a few chapters of our online text at
http://www.xess.com/pragmatic-2_1.html.  It goes through a pretty explicit
explanation of how to get some VHDL designs compiled for XILINX FPGAs and
CPLDs using the Foundation software.  Can't help you with Cypress.


--
|| Dr. Dave Van den Bout   XESS Corp.               (919) 387-0076 ||
|| devb@xess.com           2608 Sweetgum Dr.        (800) 549-9377 ||
|| http://www.xess.com     Apex, NC 27502 USA   FAX:(919) 387-1302 ||



Article: 33105
Subject: Re: Using the Xilinx Alliance 3.1i/3.3i Tools under Linux
From: Paul Graham <grahamp@ee.byu.edu>
Date: Tue, 17 Jul 2001 14:17:51 -0600
Links: << >>  << T >>  << A >>
That is a great question, but I don't have any specific data to help
answer it.  Since the Win32 APIs are being emulated through Wine, I
would expect that Windows 2000 may actually be a little faster than
Linux in most cases, though, quite comparable.  With all of the files
locally installed, we noticed that Windows NT was usually a little
faster than Linux, but not considerably so.  These tests were done
with much older versions of Wine, so things may have improved for
Wine/Linux since then. I haven't done any head-to-head comparisons
between our new Wine setup and Windows 2000---we had a Windows 2000
machine at one time but the Xilinx Alliance 3.1i tools were
sufficiently broken under Windows 2000 at that time that we had to
revert back to Windows NT 4.0 to get any work done.

We have seen several instances where the memory subsystem of Linux
provided superior results to that of Windows NT 4.0, meaning that some
designs would completely run through the tools under Linux where they
wouldn't under NT with the same or similar physical and virtual memory
parameters.

We like using Wine and Linux for processing designs for several
reasons. First, it allows our entire workgroup (about 28 people) to
use our cluster of 16 dual-processor Linux servers to remotely process
designs; this should be possible with Windows NT and 2000, but our
experience has been that the multi-user nature of Linux appears
superior in stability, functionality, and manageability to the Windows
solutions for remote processing of designs.  Second, the Linux servers
are much cheaper than the HP-UX workstations we have used in the past;
for that matter, HP-UX will not be supported in future releases of the
Xilinx tools. Third, Linux is our main desktop platform, so Wine
provides a great alternative to booting into Windows to process
designs.

I should mention that, in the past, we have come across some designs
that did not complete under our old Wine setup. Thankfully, Wine
continues to mature and we have noticed that several designs which
didn't complete under Wine/Linux in the past complete just fine now.
I believe that part of the problems in the past had to do with the
fact that we could not easily keep up with the Xilinx service packs
since they did not install directly under Wine.  Now that the service
packs install under Wine and Wine itself has matured some, I expect
that we will see even better results.  In the past, about 97% or more
of the designs were successfully processed through the Xilinx Alliance
tools under Linux.  Considering that we use the tools a lot, the
Wine/Linux environment has been quite productive for us. To this
point, we have not encountered any designs that won't process with our
new Wine setup (Wine-20010510) for the Xilinx tools, but we might
encounter a few---you never know.

Hope that helps,

Paul
=====================================
Paul Graham (grahamp@ee.byu.edu)
459 CB, Electrical Engineering Dept.
Brigham Young University
Provo, Utah 84602
phone: (801)378-7206  fax: (801)378-6586


Tom Dillon wrote:

> Does Linux offer better performance than Win2000 for large designs?
> 
> 
> 
> >>>>>>>>>>>>>>>>>> Original Message <<<<<<<<<<<<<<<<<<
> 
> On 7/17/2001, 10:10:08 AM, Paul Graham <grahamp@ee.byu.edu> wrote
> regarding Using the Xilinx Alliance 3.1i/3.3i Tools under Linux:
> 
> 
> > I have created a Web page describing how to use the Xilinx Alliance
> > 3.1i/3.3i tools under Linux using Wine.  The URL is:
> 
> > http://splish.ee.byu.edu/tutorials/linux-alliance/linux-alliance.html
> 
> > This publicly available Web page describes the complete installation
> > process as well as how to set up users' environments to run the tools.
> > I also have included sections on how to run the Xilinx tools under
> > Wine and some of the caveats and work-arounds I have encountered.
> 
> > The great news is that the Xilinx Alliance tools install nicely under
> > Wine now as do the Service Packs and Device Updates, so creating and
> > maintaining the installations has become much easier.
> 
> > If you encounter any problems with my instructions, let me know.  I
> > have tried to be as complete as possible and have tested the
> > instructions fairly well, but there is always room for improvement.
> 
> > Enjoy,
> 
> > Paul
> > =====================================
> > Paul Graham (grahamp@ee.byu.edu)
> > 459 CB, Electrical Engineering Dept.
> > Brigham Young University
> > Provo, Utah 84602



Article: 33106
Subject: Re: regarding the constraints while writing VHDL code
From: John_H <johnhandwork@mail.com>
Date: Tue, 17 Jul 2001 20:19:50 GMT
Links: << >>  << T >>  << A >>
I don't mean to be harsh, but if you're doing Post Graduate work with VLSI
with large, complex algorithms you MUST know the underlying architecture
and you MUST be well versed in HDLs such as Verilog and VHDL as they apply
to efficient designs, at least to the extent that you have a good idea of
what the synthesis software will do with your design.

If you can tell me roughly how the synthesis tool will implement an adder,
an accumulator (add/subtract with load and clear!), a RAM, and a shift
register as examples, you are probably in good shape.  If you have no
idea, you are a great distance from being able to start a dissertation
defense.

Good luck!


sandeep wrote:

> Hello everybody,
>               Myself is Sandeep,and is a Post Graduate student and
> doing dissertation in JPEG baseline image compression using VLSI.
> I have written a code for 2-D DCT using VHDL and simulated it, but hte
> problem is that it is not fitting in any of the CPLD or FPGA. I have
> used Xilinx 2.1 tool.Is there any solution to this problem?????????/
> My doubt is that while writing the code is it necessary to take in to
> consideration the internal architecture of the FPGA or CPLD??? If yes
> then in which manner???????/
>
> Thanking you in anticipation
>
> Yours
> sandeep


Article: 33107
Subject: Fibre Channel info?
From: cyber_spook <pjc@cyberspook.freeserve.co.uk>
Date: Tue, 17 Jul 2001 21:45:10 +0100
Links: << >>  << T >>  << A >>
Can anyone point me at some information on Fibre Channel (Frame info,
protocal stuff etc).

Online documents or any thing else of use other that the basic
topological web sites.

Regards

Cyber_spook_man




Article: 33108
Subject: Re: Working Design - Anyone
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Tue, 17 Jul 2001 21:01:35 GMT
Links: << >>  << T >>  << A >>
I think you're just frustrated.  I've done designs with discrete MSI.  I'm
not going back.  Debugging with a solder iron and microscope is not a lot of
fun.

"David Wright" <dwright@srtorque.com> wrote in message
news:TQ057.1409$sE4.26519@news6.giganews.com...
> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?
>
> Logic was never this complicated before!
>
> What a total waste of human intelligence.
>
> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.
>
>
>
>
>



Article: 33109
Subject: Re: MCS file format
From: Philip Freidin <philip@fliptronics.com>
Date: Tue, 17 Jul 2001 14:09:44 -0700
Links: << >>  << T >>  << A >>
While the sync word looks wrong, it is actually correct.

The format of the MCS file created by promgen assumes that you will
be using a parallel configuration mode. If used for serial configuration,
you will need to shift from the LSB of each byte first.

When promgen creates a MCS file, it  reverses the bits  within each byte.
The 99 and 66 with bits reversed dont change, but AA becomes 55 and
viceversa.

For example, I tried, the command:

promgen -w -p mcs -u 0 test_5.bit

and it gives

:020000020000FC
:10000000FFFFFFFF5599AA660C000180000000E089
:100010000C800680000000980C80048000A0FCA7E3

For MCS files, the bits in every byte are reversed. If you want
unreversed bytes, promgen has a switch "-b" which leaves the
data in the same bit order as in the RBT file (see below) . The
-b switch only works for .HEX files.

NOTE. The definitive reference for the bitstream is always the .RBT file,
which is always read serially, left to right . This is the order the data must
end up going into the FPGA, in slave or master serial mode. For all other
config modes, it must end up being the logical equivalent.

Here is the beginning of the .RBT file

Xilinx ASCII Bitstream
Created by Bitstream D.27
Design name: 	test_5.ncd
Architecture:	virtex2
Part:        	2v40fg256
Date:        	Tue Jul 17 11:54:30 2001
Bits:        	339040
11111111111111111111111111111111
10101010100110010101010101100110            <<< AA995566
00110000000000001000000000000001
00000000000000000000000000000111
00110000000000010110000000000001
0000  etc ...


>From the online docs:

"In a bitstream contained in a BIT file, the Least Significant Bit (LSB)
is always on the left side of a byte. But when a PROM
programmer or a microprocessor reads a data byte, it identifies the
LSB on the right side of the byte. In order for the PROM
programmer or microprocessor to read the bitstream correctly,
the bits in each byte must first be swapped so they are read in the
correct order. "

For serial configuration, this is a load of bull. The issue is not which
is the LSB, it is which end of the byte is shifted out first. Xilinx is
making this needlessly more complicated than it needs to be, and
confusing the issue by refering to LSB position.

Processors do not "identify" the LSB. And for all processors I know,
a left shift is no harder or easier than a right shift. So the correct thing
Xilinx should have done, is documented clearly which end of the byte
needs to be shifted out first.

The first byte of the synchronization word is AA (page 20 of Xapp 138)
It must be shifted MSB first (see .RBT file above)
If promgen has been used to create a .MCS file, the bits have been
swapped, so shift out the LSB of the PROM data, as it is actually
the MSB of the original data.

For parallel configuration, such as SelectMap, the bit reversal in each
byte of the MCS file is exactly what you want. You will be connecting D0
of your EPROM to D0 of the FPGA, and D7 of the EPROM to D7 of the
FPGA. (the remaining 6 bits are left as an exercise for the reader)

So it really depends on how you are loading the FPGA. If you are
shifting out the data 1 bit at a time, just take the data 1 byte at a time,
and shift it out starting from the LSB. (assuming you are working from
a .MCS file)

If Xilinx promgen hadn't done its bit swapping, the data would be
shifted out from the MSB of each consecutive byte.

If you are configuring with a byte wide path, then just connect D0 to D0
and D7 to D7 (and the rest) and away you go.

For further reading, try Xapp 138 and 079



On Tue, 17 Jul 2001 09:47:58 -0600, "Dave Brown" <dbrown@novatel.ca> wrote:
>Using PROMGen I made an MCS format file and have tried loading this into a
>SpartanII, and it's not working. I opened up the MCS file and looked at it,
>and I noticed that the intial dummy word and synchronization word is listed
>as FFFFFFFF5599AA66. This looks wrong to me, the sync word is supposed to be
>AA995566. I've looked at several MCS files, and they all have the sync word
>as 5599AA66. Is this correct? The FPGA configuration doesn't get past the
>sync word when using PROMs that have this MCS file.
>Thanks,
>Dave
>
>

Philip Freidin
Fliptronics

Article: 33110
Subject: Re: regarding the constraints while writing VHDL code
From: "Kevin Neilson" <kevin_neilson@yahoo.com>
Date: Tue, 17 Jul 2001 21:10:29 GMT
Links: << >>  << T >>  << A >>

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message
news:3B55E5B4.87917BD4@gmx.de...
> sandeep schrieb:
> >
> > Hello everybody,
> >               Myself is Sandeep,and is a Post Graduate student and
> > doing dissertation in JPEG baseline image compression using VLSI.
> > I have written a code for 2-D DCT using VHDL and simulated it, but hte
> > problem is that it is not fitting in any of the CPLD or FPGA. I have
> > used Xilinx 2.1 tool.Is there any solution to this problem?????????/
> > My doubt is that while writing the code is it necessary to take in to
> > consideration the internal architecture of the FPGA or CPLD??? If yes
> > then in which manner???????/
>
> Hmm, VHDL looks a little bit like C, or better Pascal. This tempts
> programmers (especially the software guys) to write just the logic
> structure they want, without thinking (or knowing) how this translates
> to hardware. The same sad procedure that created "Hello World" programms
> requireing 10 MB Ram and 300+ MHz processors :-0
> Dont get me wrong, I dont want to kick your ass, but when programming in
> VHDL, one should "see" the hardware behind the copde, at least do a
> degree. I cant say with a few word, how to make it fit. But I do know,
> that there are many DCTs out there and the DO fit well into the FPGAs
> (not CPLDs, the devices are really small). Btw, what means does not fit
> into any FPGA?? Tried the Virtex-E series? With the 3.2 million gate
> device? IF your code doesnt fit in there, you really messed something
> up.
> Have a look at this sites.
>
> www.fpgacpu.org
> www.free-ip.com
>
> --
> MFG
> Falk
>
There are some app notes on the Xilinx website about DCT construction, and a
lot of commercial soft cores available.  There is a tradeoff of course
between speed and area.  You can do a DCT with a cheap microcontroller or a
DSP but it's going to take a lot of cycles.

Remember that when writing VHDL, you're not really writing code to perform a
function; you are designing a circuit and then writing the code that
describes the circuit.  I don't mean you have to draw a schematic first, but
if you don't have a picture of what the circuit should look like, then then
synthesizer may not either.

Check out the datasheets on the Xilinx website for Alliancecores; these will
give you an idea of the size you should be expecting and the number of
cycles required for an 8x8 DCT.

-Kevin



Article: 33111
Subject: Re: Working Design - Anyone
From: Ray Andraka <ray@andraka.com>
Date: Tue, 17 Jul 2001 21:32:31 GMT
Links: << >>  << T >>  << A >>
Yep,  somewhere around 15 million marketing gates worth this past year, all in
VHDL.  I grew up doing point to point solder on TTL packages, wirewrap,
designed several large PWBs that drew tens of amps and on and on.  I'll take
the VHDL entry over any of it.  It does take some time to become proficient...
figure about 6-12 months of intensive hands on time.  It helps immensely if
you already have a good hardware background.

THink in terms of hardware, not software.  Design hierarchically, that way
each function is encapsulated and can be tested by itself (using VHDL
testbenches in simulation).  Your upper levels will be mostly just structural
instantiation of your lower levels.  Once you get the hang of the lower
levels, the upper ones should be pretty easy to do (things should start
looking the same).

Best of luck, and don't let it eat you.

David Wright wrote:

> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?
>
> Logic was never this complicated before!
>
> What a total waste of human intelligence.
>
> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33112
Subject: Re: DLL Phase Locking in Division Mode
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 17 Jul 2001 14:49:02 -0700
Links: << >>  << T >>  << A >>
Yes.  The CLKFB path is supposed to match the CLKXX path, so BUFG's must be used in
both.

Austin

John_H wrote:

> Kevin Neilson wrote:
>
> > The DLL doesn't seem to take into account the delay
> > across the BUFG in 1/2x mode.  Am I wrong?
>
> If the output of the BUFG is what you want phase aligned to the reference, then
> the feedback should also go through a BUFG.  The 1/2x, 1x, and 2x outputs should
> all be phase aligned to each other so the feedback delay should also be matched
> to the clock distribution delay by using the extra BUFG.
>
> Austin - do you agree?


Article: 33113
Subject: Re: Drive strength of Xilinx DONE pin
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 17 Jul 2001 14:50:32 -0700
Links: << >>  << T >>  << A >>
Larry,

LVTTL 12 mA slow is the hardwired IO option for DONE, pulling down only
(open drain).

Austin

Larry Doolittle wrote:

> I have scanned all the Spartan-II/Virtex-I documentation I can find,
> and no place can I find the drive strength of the DONE pin.  Is it
> settable in the bitstream like a user I/O [*], or does it take a
> default value, and if so, what is it?
>
>     - Larry Doolittle   <LRDoolittle@lbl.gov>
>
> [*] That would only half make sense.  The pull-up (when DriveDONE
> is configured as documented in XAPP176) only applies after the
> configuration is loaded and CRC verified.  Logically, however, the
> pull-down strength can't be configured, because that happens before
> any configuration bits are read.


Article: 33114
Subject: Re: Fibre Channel info?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 17 Jul 2001 14:51:52 -0700
Links: << >>  << T >>  << A >>
 http://www.optimized.com/COMPENDI/

austin

cyber_spook wrote:

> Can anyone point me at some information on Fibre Channel (Frame info,
> protocal stuff etc).
>
> Online documents or any thing else of use other that the basic
> topological web sites.
>
> Regards
>
> Cyber_spook_man


Article: 33115
Subject: Re: I NEED XILINX FOUNDATION PROFESSIONAL
From: Anna Acevedo <acevedo@xilinx.com>
Date: Tue, 17 Jul 2001 15:07:11 -0700
Links: << >>  << T >>  << A >>
Hola Yoram,

    Xilinx offers academic institutions the XUP (Xilinx University Program) Through the
program your school can purchase  the full Foundation ELITE package at a discount price
of $595 (full price is $2,995) To purchase the software please contact Augusto Vazquez
<augusto_vazquez@ins.memec.com> from Insight Memec Mexico.

If there is budget problems and your school can not afford to purchase the software they
may apply for a donation.  The donation request must be submitted by a school
representative (Professor, Dept Head, Instructor) An on-line donation form is located
at  http://university.xilinx.com/univ/xup/ubroch/qform.htm

Please contact me directly if you have any additional questions.  Me puedes escribir en
español si te es más fácil.

Anna


*****************************
Anna M. Acevedo
Xilinx University Program
2100 Logic Drive
San Jose, CA 95124
PH: (408) 879-5338
FAX: (408) 879-4780

Email: anna.acevedo@xilinx.com
http://www.xilinx.com/programs/univ.htm
*****************************



Yoram Rovner wrote:

> Hello:
>
> I'm a student from Chile starting an FPGA project. I need to get the Xilinx
> Foundation Pro and I cant effort it(it is very expensive).
> If somebody can tell me where i can get that software or a similar, please write me.
>
> Sincerily
>
> Yoram Rovner
> yoram@puc.cl
> Santiago de Chile

--



Article: 33116
Subject: Re: Which Chip Family?
From: Ray Andraka <ray@andraka.com>
Date: Tue, 17 Jul 2001 22:12:21 GMT
Links: << >>  << T >>  << A >>
From what I've seen dealing with customers,  large quantity orders tend to have roughly
the same price relationships as single quantities.  ie, if they are getting a deep
discount on one part, they'll get similar discounts on other parts, often without even
needing to satisfy a large quantity order (by virtue of being a large volume
customer).  Since only single quantity prices are published publicly, they are the only
ones I can freely quote.  If on the other hand, you are piggybacking on an existing
stock or on an existing order, then that is a different story, but I think that is a
special case (by the same reasoning, one might argue that he should (must) design with
XC2000's because the company has a zillion of them in the storeroom).

I still stand by my assertion that except for special cases, the Spartan/4K shouldn't
be used in new designs.


Falk Brunner wrote:

> Ray Andraka schrieb:
> >
> > single unit pricing From www.avnetmarshall.com/dynamic/search:
> >
> > XC2S15-5VQ100  $8.96
> > XCS10XL-4VQ100 $12.76
> >
> > These are the cheapest I saw for each part.  The XC2S15 gives you 384 LUTs plus 4
> > block RAMs at 3/4 the price of the XCS10, which has 392 LUTs.  You give up all of
> > 8 LUTs, but gain 4 block RAMs, SRL16 capability (which is big in my book), faster
> > clocks, later technology and a longer time horizon.  I'll give up the 8 LUTs for
> > all that, especially considering the price difference.  Besides, I can use the 4
> > dual port block rams as 8 big LUTs if I wanted to.
>
> >From the technical point of view, I totally agree.
> But there are sometimes other reasons to choose Spartan over Spartan-II.
> If someone develops for a big company, which has good price conditions
> from Xilinx (Quantity), then you should (must) choose Spartan. Single
> unit pricing isnt applicable here.
>
> --
> MFG
> Falk

--
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com



Article: 33117
Subject: Re: Working Design - Anyone
From: Mike Treseler <mike.treseler@flukenetworks.com>
Date: Tue, 17 Jul 2001 15:18:42 -0700
Links: << >>  << T >>  << A >>
David Wright wrote:
> 
> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?

   yes

> Logic was never this complicated before!

   that is true.
   I couldn't afford 24,000 LUTs before.

> What a total waste of human intelligence.

  No worse than crossword puzzles or solitaire.

> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.

   So why not do an TTL style schematic?
   Nothing wrong with that.
   Brand A and X have free tools for that purpose.
   No more difficult than in the old days.

    --Mike Treseler

Article: 33118
Subject: Re: Working Design - Anyone
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 18 Jul 2001 10:38:11 +1200
Links: << >>  << T >>  << A >>
David Wright wrote:
> 
> Has anyone had a working logic design in VHDL other than a few Cypress and
> Xilinx insiders?
> 
> Logic was never this complicated before!
> 
> What a total waste of human intelligence.
> 
> It is far easier to build with discrete MSI/LSI parts or code in computer
> language than get even something simple into a small CPLD or FPGA.

 VHDL does have its frustrations :-), but there are other entry schemes, 
or even a mix.

 For the simpler end of the spectrum, we favour CUPL ( or Abel / AHDL /
PHDL ), 
these HDL's are less abstract than VHDL, and allow more direct
control/mapping 
to the resource, which becomes more important on the smaller devices.

 Taking the CUPL example, you have dot extensions, to connect to
registers,
and good field and macro structures, plus conditional compile
preprocessor.

As an examlple, this is snipped from a design on the desk:

 PINNODE 45 = BitPneq16;
 PROPERTY ATMEL {FOLD=BitPneq16}; 
 Field  BitP = [BitP3..BitP0];
 
 BitP.ck = CLK;
 BitP.ar = ENn;
 BitP.d = !BitP;

 BitP0.ce = BitPneq16; 
 BitP1.ce = BitPneq16 & BitP0;
 BitP2.ce = BitPneq16 & BitP0 & BitP1;
 BitP3.ce = BitPneq16 & BitP0 & BitP1 & BitP2;
 
 BitPneq16 = !(BitP : 'b'1111);

 This CUPL code creates a 4 bit, saturating UP counter, that is able to
be 
buried / logic_doubled in the ATF15xx families. (ie these 4 MCells can
also
be used for COM pin drive, or PT term cascade )
 Coded like this, we know exactly how many cells/product terms it will
need,
with VHDL, you are never sure :-)

 -jg

Article: 33119
Subject: Re: Coolrunner: availability
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 18 Jul 2001 10:46:28 +1200
Links: << >>  << T >>  << A >>
Martin Rice wrote:
> 
> Having just written some teaching materials based on the 5032 ISP device, 
> I find the part has disappeared.  

> Do I have to re-write everything, 

Depends on what you coded in - send me some examples, and I can
advise better.

We have ported XPLA tool chain designs to CUPL, without too much
problem, and
the PLA files exported by XPLA are close to Atmel fitter compatible.

The XPLA simulator is nice, but 'closed', and cannot create test
vectors.

You will need to recode test codes, but will get test vectors from CUPL. 

> and design a new target board?

No, the Atmel ATF1502/04 are pin compatible, and will stay 5V
compatible.

-jg

-- 
======= 80x51 Tools & IP Specialists  =========
= http://www.DesignTools.co.nz

Article: 33120
Subject: Re: conditional expression optimization
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 18 Jul 2001 10:54:09 +1200
Links: << >>  << T >>  << A >>
bugbear wrote:
> 
> This question seems to fall somewhere between circuit design
> and compiler design, so I'm hoping the denizens of this group
> may be able to address it.
> 
> This expression is "clearly" replaceable by a single "false"
> 
> (a eq 10 and a eq 30)
> 
> Is there a name for this optimisation?

In the Programmable Logic Devices field, this is called 'Logic
Minimisation'

> Is it commonly implemented?

In PLD tools, yes.
In Compiler tools, less commonly, tho I have seen compilers that would
take 
 IF ConstantExpression THEN
  .. block of code..
 END;
 and remove completely the block of code, if ConstantExpression
evaluated to false.
 
-jg

Article: 33121
Subject: Newbie Question
From: Tom Wyckoff <wyckoff@worldnet.att.net>
Date: Tue, 17 Jul 2001 23:56:14 GMT
Links: << >>  << T >>  << A >>
	I purchased Atmels' AT40K FPGA starter kit after reading that it "includes 
everything you need to get started......"  It didn't.  It came with a trial 
license for a synthesizer, but it was expired.  I have the open cores 
CDROMs.  What, if anything, can I install from the CDROM to make this 
device useful?  I have an idea for a simple project, but I am missing an 
essential piece of the software puzzle.

Thanks,

Tom Wyckoff


Article: 33122
Subject: Re: Newbie Question
From: Ben Franchuk <bfranchuk@jetnet.ab.ca>
Date: Tue, 17 Jul 2001 17:58:00 -0600
Links: << >>  << T >>  << A >>
Tom Wyckoff wrote:
> 
>         I purchased Atmels' AT40K FPGA starter kit after reading that it "includes
> everything you need to get started......"  It didn't.  It came with a trial
> license for a synthesizer, but it was expired.  I have the open cores
> CDROMs.  What, if anything, can I install from the CDROM to make this
> device useful?  I have an idea for a simple project, but I am missing an
> essential piece of the software puzzle.
> 
> Thanks,
> 
> Tom Wyckoff
Hove you contacted the dealer you got your kit from? You may be able 
to get a new License. Under No circumstances do you adjust your clock back.
License software knows!

The only other option is to set the clock back from BIOS Setup,
format your drive with DOS 6, and install windows and your kit
to a virgin machine.
Ben.
-- 
"We do not inherit our time on this planet from our parents...
 We borrow it from our children."
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.

Article: 33123
Subject: Re: Fibre Channel info?
From: Muzaffer Kal<muzaffer@dspia.com>
Date: Tue, 17 Jul 2001 17:36:49 -0700
Links: << >>  << T >>  << A >>
cyber_spook <pjc@cyberspook.freeserve.co.uk> wrote:

>Can anyone point me at some information on Fibre Channel (Frame info,
>protocal stuff etc).
>
>Online documents or any thing else of use other that the basic
>topological web sites.
>
>Regards
>
>Cyber_spook_man
>
>

does this help ?

http://209.26.30.186/t11/stat.nsf/fcproj?OpenView&Count=70

Muzaffer



Article: 33124
Subject: Re: processor core
From: "Tony Burch" <tony@BurchED.com.au>
Date: Wed, 18 Jul 2001 11:30:16 +1000
Links: << >>  << T >>  << A >>
John,

There is a list of free CPU cores at the Free IP Directory:
http://perso.cybercable.fr/alaimo/ipdirectory.html

Opencores:
http://www.opencores.org/cores/minirisc/
http://www.opencores.org/projects.shtml

Free-ip:
http://www.free-ip.com/
http://www.free-ip.com/risc8/index.html
(Free-ip already mentioned by Falk in this thread)

Ad alert :)  But likely of interest...
An 8051 on a low cost BurchED board (Spartan II):
http://www1.mmu1.edu.my/~khkoay/8051core.htm

I must also second Veronica and Falk's recommendation,
which is Jan Gray's great work at
http://www.fpgacpu.org/
Well worth a look, even if you don't decide
to roll your own.

John, maybe you could share any others
that you find, that can be added to the list.

Best regards
Tony Burch
http://www.BurchED.com.au
Lowest cost, easy-to-use
FPGA prototyping kits!


"John Smith" <xyz1625us@yahoo.com> wrote in message
news:8c835672.0107170405.224a2753@posting.google.com...
> I'm looking for a small processor core that fit in a 'cheap' fpga
> leaving some space for IO.
> Free or for little cost preferred.
>
> Thanks
> John





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