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Messages from 44075

Article: 44075
Subject: Re: burning a design
From: "Steve Casselman" <sc_no_spam@vcc.com>
Date: Tue, 11 Jun 2002 16:48:41 GMT
Links: << >>  << T >>  << A >>
Yes an FPGA can change it's own design.  It should be no problem to do a
partial reconfiguration by hooking into the Jtag on a Virtex. The old xc6200
let you get to the configuration lines from the inside of the device.

Steve

> Hmm, theoretical yes. But Iam doubtfull if this will work out really good.
A
> FPGA can not DIRECTLY change its own design, but another FPGA/uC can
> reprogramm it.




Article: 44076
Subject: Re: synthesis query: Xilinx + Synplify
From: John_H <johnhandwork@mail.com>
Date: Tue, 11 Jun 2002 16:58:41 GMT
Links: << >>  << T >>  << A >>
Bleah.  I go to 13 bits and it's still implementing a tree.  At least my big
comparator I mentioned is still implemented as a carry chain.

(BTW - I forgot to specify the "== 0" for each of the elements in the example
below)

I've had troubles with Synplify messing up my carry chains throughout my coding
experience.  One version to the next things seem to change for the worse.

I hope all my improvements don't get unimproved over time!


John_H wrote:

> I did something creative with a ( val[23:3]<(en?17:9) ) kind of
> quantity.  Try a structure like:
>
> assign out = { addr[  8] & mask[  8]
>              , addr[7:6] & mask[7:6]
>              , addr[5:4] & mask[5:4]
>              , addr[3:2] & mask[3:2]
>              , addr[1:0] & mask[1:0]
>              } < 5'h1;
>
> I'm using the < in your example rather than the == because Synplify
> *used* to not implement the equality.  Maybe it does now.  If I had my
> synthesizer in front of me I'd try it for you.
>
> Rick Filipkiewicz wrote:
> >
> > Rick Filipkiewicz wrote:
> >
> > > Is there any way of re-wrting the following simple counter code so that
> > > Synplify will merge the or'ed incrementer into the 1st LUT of the adder
> > > chain ? Or am I going to have to instantiate everything ?
> > >
> > > always @(posedge clk)
> > >     if (reset)
> > >         ra <= 0;
> > >     else
> > >         ra <= fra;
> > >
> > >     wire [5:0] fra = ra + ((count_en[0] | count_en[1]) ? 1 : 0);
> >
> > In fact I think this is a small example of a bigger thing where Synplify
> > fails to take advantage of the Xilinx architecture to synthesise fast [and
> > predictable] wide logic functions using the carry chains. In the same
> > struggle to grind down some timing paths I had to work on this function:
> >
> > reg [8:0] addr, mask;
> > ....
> >
> > assign out = (addr & mask != 0);
> >
> > It had been o.k. when the 2 vectors were only 8 bits but failed when
> > extended to 9. Doing it 2 bits at a time and using the carry chain to
> > propagate and voila ... *that* part of problem solved even unto 10 bits and
> > probably 12. Only downside was having to instantiate the MUXCYs although
> > Synplify 7.x & ModelSim 5.5+ can handle arrays of instances so it wasn't
> > too bad.


Article: 44077
Subject: Re: where did my MHz go!
From: kayrock66@yahoo.com (Jay)
Date: 11 Jun 2002 10:04:15 -0700
Links: << >>  << T >>  << A >>
Good point about the post -MAP time, I think thats best case timing,
and also, to answer your question "Does my choice of LOCs effect
circuit speed?"  the answer is yes, the placer does its best but if
you tie its hands then it can only do its best.  It gave a really good
hint about higher placement effort because it could see the long
routing delay.  Instead of using LOCs to stop your circuit from being
optimized away, connect your ports to primary I/O's- unassigned, and
see what the tool does for you.

and to answer the other gentlemans question about what to do with high
fanout nets, most modern synthesizers will reduce your fan (when
instructed) out by trying first to duplicate the driving logic, and
secondly by buffering.

Regards

Davis Moore <davism@NOSPAMxilinx.com> wrote in message news:<3D050729.E51EDBBC@NOSPAMxilinx.com>...
> Ken,
> 
> The post-MAP timing report will always report a clock frequency greater
> than the post-PAR timing report. This is because the post-MAP NCD
> does not contain any routing delay information as the design has not yet
> been placed or routed.
> 
> Ken Mac wrote:
> 
> [...SNIP...]
> 
>   Anyway, after mapping, the maximum clock frequency is reported to be
>   138.947MHz.
> 
>   But, after place and route, the max clock freq. is reported to be 91.166MHz.
> 
>   Where could I be losing so much MHz?  Can my choice of LOCs in the UCF
>   affect the max clock freq.?
> 
> [...SNIP...]

Article: 44078
Subject: Re: burning a design
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 10:24:17 -0700
Links: << >>  << T >>  << A >>
Even more fundamentally, all Xilinx FPGAs can instigate their own complete
reconfiguration, by using one of their outputs connected to PROGRAM, and pulling
it down. This triggers reconfiguration, and is a 100% safe operation, even
though it seems to violate a data sheet timing parameter.

Peter Alfke, Xilinx Applications
(back from a one-week seminar tour of Australia.
I was impressed by the enormous interest in Virtex-II and Virtex-IIPro!)
==================================
Steve Casselman wrote:

> Yes an FPGA can change it's own design.  It should be no problem to do a
> partial reconfiguration by hooking into the Jtag on a Virtex. The old xc6200
> let you get to the configuration lines from the inside of the device.
>
> Steve
>
> > Hmm, theoretical yes. But Iam doubtfull if this will work out really good.
> A
> > FPGA can not DIRECTLY change its own design, but another FPGA/uC can
> > reprogramm it.


Article: 44079
Subject: Re: Asynchronous Perhiperal Mode
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 10:27:49 -0700
Links: << >>  << T >>  << A >>
Mauricio, you answered your own question, and described it exactly right.
It has to be this way, otherwise you could not concatenate the lead device
with additional slave serial devices...
Peter Alfke
=====================
Mauricio Lange wrote:

> Hello, this question may be stupid, I think
> What happens with CCLK when in Asynchronous Pheriperal Mode (010)?
> AFAIK, in the other modes CCLK counts until n, where n is the lenght
> of the bitstream. So, in this mode, CCLK should be counting in
> something as bursts?
> To clarify, suppose that I send a byte of data, wait for the RDY/-BUSY
> to go high, send another byte, etc. and between every byte my delay is
> variable, suppose, 2us to 3 or 4us. CCLK should count at the internal
> rate, stop until the FPGA accepts a new byte, count again, etc?
> If that were not the case, what could happen if I wait too much
> without sending data to the FPGA?
> Note: I am using a XC4010XL FPGA
>
> Thank you very much
>
> Mauricio Lange


Article: 44080
Subject: Re: OFFSET constraint for internal clock
From: kayrock66@yahoo.com (Jay)
Date: 11 Jun 2002 10:30:02 -0700
Links: << >>  << T >>  << A >>
Aren't those contraints relative to the clock in the first place? 
With the clock nets you pretty much get what they give you.  Use the
DLL/DCM's to phase lock your clocks to each other.  You might be able
to do something with the BUFGMUXs if you're in a Virtex 2.  Another
topology is mux your you clocks inside the chip, bring them back out
and in to a DLL.  When you switch the mux you'll have to wait for the
DLL to re-synchronize.

Regards.

"Piotr" <foryt@poczta.pl> wrote in message news:<ae23bh$nkv$1@news.lublin.pl>...
> In my design internal clock is sourced from 4-to-1 multiplexer. Inputs of
> the multiplexer are connected to IPADs. Is there any possibility to add
> OFFSET_IN_BEFORE / OFFSET_OUT_AFTER constraint to this internal clock line.
> Thanks in advance,
> Piotr Foryt

Article: 44081
Subject: fpga and ultra highspeed counters
From: "Pat Ford" <pat.ford@nrc.ca>
Date: Tue, 11 Jun 2002 13:38:04 -0400
Links: << >>  << T >>  << A >>
Hi All;
 I have an interesting problem, one group of sensors outputs a signal which
varies with applied pressure (~35KHz). we use that signal to gate a 100MHz
counter, which we read to 24 bits. This system currently uses a PDP11, I was
thinking that a PCI card with a fpga could be set up to do this.
 After mentioning this to other it was decided to see about  bumping up the
input to 200MHz, so we can update faster. How hard will it be to do a 200MHz
gated, 24 bit counter in a FPGA? We need to do at least 16 and likely 24
counters, so is it possible to do more then one counter per fpga?
 I'm looking at Xilinx is that a sensible choice? Any recommendations on the
pci cards?
Thanks
Pat




Article: 44082
Subject: Re: synthesis query: Xilinx + Synplify
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 11 Jun 2002 19:28:23 +0100
Links: << >>  << T >>  << A >>


John_H wrote:

> Bleah.  I go to 13 bits and it's still implementing a tree.  At least my big
> comparator I mentioned is still implemented as a carry chain.
>
> (BTW - I forgot to specify the "== 0" for each of the elements in the example
> below)
>
> I've had troubles with Synplify messing up my carry chains throughout my coding
> experience.  One version to the next things seem to change for the worse.
>
> I hope all my improvements don't get unimproved over time!
>
> John_H wrote:
>

Even if you give it a hint from the back of the book:

wire [4:0] temp = {<your vectorised stuff>};

wire [4:0] carry_out;
assign carry_out[0] = temp[0] ? 1'b0 : 1'b1;
...
assign carry_out[4] = temp[4] ? carry_out[3] : 1'b1;

assign out = carry_out[4];

Synplify still doesn't get the plot! What this means is that Synplify is just not
looking for (or trying to optimise to) logic structures it could implement via the
carry chain. Even a simple wide ``and'' or ``or'' doesn't work although as far as I
can see Xilinx allowed a constant `1' or `0' on the the non-carry input of a MUXCY
for just this purpose.

What we need is a directive like ``syn_carry_chain'' or, to make quite sure,

``syn_this_is_a_carry_chain_so_just_do_it_and_dont_ask_questions''.


Article: 44083
Subject: Re: Problems initialising an FPGA - SPARTAN II
From: "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it>
Date: Tue, 11 Jun 2002 18:35:06 GMT
Links: << >>  << T >>  << A >>
"Benjamin Todd" <Benjamin.Todd@cern.ch> ha scritto nel messaggio
news:ae4ii0$9nt$1@sunnews.cern.ch...

> I have just moved from a -5 Spartan II to the faster -6...

Faster? As far as I know, -5 means 5 ns pin-to-pin delay, -6 means 6 ns
pin-to-pin delay. -5 should be faster.

--
Lorenzo



Article: 44084
Subject: Re: fpga and ultra highspeed counters
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 12:35:15 -0700
Links: << >>  << T >>  << A >>
This is easy. You could even go to 300 or even 400 MHz.

I suppose you use binary counters.
The easiest and fastest counter is - strange as it may sound - a ripple counter,
where the first toggling flip-flop is controlled by the enable.
The drawback is a settling time of < 100 ns after the counter has been stopped,
before you should start the read-out. If that is a problem, use a synchronous
counter at up to 200 MHz, with slightly higher power consumption.

You can pack dozens of these counters into the smallest Spartan-II or Virtex-E
device and hundreds of counters into the larger devices. Each counter takes 24
flip-flops or 24 Logic Cells, which translates into about 300 gates in
FPGA-speak.
To be on the safe side, I would assume "500 gates" worst case.
That gives you more than 60 counters in an XCV100E or the roughly equivalent
Spartan-II device, called XC2S100.

FPGAs make great counters!
Peter Alfke, Xilinx Applications
=======================

Pat Ford wrote:

> Hi All;
>  I have an interesting problem, one group of sensors outputs a signal which
> varies with applied pressure (~35KHz). we use that signal to gate a 100MHz
> counter, which we read to 24 bits. This system currently uses a PDP11, I was
> thinking that a PCI card with a fpga could be set up to do this.
>  After mentioning this to other it was decided to see about  bumping up the
> input to 200MHz, so we can update faster. How hard will it be to do a 200MHz
> gated, 24 bit counter in a FPGA? We need to do at least 16 and likely 24
> counters, so is it possible to do more then one counter per fpga?
>  I'm looking at Xilinx is that a sensible choice? Any recommendations on the
> pci cards?
> Thanks
> Pat


Article: 44085
Subject: Re: Problems initialising an FPGA - SPARTAN II
From: John_H <johnhandwork@mail.com>
Date: Tue, 11 Jun 2002 19:59:38 GMT
Links: << >>  << T >>  << A >>
...which is why we engineers are often confused by the timing values.

-6 is faster.


Lorenzo Lutti wrote:

> "Benjamin Todd" <Benjamin.Todd@cern.ch> ha scritto nel messaggio
> news:ae4ii0$9nt$1@sunnews.cern.ch...
>
> > I have just moved from a -5 Spartan II to the faster -6...
>
> Faster? As far as I know, -5 means 5 ns pin-to-pin delay, -6 means 6 ns
> pin-to-pin delay. -5 should be faster.
>
> --
> Lorenzo


Article: 44086
Subject: Re: synthesis query: Xilinx + Synplify
From: John_H <johnhandwork@mail.com>
Date: Tue, 11 Jun 2002 20:01:43 GMT
Links: << >>  << T >>  << A >>
I like the directive thought...

/* synthesis syn_for_all_that_is_holy_please_oh_please_use_an_FDSE */;


Rick Filipkiewicz wrote:

> What we need is a directive like ``syn_carry_chain'' or, to make quite sure,
>
> ``syn_this_is_a_carry_chain_so_just_do_it_and_dont_ask_questions''.


Article: 44087
Subject: Visual SourceSafe and VHDL files
From: "Jerry Francis" <jerryf@vt.edu>
Date: Tue, 11 Jun 2002 16:25:44 -0400
Links: << >>  << T >>  << A >>
Hi All,

I am trying to use Microsoft Visual Source Safe to store VHDL files and have
the $Log:  $ and $History:  $ keywords expand.  Can someone tell me where
and how I can modify the
settings so that VSS will use "--" for files of type *.vhd.  I read in the
help that I can modify the srcsafe.ini file to do this, but the help does
not describe in what section or how.


Thank you,
Jerry




Article: 44088
Subject: Re: OFFSET constraint for internal clock
From: Utku Ozcan <utku.ozcan@netas.com.tr>
Date: Tue, 11 Jun 2002 23:40:29 +0300
Links: << >>  << T >>  << A >>
Piotr wrote:

> In my design internal clock is sourced from 4-to-1 multiplexer. Inputs of
> the multiplexer are connected to IPADs. Is there any possibility to add
> OFFSET_IN_BEFORE / OFFSET_OUT_AFTER constraint to this internal clock line.
> Thanks in advance,
> Piotr Foryt

You can't use OFFSET for internal clocks. You must use
TIMESPEC, TIMEGRP, TNM commands in UCF to constrain.
For example, you have FF which drives your signal "foo".
This signal is clocked by an internal clock.
This signal is connected to PAD "foo_pad". In this application,
the constraint would be:

TIMESPEC TS_FOOPAD=FROM:FFS("foo"):TO:PADS("foo_pad"):TS_CLK / 2;

... where TS_CLK is the TIMESPEC you implemented for your internal clock.
This gives a rough OFFSET constraint at half period of internal clock.

Utku



Article: 44089
Subject: IBIS to Spice Translation (part2)
From: nospam@needed.com (Paul)
Date: Tue, 11 Jun 2002 17:12:03 -0400
Links: << >>  << T >>  << A >>
This figure is to accompany the text description in my previous post.

It is a PostScript picture of the Intusoft subcircuit representation
of the IBIS driver. The picture should be viewable in GhostScript or 
distillable with Acrobat Distiller. Keep everything from
"%!PS-Adobe-3.0" to "%%EOF".

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/m/moveto ld/l/lineto ld/c/curveto ld /h/closepath ld/r/stroke ld
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10.83333 (ENABLE)a 353 520 Z 41.1667 (100)a 581 Y 41.1667 (500)a
339 541 Z (INPUT)s 461 584 Z 41.1667 (820)a 463 539 Z 41.1667 (830)a
528 614 Z 41.1667 (300)a 128 555 Z -14.08333 (RB3)a 123 542 Z
27.5 (100Meg)a 180 555 Z 55.5 (C1)a 543 Y 20.5 (0.01p)a 65 542 Z
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18.08333 0 32 1.833333 0 (Logic 0 Ramp Gen)z 266 123 Z
6 (V=f\(8,840\))a 253 506 Z (3)s 259 202 Z (2)s 254 548 Z
6 (V=f\(850,8\))a 156 440 Z -4 (I=f\(8,3\))a 317 Y -4 (I=f\(2,8\))a
214 417 Z -27.83333 (R2)a 216 298 Z -27.83333 (R1)a 203 398 Z
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39.3333 0 32 3.91667 0 (1 ohm)z N 184.5 527 m 184.5 497 l r
184 497.5 m 209 497.5 l r 186.5 499 m
186.5 509.7695 192.5442 518.5 200 518.5 c r 186.5 215 m 186.5 185 l r
186 185.5 m 211 185.5 l r 202 186.5 m
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260 178 Z 68.6667 0 32 6.83333 0 (Logic 0)z 164 Y 16.91667 (Driver)a
[ 3 3 ] 0 D 0.5 G N 241 215 m 167 279 l r 433 129 m 433 129 l r
237 507 m 161 457 l r 0 G 12 0 0 12 325 463 M (Input )s 449 Y
73.75 0 32 7.33333 0 (Diode )z 435 Y 27.91667 (Clamp)a 274 344 Z
(Input )s 330 Y 73.75 0 32 7.33333 0 (Diode )z 316 Y
27.91667 (Clamp)a 180 650 Z 14.16667 0 32 1.416667 0 
(Intusoft IBIS2SPICE I/O Driver Subcct)z EM EP end showpage
%%PageTrailer
%%Trailer
%%EOF
************* end Intusoft IBIS2SPice Subcct Schematic *****************

Article: 44090
Subject: Multi Pass PAR
From: "Jim Raynor" <chris_cheung66@hotmail.com>
Date: Tue, 11 Jun 2002 21:25:05 GMT
Links: << >>  << T >>  << A >>
hi,

    When I use the Xilinx Foundation Multi-pass PAR, it always search for
the non-existing directory mppr_result.dir/*.*_0_0_0 and it says Error:
Unable to open directory...blah blah blah....

    Does anyone know how to fix that problem?

    Thanks




Article: 44091
Subject: Re: Problems initialising an FPGA - SPARTAN II
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 14:33:40 -0700
Links: << >>  << T >>  << A >>
John is right.
On all the modern (Virtex and Spartan class) devices, the larger speed-file
number describes the faster part. And the number has no physical meaning. We
gave up on that...

In the distant past, the speed-file number reflected the LUT-delay in
nanoseconds, but that scheme collapsed as the delays fell below 1 ns. We then
realized that a numbering scheme should not drive us towards zero as speed
increases.
Now we have room for progress into the picoseconds...
Peter Alfke
=========================
John_H wrote:

> ...which is why we engineers are often confused by the timing values.
>
> -6 is faster.
>
> Lorenzo Lutti wrote:
>
> > "Benjamin Todd" <Benjamin.Todd@cern.ch> ha scritto nel messaggio
> > news:ae4ii0$9nt$1@sunnews.cern.ch...
> >
> > > I have just moved from a -5 Spartan II to the faster -6...
> >
> > Faster? As far as I know, -5 means 5 ns pin-to-pin delay, -6 means 6 ns
> > pin-to-pin delay. -5 should be faster.
> >
> > --
> > Lorenzo


Article: 44092
Subject: Re: fpga and ultra highspeed counters
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 12 Jun 2002 09:34:46 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> This is easy. You could even go to 300 or even 400 MHz.
> 
> I suppose you use binary counters.
> The easiest and fastest counter is - strange as it may sound - a ripple counter,
> where the first toggling flip-flop is controlled by the enable.
> The drawback is a settling time of < 100 ns after the counter has been stopped,
> before you should start the read-out. If that is a problem, use a synchronous
> counter at up to 200 MHz, with slightly higher power consumption.

In most Freq Counter apps, this is no problem. The simplest use
alternate 
GATE and READ phases, with a cycle available for a read ( 35KHz in this
case )

This gives one result per two cycles in.

Next up is to alternate POS-POS then NEG-NEG times, which gives 2
results
every 2.5 cycles. Slightly more logic, for a good rate gain, plus you
get some edge effect averaging.

 By having effectively two counters, and more complex logic again, 
you could apply a fixed 'ripple delay', during which time the ripple 
counters are allowed to settle, then you read ( clear optional ), and
restart. eg apply a small say 24 cycle counter ( 5 bits ), 
and you can Short-Pause-For-Read, then restart, and have 
no other signals, so ripple counters can fly. 
 Probably a twisted ring / johnson ctr is best for the RDelay Ctr.

 Simple maths in the reader end gives dT = (ThisReading - LastReading) +
RDelay

Questions for Peter:
 What is the MAX toggle rate, for a ripple counter, in FPGAs ? ( GHz yet
?)
 
 Is there a simple ceiling number for the Rdelay counter. eg for like
registers,
and a 24 stage ripple counter, a Rdelay of 24 gives each stage one whole
clk time
for Ck -> next edge, likely conservative. 
 How about 12, for a half clock time for Ck-> next edge ?
 
( I realise registers are close to free in FPGA, but there may be speed 
gains in not over-doing the RDelay size )

-jg

> 
> You can pack dozens of these counters into the smallest Spartan-II or Virtex-E
> device and hundreds of counters into the larger devices. Each counter takes 24
> flip-flops or 24 Logic Cells, which translates into about 300 gates in
> FPGA-speak.
> To be on the safe side, I would assume "500 gates" worst case.
> That gives you more than 60 counters in an XCV100E or the roughly equivalent
> Spartan-II device, called XC2S100.

Article: 44093
Subject: MAP problem with RLOC'ed macros
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Tue, 11 Jun 2002 23:12:22 +0100
Links: << >>  << T >>  << A >>
I've contructed some logic using the Xilinx carry chain [see synthesis
query: Xilinx + Synplify] and used Synplify's xc_map, xc_uset, xc_rloc
to contruct an RPM that includes this and a few other LUTs.

In one design it worked fine but in another (its part of an SDRAM
controller) MAP bombs out with an error message saying it can't place
the F-LUT because of a conflict on the F input pins! As far as I can see
the only possible sources of conflict are:

(a) a MULT_AND having been mapped to the slice concerned.

(b) The G-LUT of the chain having been mapped to where the F-LUT should
go.

I can't find any reference to this in the answers database but there's
one vaguely related that's to do with MULT_ANDs.

If the problem is caused by (b) is there any way for Virtex to specifiy
that an LUT goes into a specific one of the 2 positions in a slice ? You
could do this for the 4K series but the obvious try of applying the .<F
| G> extension to the slice ident doesn't work.



Article: 44094
Subject: Re: IBIS to Spice Translation (part1)
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 11 Jun 2002 15:36:39 -0700
Links: << >>  << T >>  << A >>
Paul,

Hey this is nifty.  This should allow anyone to download the IBIS models
from any vendor, convert to spcie .model statements, and then simulate it in
spice.

Sounds like you did this for 3.3V driver model.

Do the free versions of spice support the simple transmission line model?

Austin



Article: 44095
Subject: Re: fpga and ultra highspeed counters
From: John_H <johnhandwork@mail.com>
Date: Tue, 11 Jun 2002 22:53:19 GMT
Links: << >>  << T >>  << A >>
Another idea for lots of capability in small space depending on the detail of your
needs.  If you want your read value accurate to a few nanoseconds *and* you need
access to multiple values with a few 10s of nanoseconds, this approach wouldn't
work.

Use a Virtex-II XC2V40 device.

Bring the gate in on the DDR input registers.

For N counters, use N lower count stages of only a few bits to add zero, one, or two
bits depending on the DDR gate.

Cycle through a dual-port CLB SelectRAM (or BlockRAMs for that matter), replacing
the LSbits with the live lower stage value and incrementing the upper bits by one as
appropriate.  This function can be done at a slower speed than the counter.

Read the count value directly from the dual-port RAM.

If you need a read strobe to catch a live count value rather than one that's a few
cycles off due to the cycling, you can add a little logic to preempt the normal
cycling and process the live value.

The resolution and capabilities you want could probably support up to 64 counters of
32 bits each at nearly 800MHz (based on DDR capabilities but possibly limited by
8-bit 0/+1/+2 adders) in a part you can get for a decent price.

A fun little project.


Article: 44096
Subject: LVPECL open-emitter interface to Virtex-II
From: "Huy Nguyen" <hnguyen@ll.mit.edu>
Date: Tue, 11 Jun 2002 14:56:36 -0800
Links: << >>  << T >>  << A >>
Hello, 

I am trying to interface a Virtex-II chip to a standard LVPECL device with open-emitter output driver.  This type of circuit requires a sink current for emitters, which is not provided by the differential termination scheme in Xilinx AppNote133. 

Is this differential termination scheme applicable for Xilinx's pseudo LVPECL drivers only, or also for standard LVPECL as well ?

Thank you.

Huy

Article: 44097
Subject: Re: 20,000 gates?
From: "Roger King" <roger@king.com>
Date: Tue, 11 Jun 2002 23:09:02 GMT
Links: << >>  << T >>  << A >>
Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really
low number, it looks like I can only develop extremely simple projects.



"Roger King" <roger@king.com> wrote in message
news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com...
> Is 20,000 gates enough for creating a nice project? What are some projects
> one can create by using 20,000 gates? I am trying to decide if 20,000
gates
> fpga board would be sufficient for a hobbyist that wants to use it for
about
> 2 years.
>
> I have another question. How many megs of RAM will I be able to develop
> using 20,000 gates fpga? I mean if I want to use the fpga as a ram.
>
>
>
>



Article: 44098
Subject: Re: fpga and ultra highspeed counters
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 16:10:54 -0700
Links: << >>  << T >>  << A >>


Jim Granville wrote:

> Questions for Peter:
>  What is the MAX toggle rate, for a ripple counter, in FPGAs ? ( GHz yet?

Barely.
The flip-flops in Virtex-II are very fast, but the feedback from Q to D is very
general, and thus relatively slow, so the loop has a delay of just around one ns,
which means 1 GHz is barely possible. ( I had 420 MHz in XC4000XL 4 years ago!).
There is a one-bit prescaler in each DCM which is faster, but has no logic around it.

Hi, Jim. I was in Sydney and Melbourne, just around the corner. Thought of you...

Peter



Article: 44099
Subject: Re: 20,000 gates?
From: Peter Alfke <Peter.Alfke@xilinx.com>
Date: Tue, 11 Jun 2002 16:27:45 -0700
Links: << >>  << T >>  << A >>
Watch out for CLB-count.
One CLB had 2 LUTs/flip-flops in XC4000,
then four of them in Virtex,
and now eight LUTs/flip/flops in Virtex-II.
There are architectural reasons for these changes, but they make CLB count
meaningless, unless you specify the family.
Peter Alfke

Roger King wrote:

> Ok, let me give you a better statistic, 384 CLBs? 384 sounds like a really
> low number, it looks like I can only develop extremely simple projects.
>
> "Roger King" <roger@king.com> wrote in message
> news:CUmN8.248826$ah_.140060@news01.bloor.is.net.cable.rogers.com...
> > Is 20,000 gates enough for creating a nice project? What are some projects
> > one can create by using 20,000 gates? I am trying to decide if 20,000
> gates
> > fpga board would be sufficient for a hobbyist that wants to use it for
> about
> > 2 years.
> >
> > I have another question. How many megs of RAM will I be able to develop
> > using 20,000 gates fpga? I mean if I want to use the fpga as a ram.
> >
> >
> >
> >




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