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Messages from 44225

Article: 44225
Subject: Can someone who is not a student use Xilinx Foundation 2.1i Student
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Fri, 14 Jun 2002 03:03:29 -0500
Links: << >>  << T >>  << A >>
        I am wondering if it is possible to run Xilinx Foundation 2.1i
Student Edition even if that person is not a student.
Obviously, the software itself is called "Student Edition," so it seems
like I have to be a student to use it, but XESS Corp.
(http://www.xess.com/prod023.php3) which used to carry Xilinx Foundation
2.1i Student Edition, doesn't really say if a non-student user is
allowed to use it.



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 44226
Subject: Re: 20,000 gates?
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 14 Jun 2002 10:17:37 +0100
Links: << >>  << T >>  << A >>


Peter Alfke wrote:

> Gate count is known to be a meaningless measure of FPGA capability.
> Take the simple case of a Xilinx look-up table.
> Xilinx counts it as about 6 gates ( 12 gates together with the associated
> flip-flop).
>
> The user might see it as a single gate, or, at the other extreme, as a 16-bit
> shift register, in which case it is worth at least sixty ASIC gates.
> Anything with an uncertainty range from 1 to 60 is a lousy measuring stick.
>
> And how do you count clock management, carry, I/O flexibility etc ?
> Five-to-one? Just give up, and realize that it's futile!
>
> Peter Alfke, Xilinx Applications
> =================
>

Peter,

I don't think you're being entirely fair here since its Xilinx themselves that
insist on continuing to use the ``marketing gate'' count and its worse than that
since it not only appears in marketing glossies but actually makes it into the
data sheets. So anyone without the healthy scepticism (o.k. cynicism) brought on
by a couple of dozen years reading marketing waffle might be forgiven if they get
confused!

Its even worse since the ``waffle gate'' count is actually embedded in the device
type scheme. The Virtex-2 numbering scheme is the worst example so far where e.g.
on a like for like comparison an XC2V1000 =~ XC400E.

So a suggestion: Send this to where the Dodos went [in the same way Xilinx changed
the speed grade numbering from LUT Tpd to an abstract number where bigger =
faster] and just number the devices in sequence from the smallest to the biggest
by, for example, the relative LUT count. Or maybe the number of LUTs to the
nearest 100 followed by the number of BRAM bits to the nearest KB

XC2V50 ->     XC2V005009
XC2V1000 -> XC2V102090

A bit like the numbering scheme Micron use to describe SDRAMs and SDRAM DIMMs.



Article: 44227
Subject: Re: MAP problem with RLOC'ed macros
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 14 Jun 2002 10:28:58 +0100
Links: << >>  << T >>  << A >>


Ray Andraka wrote:

> Rick Filipkiewicz wrote:
>
> >
> > In the sprirt of this thread I'd like to add a new directive:
> >
> > syn_dont_buffer_signals_or_replicate_luts_since_it_always_makes_things_worse
> >
> > or
> >
> > syn_if_you_cant_reduce_fanout_by_replicating_ffs_then_leave_the_net_alone...
>
> ...and_if_it_is_an_instantiated_ff_then_don't_replicate_it_either
>

absolutely!! If the instantiated FF is a domain crosser then replication is a
total killer [I wonder if any of the s/w engineers writing Synplify code have ever
had their asses bitten by a once every 4-5 hours  metastab failure - somehow I
doubt it!].

So far, until reading John's and your comments, I've been making the naive
assumption that by instantiating I'd avoid this problem at least for synthesis
(what MAP & PAR get up to is a whole other mess). Now I'm worried and will have to
go & put in some sort of post synth check, maybe even go to the extent of
synthesising the domain crossing modules separately and use NGDBUILD to integrate
the EDIFs.



Article: 44228
Subject: 6505 ip core
From: "tony" <nospam@nospam.com>
Date: Fri, 14 Jun 2002 09:48:57 GMT
Links: << >>  << T >>  << A >>
Someone tested this m6505.tdf cpu ip core for Altera?
http://shimizu-lab.dt.u-tokai.ac.jp/pgm/m65/index.html

Regards.

Antonio

To contact me: panfilo58 (at) hotmail.com




Article: 44229
Subject: ISE 4.2i and Synopsys Design Compiler
From: Andreas Wassatsch <wassatsch@mppmu.mpg.de>
Date: Fri, 14 Jun 2002 12:24:16 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------3B1049327CC3BEA92B9E39BF
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hello,

i'm try to switch my design flow from ISE4.1i to ISE4.2i, but i can't
find in the full ISE4.2i installation the nessecary synopsys synthese
library files (*.db, *.sdb, ...) for the Design/FPGA-Compiler.

Unfortunately i can't switch to the FPGA Compiler II due to the limeted
VHDL language support without an intensive adaption of my vhdl sources.

Has anybody a good idea to solve this problem ?

thanks


Article: 44230
Subject: Re: ISE 4.2i and Synopsys Design Compiler
From: Andreas Wassatsch <wassatsch@mppmu.mpg.de>
Date: Fri, 14 Jun 2002 12:59:51 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------4E4872DFE8FE5FA2749173AB
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

sorry i found the right cae lib cd in my package


Article: 44231
Subject: Re: Xilinx primitives & ModelSim
From: Ray Andraka <ray@andraka.com>
Date: Fri, 14 Jun 2002 12:15:22 GMT
Links: << >>  << T >>  << A >>
Try putting the type identifier in the generic declaration part of the
component declaration.  I think it is complaining because the types don't
match:

component FD
  --synthesis translate_off
  generic(TimingChecksOn: Boolean := FALSE);
  --synthesis translate_on
  port (D,C : in std_logic;
   Q : out std_logic);
 end component;
  attribute syn_black_box of FD : component is true;


David R Brooks wrote:

> On Thu, 13 Jun 2002 11:28:09 GMT, in comp.arch.fpga, Allan Herriman
> and Ray Andraka wrote:
>
> [snip]
> :
> :3.  Set the generic TimingChecksOn to FALSE when you instantiate the
> :FD.  You will need to put in pragmas to stop the synthesiser from
> :seeing the generics:
> :
> :ff : FD
> :  -- synopsys translate_off
> :  generic map (
> :      TimingChecksOn =3D> FALSE
> :  )
> :  -- synopsys translate_on
> :  port map (
> :    ....
>
> Hmm, I try that, & get "undefined identifier TimingChecksOn" messages.
> This seems to imply that TimingChecksOn is not a generic of FD. Have I
> missed something? (I am using the standard mapping of UNISIM).
>
> Also, is it possible to get the timing checks turned off when running
> VSIM from the GUI, or is it only possible from the command line? (I
> see no parameter in MODELSIM.INI that would control it.)
>
> TIA

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44232
Subject: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student Edition?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Fri, 14 Jun 2002 12:24:08 +0000 (UTC)
Links: << >>  << T >>  << A >>



"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> wrote in
message news:aec773$cg7$1@newsreader.mailgate.org...
>         I am wondering if it is possible to run Xilinx Foundation 2.1i
> Student Edition even if that person is not a student.
> Obviously, the software itself is called "Student Edition," so it seems
> like I have to be a student to use it, but XESS Corp.
> (http://www.xess.com/prod023.php3) which used to carry Xilinx Foundation
> 2.1i Student Edition, doesn't really say if a non-student user is
> allowed to use it.

Although I'm not a registered student at any institution, I don't have any
qualms about using student software, if I use it for self-study at home. If
they ask for an institution name when registering, I just enter 'Home'. I
don't think any human beings ever look at the registration details, anyway!

Leon
--
Leon Heller, G1HSM leon_heller@hotmail.com
http://www.geocities.com/leon_heller
Low-cost Altera Flex design kit: http://www.leonheller.com






Article: 44233
Subject: Re: fpga and ultra highspeed counters
From: "Pat Ford" <pat.ford@nrc.ca>
Date: Fri, 14 Jun 2002 08:40:58 -0400
Links: << >>  << T >>  << A >>
 They do BUT each card will only do 8 channels and the cost is high, and
they don't support the range of OS's that we are looking at.
 We are looking at the Nallatech
 Strathnuey kit with the XCV1000 fpga, any have opinions on this card?
http://www.nallatech.com/products/dime_select/strathnuey/index.asp
thanks for your help so far
Pat

"Jay" <kayrock66@yahoo.com> wrote in message
news:d049f91b.0206131216.10a6fa2d@posting.google.com...
> I don't want to spoil your fun but this sounds like something that
> might already be available.  Look at those PC intrumentation guys like
> National Instruments and the like, they may have something you can use
> or that can be gated.
>
> Regards
>
> p.s. PDP-11, I haven't seen those used for a while.
>
> John_H <johnhandwork@mail.com> wrote in message
news:<3D067F61.FADAE0B@mail.com>...
> > Another idea for lots of capability in small space depending on the
detail of your
> > needs.  If you want your read value accurate to a few nanoseconds *and*
you need
> > access to multiple values with a few 10s of nanoseconds, this approach
wouldn't
> > work.
> >
> > Use a Virtex-II XC2V40 device.
> >
> > Bring the gate in on the DDR input registers.
> >
> > For N counters, use N lower count stages of only a few bits to add zero,
one, or two
> > bits depending on the DDR gate.
> >
> > Cycle through a dual-port CLB SelectRAM (or BlockRAMs for that matter),
replacing
> > the LSbits with the live lower stage value and incrementing the upper
bits by one as
> > appropriate.  This function can be done at a slower speed than the
counter.
> >
> > Read the count value directly from the dual-port RAM.
> >
> > If you need a read strobe to catch a live count value rather than one
that's a few
> > cycles off due to the cycling, you can add a little logic to preempt the
normal
> > cycling and process the live value.
> >
> > The resolution and capabilities you want could probably support up to 64
counters of
> > 32 bits each at nearly 800MHz (based on DDR capabilities but possibly
limited by
> > 8-bit 0/+1/+2 adders) in a part you can get for a decent price.
> >
> > A fun little project.



Article: 44234
Subject: BGA package
From: "Minlin Fan" <minlinf@hotmail.com>
Date: Fri, 14 Jun 2002 15:06:30 +0100
Links: << >>  << T >>  << A >>
Is there BGA version of the Xilinx XC9500XL?

Minlin



Article: 44235
Subject: Re: MAP problem with RLOC'ed macros
From: hamish@cloud.net.au
Date: 14 Jun 2002 14:25:28 GMT
Links: << >>  << T >>  << A >>
Rick Filipkiewicz <rick@algor.co.uk> wrote:
> absolutely!! If the instantiated FF is a domain crosser then replication is a
> total killer [I wonder if any of the s/w engineers writing Synplify code have ever

Spent part of last week working around automatic duplication of inferred
domain crossers. Ouch. Found that using the new clock groups in 7.x
helps.

syn_keep and syn_preserve did not stop it from duplicating the critical
FFs. Only syn_maxfan = big plus setting the clock groups helped.
I couldn't go to 7.1 to use syn_replicate, as I discovered another
bug in that which has just about scared me off for life.

I think that Synplify should use the information from the clock
groups to know that it shouldn't duplicate domain crossers.

Hamish
-- 
Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>

Article: 44236
Subject: Re: MAP problem with RLOC'ed macros
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Fri, 14 Jun 2002 10:43:49 -0400
Links: << >>  << T >>  << A >>
Just a note on the ``push the big green button''  approach; it looks like
Xilinx is going in that direction too with their new ISE, I just been told
that the
Design Manager interface will be phased out within a year!
I looks like a never ending cycle: by the time you get familiar with the
tool
and you can learn the finer points they change it on you ....
Who knows, maybe in a few years we will get to the "single button"
approach...my old grandma will point and click and voila out comes first
class hardware :-)
Then maybe not!

jakab


Rick Filipkiewicz <rick@algor.co.uk> wrote in message
news:3D0936A3.3286B8DD@algor.co.uk...
>
>
> Ray Andraka wrote:
>
> > Aw man!   I'm still using mostly 7.03 because I have a couple projects
that started before 7.1
> > came out and I don't like switchin horses midstream.   I guess we now
will have to put the syn
> > keeps before the LUT (!!!).  That does get messy.  I'm still very
annoyed that Synplify thinks
> > that if it can figure out what is in a black box (by virtue of the black
box happening to be a
> > xilinx primitive) it has a right to muck with it.  As far as I am
concerned, if it is a black
> > box, it should not be mucked with PERIOD.  Of course the Synplicity
response is that they don't
> > see it as a real problem.  This is right up there with the tristate push
through issue.  It
> > completely wrecks the libraries I've put together over the past 3 years.
Guess I'll be
> > spending time looking for a work-around once again :-(
>
> Look like once again we have a good->v.good product being damaged by
post-IPO arrogance ... or is
> it just another symptom of the constant drift towards the ``push the big
green button''  approach ?
>
> I don't instantiate as much as you do but I absolutely concur that an
instantiated black box
> component should just be left alone, FULL STOP (US = PERIOD), no
questions - its *my* decision to
> do this *not* the tool's
> If I have to instantiate then its because the tool, together with any syn
directives/attributes, is
> not getting me what I want from the RTL so the last thing I want is yet
more messing about.
>
> Instead of wasting time on this rubbish [and tri-state push through is
even more ludicrous] why
> can't Synplicity get the register replication stuff working as well it did
for 5.x ?
>
> In the sprirt of this thread I'd like to add a new directive:
>
>
syn_dont_buffer_signals_or_replicate_luts_since_it_always_makes_things_worse
>
> or
>
> syn_if_you_cant_reduce_fanout_by_replicating_ffs_then_leave_the_net_alone
>
>
>
>



Article: 44237
Subject: Re: Xilinx primitives & ModelSim
From: "Michael Rhotert" <mrhotert@yahoo.com>
Date: Fri, 14 Jun 2002 16:53:01 +0200
Links: << >>  << T >>  << A >>
"David R Brooks"  wrote
>
> Also, is it possible to get the timing checks turned off when running
> VSIM from the GUI, or is it only possible from the command line? (I
> see no parameter in MODELSIM.INI that would control it.)
>
In the GUI, select:   Design>Load Design...
In the "VHDL" tab of the Load Design dialog window, there is a checkbox
called "Disable Timing Checks".

AFAIK, you have to do this everytime you startup Modelsim.

/Michael



Article: 44238
Subject: Re: BGA package
From: John_H <johnhandwork@mail.com>
Date: Fri, 14 Jun 2002 07:58:05 -0700
Links: << >>  << T >>  << A >>
From the...  um.  Data sheet?

http://direct.xilinx.com/partinfo/9500xl.pdf

Table 2: XC9500XL Packages and User I/O Pins (not including 4 dedicated
JTAG pins)
             XC9536XL XC9572XL XC95144XL XC95288XL
44-Pin PLCC     34       34
64-Pin VQFP     36       52
100-Pin TQFP             72        81
144-Pin TQFP                      117       117
208-Pin PQFP                                168
48-Pin CSP      36       38
144-Pin CSP                       117
280-Pin CSP                                 192
256-Pin BGA                                 192

Part numbers XC95288XL-7BG256C0696 and XC95288XL-7FG256C, for instance,
show stock on avnet.com at $25.74 each, for instance.  (Minimum
quantities are mentioned)

It's interesting to note they also have an "FG256" listed that doesn't
seem to be in the family data sheet above, but is in the ordering
information for the part, page 11 of

http://direct.xilinx.com/partinfo/ds055.pdf



              Description:   3.3
Minlin Fan wrote:
> 
> Is there BGA version of the Xilinx XC9500XL?
> 
> Minlin

Article: 44239
Subject: Re: MAP problem with RLOC'ed macros
From: John_H <johnhandwork@mail.com>
Date: Fri, 14 Jun 2002 08:05:34 -0700
Links: << >>  << T >>  << A >>
The "ise" interface, project navigator, isn't bad.  The only issue I
have with it is the inability to run parts of the process based on the
last run if there's a new edif.  I can execute FPGA_editor from the
command line, but I'd love an option of "Run Prev" from the menu.

It's just another wrapper for the same legacy tools.

New model year has different headlights and new sheet metal on the
trunk.



jakab tanko wrote:
> 
> Just a note on the ``push the big green button''  approach; it looks like
> Xilinx is going in that direction too with their new ISE, I just been told
> that the
> Design Manager interface will be phased out within a year!
> I looks like a never ending cycle: by the time you get familiar with the
> tool
> and you can learn the finer points they change it on you ....
> Who knows, maybe in a few years we will get to the "single button"
> approach...my old grandma will point and click and voila out comes first
> class hardware :-)
> Then maybe not!
> 
> jakab

Article: 44240
Subject: Re: MAP problem with RLOC'ed macros
From: Ray Andraka <ray@andraka.com>
Date: Fri, 14 Jun 2002 15:59:22 GMT
Links: << >>  << T >>  << A >>

John_H wrote:

> It's just another wrapper for the same legacy tools.
>
> New model year has different headlights and new sheet metal on the
> trunk.
>

And a totally rewritten owner's manual and a new ergonomic controls layout that
is supposed to be somehow better than last year's new ergonomic controls layout.

I feel sorry for the average designer that only does one FPGA every 18-24
months.  Not only does he have to deal with a new architecture everytime he
starts a design, but he also has to learn a whole new tools interface and work
arounds for the 'features' in the latest software that weren't there before.

Come on guys, let's just get what you have working right before you foist all
these new-fangled half-baked 'improvements' on us, and for God's sake, test your
new software to make sure you didn't break what did work.  The big green
push-button is a myth...stop chasing it!


--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 44241
Subject: Re: Power supply caps on PCB
From: rickman <spamgoeshere4@yahoo.com>
Date: Fri, 14 Jun 2002 12:25:04 -0400
Links: << >>  << T >>  << A >>
I won't argue that any of your recommendations are bad, but they don't
play together that I can tell.  In one place you say that a cap with a
SRF of 7 MHz is not good at 150 MHz which will require another cap with
an SRF of 150 MHz.  Later you say that this will cause a resonance
somewhere in the middle so you try to keep the SRFs within a decade.  

John_H wrote:
 
> below.  One graph I'm looking at shows an SRF of about 7MHz for a 1uF 1206.  The
> impedance at 7MHz is about 0.1 Ohm each.  The impedance drops to 1ohm around 250kHz and
> 150MHz.  While these values aren't bad, consider the current demands for 150MHz:  1/12
> Ohm (12 1uF caps in parallel, ignoring other parasitics for the moment) will keep the
> voltage tolerance within 100mV for 1.2A surges.  Maybe this is sufficient, but one cap
> with an SRF around 150MHz would give you performance nearly as good at 150MHz.  The 7MHz

> frequencies.  The caps need to be selected with a nice "spread" across the frequencies
> you're working with.  An SRF at 1MHz and another at 100MHz will actually give you
> problems - a resonance - at 10MHz, reducing the effects of even the one type of
> capacitor.  If the SRF values are kept somewhat close, the resonance shouldn't be a big
> issue (evaluate "somewhat?" I don't have a good value to suggest, but a decade is well
> beyond what I'd like to use).  My clock frequency is a major design consideration.  The

As you say, you are looking to keep the impedance below a given value
across a wide range of frequencies.  If we use your example, you can use
12 caps each with 1 ohm and get 1/12 ohms keeping the voltage noise
below 100 mV with up to 1.2 Amp surges.  

My rational for matching caps to pins is based on the idea the the pin
is the limiting impedance and resistance element.  The pin sets the
limit on the current a chip can draw and the surges that can be
supported.  The current is split among enough pins to keep each pin
current below this threshold.  Matching caps to pins then matches
impedance to the individual power points, i.e. a chip with 4 power pins
will draw about 10 times less current than one with 40 power pins and so
needs 10 times fewer caps.  Or just consider that the current surge in a
single pin will always be supplied by the cap with it.  


> The chip needs very low impedance to ground.  If you can't mount your cap on the same
> side of the board as the chip, you have to go through a via anyway, encountering loop
> inductance.  If you can mount the cap on the same side of the board but have to use
> more track to connect, the narrow line gives you loop inductance.  When you have the cap
> and the pins both connected to a plane - even the swiss cheese - the inductance is
> manageable.  One cap per power/ground pin pair isn't helping out much except for
> paralleling the impedances.

The issue of connecting the caps to the pins is not a bad as you make
it.  If you connect the chips to the power planes you use vias, when you
connect caps to the power planes you use vias, so the situation is no
different than connecting the caps directly to the chip pins.  This can
use a single via per pin rather than the two vias with the other
approach and add less parasitic inductance.  


In the many discussions here about this issue, one person has pointed
out that if you do a detailed analysis of the impedances, currents and
frequencies, you will find that the power plane does most of the
decoupling at the frequencies you really care about (harmonics > 400
MHz).  So often the best caps you use are really just providing bulk
capacitance.  

Some day I will build one of our boards with no decoupling caps and see
how well it works.  Then if needed I will add them a few at a time to
see what it really takes to make it work.  I think the bottom line is
that this is largely voodoo and a little experimentation will replace a
lot of analysis.  Now if I only had a temperature chamber to do the
testing in since I believe this is exacerbated by cold.  


-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 44242
Subject: Xilinx JTAG embedded programming
From: "Minlin Fan" <minlinf@hotmail.com>
Date: Fri, 14 Jun 2002 17:28:08 +0100
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.

------=_NextPart_000_0014_01C213C8.D97BEE80
Content-Type: text/plain;
	charset="gb2312"
Content-Transfer-Encoding: quoted-printable

Except the Xilinx application note "Xilinx ISP using an embedded =
microcontroller", is there any other information regarding JTAG embedded =
programming (ISP)? Cheers.

Minlin



Article: 44243
Subject: Re: MAP problem with RLOC'ed macros
From: nweaver@CSUA.Berkeley.EDU (Nicholas Weaver)
Date: Fri, 14 Jun 2002 16:32:17 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <3D0A1338.874D57EC@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:

>Come on guys, let's just get what you have working right before you
>foist all these new-fangled half-baked 'improvements' on us, and for
>God's sake, test your new software to make sure you didn't break what
>did work.  The big green push-button is a myth...stop chasing it!

And damnit, if you are going to spend time on doing automatic
"improvements", for god sakes generate placement with the design.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 44244
Subject: Re: Can someone who is not a student use Xilinx Foundation 2.1i Student
From: Winnie Hsu <Winnie.Hsu@xilinx.com>
Date: Fri, 14 Jun 2002 10:27:29 -0700
Links: << >>  << T >>  << A >>
Foundation 2.1i is really old and technology is not up to date.
Why don't you try downloading free WebPACK and use it legally.

-Winnie
--------------------------------------------------------------
All of my comments here represent personal opinions.
--------------------------------------------------------------

Kevin Brace wrote:

>         I am wondering if it is possible to run Xilinx Foundation 2.1i
> Student Edition even if that person is not a student.
> Obviously, the software itself is called "Student Edition," so it seems
> like I have to be a student to use it, but XESS Corp.
> (http://www.xess.com/prod023.php3) which used to carry Xilinx Foundation
> 2.1i Student Edition, doesn't really say if a non-student user is
> allowed to use it.
>
> Kevin Brace (In general, don't respond to me directly, and respond
> within the newsgroup.)


Article: 44245
Subject: Re: Power supply caps on PCB
From: John_H <johnhandwork@mail.com>
Date: Fri, 14 Jun 2002 17:32:08 GMT
Links: << >>  << T >>  << A >>
rickman wrote:

> I won't argue that any of your recommendations are bad, but they don't
> play together that I can tell.  In one place you say that a cap with a
> SRF of 7 MHz is not good at 150 MHz which will require another cap with
> an SRF of 150 MHz.  Later you say that this will cause a resonance
> somewhere in the middle so you try to keep the SRFs within a decade.

Spot coverage without consideration for the whole picture will introduce potential problems;
I didn't intend to recommend adding a single cap to the dozen with the low SRF.  If the SRFs
are distributed, the coverage is superb.  I was trying to point out that a single cap can do
the work of a dozen when you're far enough away from those dozen caps' SRF.  It could be a
mistake to only add the one cap at the higher SRF to complement the dozen.  It would be more
effective to have fewer caps across the frequency range than a quantity of single value caps.


Article: 44246
Subject: GCK input routing
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Fri, 14 Jun 2002 17:36:19 GMT
Links: << >>  << T >>  << A >>
I have a board with a VirtexE2000 part on it that was developed for another
project and I am adapting it for a new project. One of the issues is that I
have a Mictor connector that I will be using to interface a 32bit bus at
100Mhz from the FPGA to another *yet to be developed* board. It turns out
that a clock will be coming into the FPGA across this hi-speed connector (a
Mictor is a microstrip connector with 38 pins that is 50 ohms at 1NS,
according to AMP). The clock coming in will be coming to an IOPAD and not a
GCK input.

So, here is my question: "Can I route an IOPAD from one bank to the GCK of a
different bank and then distribute clocks from that GCK?"

Charles



Article: 44247
Subject: Re: MAP problem with RLOC'ed macros
From: "cfk" <cfk_alter_ego@pacbell.net>
Date: Fri, 14 Jun 2002 17:38:05 GMT
Links: << >>  << T >>  << A >>
And while were at it:
just_do_what_I_mean_even_if_it_is_not_what_I_said

"Ray Andraka" <ray@andraka.com> wrote in message
news:3D096C31.811CB7A3@andraka.com...
>
>
> Rick Filipkiewicz wrote:
>
> >
> > In the sprirt of this thread I'd like to add a new directive:
> >
> >
syn_dont_buffer_signals_or_replicate_luts_since_it_always_makes_things_worse
> >
> > or
> >
> >
syn_if_you_cant_reduce_fanout_by_replicating_ffs_then_leave_the_net_alone...
>
> ...and_if_it_is_an_instantiated_ff_then_don't_replicate_it_either
>
>
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>



Article: 44248
Subject: DCT in fpga ?
From: "Domagoj" <domagoj@engineer.com>
Date: Fri, 14 Jun 2002 11:02:28 -0700
Links: << >>  << T >>  << A >>
hi there,

i'm expected to evaluate multimedia DCT implementation alternatives in fpga,
any suggestions would be appreciated. Especially:
which number system should i use,
which approach (systolic arrays, cordics,...)
recommended algorithm for Virtex II... ?

thx in advance!

regards,
Domagoj
domagoj (et) engineer.com



Article: 44249
Subject: Re: MAP problem with RLOC'ed macros
From: Rick Filipkiewicz <rick@algor.co.uk>
Date: Fri, 14 Jun 2002 19:14:46 +0100
Links: << >>  << T >>  << A >>


cfk wrote:

> And while were at it:
> just_do_what_I_mean_even_if_it_is_not_what_I_said
>

Aha! Not to detract from your own phrase but its also my favourite Richard
Feynman quote., used to be at the bottom of all my emails. His variant was
``Listen to what I mean, not what I say''.




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