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Messages from 46450

Article: 46450
Subject: Virtex-II partial reconfiguration flow diagram
From: Theodore.Marescaux@imec.be (Theo)
Date: 30 Aug 2002 02:22:40 -0700
Links: << >>  << T >>  << A >>
Hi all,

Does someone know of a flow diagram for the Virtex-II partial
reconfiguration ? More specifically what I really need to know is
whether the V2 does twitch some pin when partial reconfiguration
succeeded or when it failed (e.g. on a CRC error).

Thanks in advance,
Theo

Article: 46451
Subject: XNF vs. EDIF
From: "E. Napoli" <etnapoli@unina.it>
Date: Fri, 30 Aug 2002 12:13:37 +0200
Links: << >>  << T >>  << A >>
Is there a difference between EDIF and XNF outside the syntax?
I mean, are they always exchangeable at the same point of the design flow?
Why should I use XNF instead of EDIF?

Thanks for your attention in advance,

ENapoli





Article: 46452
Subject: Availability of Xilinx Coolrunner II
From: Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de>
Date: Fri, 30 Aug 2002 10:15:24 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hallo,

what is the status of availability of the Xilinx Coolrunner II Parts. My
order, put on the premise " 6 weeks from order" , is after 6 weeks still on
the status "TDA" ( " to be announced") and I can't get any information for
the distributor.

Bye

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 46453
Subject: Re: Handel-C data widths
From: Andy.Nisbet@cs.tcd.ie (Dr. Andy Nisbet)
Date: 30 Aug 2002 03:19:50 -0700
Links: << >>  << T >>  << A >>
Hello,
the solution is to only supply the  9 least significant bits ...

i<-9 means take the 9 LSBs of i.

Go to help in DK1 and search on operators and you will find a description.

Cheers,
       Andy


govind.kharbanda@sli-institute.ac.uk (Govind Kharbanda) wrote in message news:<2f5db38d.0208290806.4721d7c1@posting.google.com>...
> Hi,
> 
> I'm writing with a query on use of the Handel-C language, please let
> me know if there is a more appropriate forum in which to post.
> 
> If you write code such as:
> 
>   /*
>    * lookup tables
>    */
> 
> ram <signed int> trig_256[320]    with {block = 1};
> ram <signed int> trig_2048[2560]  with {block = 1};
> 
>   /*
>    *  read in trig array into block ram (block = 1)
>    */
> 
>   chanin <signed int> input_trig_256 with { infile = "trig_256.dat" };
>   chanin <signed int> input_trig_2048 with { infile = "trig_2048.dat"
> };
> 
>   unsigned int 13 i;  // index for looping arrays
> 
>   i=0;
>   do
>   { 
>     par
> 	{
> 	  i++;
>       input_trig_256 ? trig_256[i];
> 	}
>   } while (i!=320);
> 
> 
>   i=0;  
>   do
>   { 
>     par
> 	{
> 	  i++;
>       input_trig_2048 ? trig_2048[i];
>     }
>   } while (i!=2560);
> 
> the compiler will complain that the index i does not agree with the
> size of the first array, trig_256, which only needs an unsigned 9 to
> access all its elements.  How do I get round this 'properly'? The
> following two work arounds have been found to function but aren't
> ideal
> 
> [1] declare a new index variable each time I need to loop an array of
> a different size - but code gets messy
> [2] do not declare size of RAM, but let Handel-C infer it i.e.
>   
>   ram <signed int> trig_256[]    with {block = 1};
> 
>   - doesn't work with more complex code
> 
> Gov

Article: 46454
Subject: problem configration spartan2 with prom.
From: arvindstomar@hotmail.com (arvind)
Date: 30 Aug 2002 03:48:20 -0700
Links: << >>  << T >>  << A >>
i am trying to configure the sprtan2 xc2s200 pq208 fpga with xc18v04
prom in "master serial mode" but the done pin is not getting high.
the prom is programmed successfully but the chacksum is not matching
when i am trying to read chacksum from PROM it is not matching by
desired chacksum.
the pull up for done pin is 3.3k and for init bar is 4.7k the initbar
is is coming high but the done pin is not getting high.
if anybody have idea about this problem pl'z help me.
thanks for any help.
arvind singh tomar

Article: 46455
Subject: Re: problem configration spartan2 with prom.
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Fri, 30 Aug 2002 14:22:08 +0200
Links: << >>  << T >>  << A >>
arvind wrote:
> 
> i am trying to configure the sprtan2 xc2s200 pq208 fpga with
> xc18v04 prom in "master serial mode" but the done pin is not
> getting high.
> the prom is programmed successfully but the chacksum is not
> matching when i am trying to read chacksum from PROM it is not
> matching by desired chacksum.

Hi
Have you used the same bitstream for the PROM and the JTAG configuration?
The startup clock must be "cclk" for a PROM and "JTAG Clk" for the JTAG
configuration.

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    10-12 Avenue de Verdun
Tel +33 1 46 52 53 11      F-92250 LA GARENNE-COLOMBES - FRANCE
Fax +33 1 46 52 53 02      http://www.IPricot.com/

Article: 46456
Subject: SDRAM - is concurrent auto precharge common?
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Fri, 30 Aug 2002 13:28:50 +0100
Links: << >>  << T >>  << A >>
I'm designing an SDRAM controller that is optimised for relatively small
data sets (within (page size * number of banks)). though will also handle
larger data sets equas well as designs I've already found.

I haven't found a core that optimises these localised accesses to get better
performance (so far).

The 'problem' is that the SDRAM I'm using has a useful feature where you can
swap banks (within the same row) on a cycle by cycle basis with precharging
of the old bank being taken care of automatically hence saving a few
precharge cycles.

This feature of the Micron SDRAM I'm using isn't common to all SDRAM
designs, but I'd like to know whether it is VERY common or just a useful
idiosyncracy of the Micron design.

The feature is called Concurrent autoprecharge.

If it proves relatively common I can see it being worth contributing this
core to say opencores even though they already have an SDRAM controller.

Paul



Article: 46457
Subject: Max SSO in Virtex2 (Simultaneously Switching Out
From: hugo <hugo_ecot@mentor.com>
Date: Fri, 30 Aug 2002 06:31:24 -0700
Links: << >>  << T >>  << A >>
Hi,

I want realise 8 bus with 40 line, so 320 line in SSTL2 standard are require.

What do you think about the SSO (Simultaneously Switching Output).

The Data sheet specifies a SSO per [power / groung pair] of 5 for the SST2_II_DCI. If i use a XC2V1500 (FF896), there is 8 equivalent [power / groung pair] per bank, and there is 8 banks in the VirtexII.

Ref:P260/261 virtex-II Hanbook 

So the total amount of SSO is 5*8*8=320. which is the number of SSTL2 line i expected . 
I am near the SSO limit but i don't exceed the virtex2 capabitilies. 

ARE YOU AGREE WITH THIS DEMONSTRATION? 

Thanks a lot for your opinion.

Hugo.

Article: 46458
Subject: Re: SDRAM - is concurrent auto precharge common?
From: spam_hater_7@email.com (Spam Hater)
Date: Fri, 30 Aug 2002 15:09:17 GMT
Links: << >>  << T >>  << A >>
Paul,

The place to check to see if it's "very common" is Intel's PC100
specification.

IME, all SDRAMs will do auto-precharge, but...

1) It's only useful if you always do the same size burst.

2) It doesn't really save you any cycles.  You activate C while
transferring from B, you can precharge A while transferring from B
also.

$.02,
SH7

On Fri, 30 Aug 2002 13:28:50 +0100, "Paul Baxter"
<pauljnospambaxter@hotnospammail.com> wrote:

>I'm designing an SDRAM controller that is optimised for relatively small
>data sets (within (page size * number of banks)). though will also handle
>larger data sets equas well as designs I've already found.
>
>I haven't found a core that optimises these localised accesses to get better
>performance (so far).
>
>The 'problem' is that the SDRAM I'm using has a useful feature where you can
>swap banks (within the same row) on a cycle by cycle basis with precharging
>of the old bank being taken care of automatically hence saving a few
>precharge cycles.
>
>This feature of the Micron SDRAM I'm using isn't common to all SDRAM
>designs, but I'd like to know whether it is VERY common or just a useful
>idiosyncracy of the Micron design.
>
>The feature is called Concurrent autoprecharge.
>
>If it proves relatively common I can see it being worth contributing this
>core to say opencores even though they already have an SDRAM controller.
>
>Paul
>
>


Article: 46459
Subject: Re: XNF vs. EDIF
From: Vikram Pasham <Vikram.Pasham@xilinx.com>
Date: Fri, 30 Aug 2002 10:10:29 -0500
Links: << >>  << T >>  << A >>

XNF (Xilinx Netlist Format) and EDIF (Electronic Design Interchange Format)
are two different netlist formats and there is no significant advantage of one
over the other. "Ngdbuild" can take either of these netlist formats and after
that the design flow is same. EDIF is an industry standard and XNF is Xilinx's
proprietary standard. Latest Xilinx tools only generate
EDIF files. Further info on EDIF format can be found at www.edif.org.


-Vikram


"E. Napoli" wrote:

> Is there a difference between EDIF and XNF outside the syntax?
> I mean, are they always exchangeable at the same point of the design flow?
> Why should I use XNF instead of EDIF?
>
> Thanks for your attention in advance,
>
> ENapoli


Article: 46460
Subject: Re: Question on Fast CPLDs
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 30 Aug 2002 17:22:32 +0200
Links: << >>  << T >>  << A >>
"Kenneth" <kenneth.lee@terapower.com.hk> schrieb im Newsbeitrag
news:3D6F189F.972F1C46@terapower.com.hk...
> Dear All,
>
> Currently I have a design which is quite simple and am planning to
> implement it in a CPLD.  However, the target operating speed is
> around 300MHz.
>
> After searching, I found that some CPLDs from Xilinx and Lattice
> are claimed to be able to operate at more than 300MHz.  However,
> it seems that there is no PLL/DLL inside their CPLDs.  So how can
> they operate at this high frequency?  Does it mean that I need to

AFAIR the new Coolrunner-II have a clock doubler inside.

--
MfG
Falk




Article: 46461
Subject: Re: gate the main FPGA clk
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Fri, 30 Aug 2002 17:26:58 +0200
Links: << >>  << T >>  << A >>
"Denis Gleeson" <dgleeson@utvinternet.com> schrieb im Newsbeitrag
news:6f080894.0208291343.4746da5a@posting.google.com...

> My problem is this. I am feeding an FPGA with a 100MHz clock.
> Under certain conditions I want to feed this clock to a pin
> on my FPGA as an output.
> To allow for the condition I need to gate the Main clock
> with what I have below.
>
> assign Acquisition_Clk = qbar ? Main_clk:1'b0;
> //  Acquisition_Clk will be the output clk from the FPGA.
> //  qbar is the negated q from a previous D-type FF.
>
> What worries me is that I am feeding a CLK signal through
> a non clk path. The translation report even warns me as below:
>
> Checking expanded design ...
> WARNING:NgdHelpers:357 - clock net "Main_clk_ACLKed" has non-clock
> connections
>
> So if what Im doing is not advisable, what should I be doing to gate
> the main FPGA clk.

You can gate the main clock this way, BUT depending on how the above
equation is translated and how qbar is generated, the gated clock acn
contain runt pulses. If the device that receives the clock can handle this,
no problem, if not???
And perter is right, you better through this stone-age device away and get a
up-todate one.

--
MfG
Falk




Article: 46462
Subject: RAM in CCC behavioral FPGA
From: Charles Wagner <Charles.Wagner@irisa.fr>
Date: Fri, 30 Aug 2002 17:29:06 +0200
Links: << >>  << T >>  << A >>
In a SystemC behavioral specification I want to map an array
to a FPGA (Virtex) memory implementation (DesignWare memory model
"DW_ram_rw_s_dff " for example).
with Synopsys tools : CCC SystemC Behavioral Compiler, dc_shell, Memory
Wrapper Generator.

Has anybody been able to do this ?

Charles


Article: 46463
Subject: Re: XNF vs. EDIF
From: "Steve Casselman" <sc@vcc.com>
Date: Fri, 30 Aug 2002 15:56:20 GMT
Links: << >>  << T >>  << A >>
Xilinx went from XNF to XDL. XDL has all the routing pip information and is
a more physical language then XNF.

Steve


>>Latest Xilinx tools only generate
> EDIF files. Further info on EDIF format can be found at www.edif.org.




Article: 46464
Subject: Re: Virtex-II partial reconfiguration flow diagram
From: "Steve Casselman" <sc@vcc.com>
Date: Fri, 30 Aug 2002 16:06:19 GMT
Links: << >>  << T >>  << A >>
The CRC is checked when you do the startup command. The device will not go
through the startup if the CRC is wrong. When your doing partial
reconfiguration there is a good chance your not using the startup command.
If you reset the CRC before you load a packet and write the expected CRC at
the end you can read the status register to see if your configuration passed
(Bit 0 -- 0=OK, 1=ERR).

Steve


"Theo" <Theodore.Marescaux@imec.be> wrote in message
news:7b022d6a.0208300122.55ddd470@posting.google.com...
> Hi all,
>
> Does someone know of a flow diagram for the Virtex-II partial
> reconfiguration ? More specifically what I really need to know is
> whether the V2 does twitch some pin when partial reconfiguration
> succeeded or when it failed (e.g. on a CRC error).
>
> Thanks in advance,
> Theo



Article: 46465
Subject: Re: XNF vs. EDIF
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 30 Aug 2002 16:13:04 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <EAMb9.1545$Xs1.71868804@newssvr13.news.prodigy.com>,
Steve Casselman <sc_nospam@vcc.com> wrote:
>Xilinx went from XNF to XDL. XDL has all the routing pip information and is
>a more physical language then XNF.

Well, more XNF was a format xilinx did largely before EDIF took off.
Both are used to describe pre technology mapping netlists in the
Xilinx flow.

XDL is a post mapping, post placement, or post routing representation.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 46466
Subject: Webpack 4.2 Schematic
From: "Stephan Flock" <sflock@t-online.de>
Date: Fri, 30 Aug 2002 18:43:06 +0200
Links: << >>  << T >>  << A >>
I've been working with Foundation for quite a while and I'm now trying to
get familiar with Xilinx Webpack 4.2.
I'm mainly using schematic design entry and I have been using Abel as well,
which is unfortunately no longer supported by Webpack.

I would like to know, if it is possible to have a top level schematic spread
over more than one sheet, I tried this but couldn't get it to work.
Is there any detailed information on the treatment of nets between several
sheets on one level, with or without i/o taps etc. available somewhere?

Thanks and regards,
Stephan Flock



Article: 46467
Subject: Re: Crashes while reading from memory with Nios
From: kempaj@yahoo.com (Jesse Kempa)
Date: 30 Aug 2002 10:01:02 -0700
Links: << >>  << T >>  << A >>
Hi Christian,

Without actually trying this, I have a hunch you are corrupting your
program memory and/or data memory. You mention building your code with
a base of 0x1000 - the start address of your second memory area. This
is fine, but before writing any data to a specific address within that
memory area, you should take a close look at your .objdump and .nm
files (created during nios-build of your software based at 0x1000).
These will tell you how much memory is used for code & data (not
including dynamic allocation - i.e., stack usage).

In your case, writing data to 0x1200 is probably overwriting program
code, and causing the subsequent crash. Here is an example exerpt from
a .nm file I just compiled... it uses shared program/data memory
starting at address 0x40000. Since I am using the same memory for code
and data, data memory starts just after the code ends... here is the
portion of the .nm file showing where its "safe"  to start using
hard-coded addresses (well, safe in a relative sense... a software
engineer would never tell you this!):

00047cc8 A _nasys_uninitialized_storage
00047cc8 B _bss
00047cc8 D _edata
00047cc8 D _nasys_data_destination_end

The best option would be to look at this, open up your nios.h & nios.s
files, and bump down the program memory end address, and data memory
end address....after this you'll need to "make all" in your lib, and
then re-build your software. This will make an area of memory that is
completely safe for you to dink with. Alternatively, let the compiler
handle addressing as it does so well:

int some_integer;
int *some_ptr;

some_ptr = &some_integer;

and so forth....

Regards,

Jesse Kempa

Christian Kramer <RemoveThis_christian.kramer@isw.uni-stuttgart.de> wrote in message news:<aknd4p$e8t$1@news.uni-stuttgart.de>...
> I have the following setup:
> 
> One Nios processor (16 bit) with to areas of (internal) RAM.
> Both areas are about 2kbyte of size, one loacted at 0x0000 and one 
> located at 0x1000.
> 
> I have an "operating system" placed in the first memory area. It 
> receives over an UART software (C-Code, compiled with 'nb -b 0x1000 
> mycode.c') and writes it in the memory locateted at 0x1000, which is 
> working fine.
> After receiving the program-data, the program gets executed with
> asm(" PFX %hi(0x800)
>                       MOVI %g0,%lo(0x800)
>                       CALL %g0
>                       NOP   
>                 ");   
> This works fine, too.The software is running and I can accsess the 
> 7seg-Display on the Nios development board.
> But when I try to have the program writing to memory with:
> 
>     unsigned int * memptr;
>     memptr = (int *) 0x1200;
> 
>     *memptr= 0xabcd;      // if I remove this line, program works again
> 
> the processor crashes ( at least the program stops execution).
> 
> Has anyone an idea, what causes this crash?
> 
> I have the following ideas:
> 1.)  The program compiled with 'nb -b0x1000 mycode.c' is built to be the 
> only executable on the nios. Maybe there are  mess-ups with some of the 
> nios registers, caused by the operating system running before.
> 2.) I am using the wrong method to write to memory.
> 3.) It has something to do with the framepointer (I am not into 
> assembly, but I found a lot of  "%fp" in the objdump of my code. I 
> didn't find useful explainations on framepointer in the documentation.
> 
> Thanks for reading!
> Christian

Article: 46468
(removed)


Article: 46469
Subject: Re: gate the main FPGA clk
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 30 Aug 2002 17:49:12 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <6f080894.0208291343.4746da5a@posting.google.com>,
Denis Gleeson <dgleeson@utvinternet.com> wrote:
>Hello all
>
>Im new to this FPGA design stuff so any help or redirection
>will be appreciated.
>
>My problem is this. I am feeding an FPGA with a 100MHz clock.
>Under certain conditions I want to feed this clock to a pin 
>on my FPGA as an output.
>To allow for the condition I need to gate the Main clock 
>with what I have below. 

One possibility, on a more modern part: You could take the 100 MHz
clock, feed it through the DLL to get a 200 MHz clock as well, have
THAT be the clock on the Opad flip flop, and have the 100 MHz clock,
gated, be the input to that flip flop.  Voila, no clock glitching,
runt pulses, or anything.

>PS. I am targeting a xilinx XC3020

You're making a 3020 run at 100 MHz?  You sure you have the part
number right?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 46470
Subject: Re: gate the main FPGA clk
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 30 Aug 2002 11:43:48 -0700
Links: << >>  << T >>  << A >>

--------------56A484C579E7B454231617B2
Content-Type: text/plain; charset=us-ascii; x-mac-type="54455854"; x-mac-creator="4D4F5353"
Content-Transfer-Encoding: 7bit

Here is my empirical rule-of-thumb:

"One year in FPGA evolution is like 15 years in human life."

That means, a recently introduced device still has some maturing to do, as
all parents of teenagers are painfully aware of.
A 2-3 year old device is a joy to use, smart, mature, consistent, fast,
strong and full of energy like a human in his twenties to forties and
fifties.
A 4-5year old device is smart, mature and dependable, and deserves respect,
love, care and some forgiveness, like a human in his sixties and seventies.
Even older devices should be remembered and revered in their graveyard.

This analogy has its flaws:
The reliability-based lifetime of working silicon is much longer than 20
years. Silicon does not really age, if overstresses are avoided.
And the availability of old chips is also remarkable. XC3000 devices were
introduced 15 years ago, and can still be purchased today. But, please, use
them only for retrofitting old designs.
Because the newer device families are genetically far superior to their
ancestors.
Can't say that about humanity...

Peter Alfke, philosophically and a bit conservatively.



Article: 46471
Subject: The Prodigal Son
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 30 Aug 2002 14:22:54 -0700
Links: << >>  << T >>  << A >>
Xilinx welcomes Steve Knapp, back from 5 years trying his luck
elsewhere.
Some of you may remember his Optimagic Jumpstation.
Here we remember him as a hell of an Applications engineer,
a good writer, and a genuinely nice guy.
We are glad he found the way back home, where he belongs !

Peter Alfke, Xilinx Applications


Article: 46472
Subject: Silicon lifetime
From: hmurray@suespammers.org (Hal Murray)
Date: Fri, 30 Aug 2002 21:27:21 -0000
Links: << >>  << T >>  << A >>
>The reliability-based lifetime of working silicon is much longer than 20
>years. Silicon does not really age, if overstresses are avoided.

Are the failure rates of silicon significantly dependent on
temperature? (like tantalum caps, for example)

I'm interested in the case where there are no metal migration
type bugs in the design.  (I realize that may not be a valid
assumption.)  Are there always things like thin spots in wires
that make the tail of the curve temperature dependent?

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 46473
Subject: Re: gate the main FPGA clk
From: dgleeson@utvinternet.com (Denis Gleeson)
Date: 30 Aug 2002 14:42:08 -0700
Links: << >>  << T >>  << A >>
Hi Peter

Thanks for your response.
One of the things that concerns me is the number of pins on a device.
If it comes to it I am hoping to mount these devices on the PCB myself.
Certainly for prototypes anyway.

So in keeping to a PLCC84 package I see that I could get a XCS05XL
or XCS10XL at low cost in small quantities.  I see that I can even get
a PLCC84 XCS05 spartan device at a good price.

Can you comment on possible problems I might come across when gating the
100MHz
clk with say the XCS05XL.

Denis


Peter Alfke <peter@xilinx.com> wrote in message news:<3D6E9C74.10A4BF92@xilinx.com>...
> Denis, why are you designing something with, for, or in a 15-year old
> device?
> 100 MHz is easy today, but was not easy in 1987 when the XC3020 was
> designed.
> My suggestion is to use a much faster, bigger, and generally more
> sophisticated device with better software support,  like Virtex,
> Spartan-II, or Virtex-II devices. Much easier, cheaper, and more
> rewarding.  :-)
> 
> Peter Alfke, Xilinx Applications
> 
> Denis Gleeson wrote:
> 
> > Hello all
> >
> > Im new to this FPGA design stuff so any help or redirection
> > will be appreciated.
> >
> > My problem is this. I am feeding an FPGA with a 100MHz clock.
> > Under certain conditions I want to feed this clock to a pin
> > on my FPGA as an output.
> > To allow for the condition I need to gate the Main clock
> > with what I have below.
> >
> > assign Acquisition_Clk = qbar ? Main_clk:1'b0;
> > //  Acquisition_Clk will be the output clk from the FPGA.
> > //  qbar is the negated q from a previous D-type FF.
> >
> > What worries me is that I am feeding a CLK signal through
> > a non clk path. The translation report even warns me as below:
> >
> > Checking expanded design ...
> > WARNING:NgdHelpers:357 - clock net "Main_clk_ACLKed" has non-clock
> > connections
> >
> > So if what Im doing is not advisable, what should I be doing to gate
> > the main FPGA clk.
> >
> > Many Thanks
> >
> > Denis
> >
> > PS. I am targeting a xilinx XC3020

Article: 46474
Subject: Re: Silicon lifetime
From: Peter Alfke <peter@xilinx.com>
Date: Fri, 30 Aug 2002 15:01:01 -0700
Links: << >>  << T >>  << A >>
Hal, I am not a reliability expert. Other people may be able to answer this
question better than I can.
But I know that "20 year guaranteed life" is a basic assumption in many designs,
and everybody has seen the bathtub curves. Obviously, most electronic systems
are being scrapped much earlier, but the IC industry tries not to be the
limiting factor. Obsolecense is the driving force in almost all cases, with some
exceptions in military and telecom applications...
Peter Alfke
===============================================
Hal Murray wrote:

> >The reliability-based lifetime of working silicon is much longer than 20
> >years. Silicon does not really age, if overstresses are avoided.
>
> Are the failure rates of silicon significantly dependent on
> temperature? (like tantalum caps, for example)
>
> I'm interested in the case where there are no metal migration
> type bugs in the design.  (I realize that may not be a valid
> assumption.)  Are there always things like thin spots in wires
> that make the tail of the curve temperature dependent?
>
> --
> The suespammers.org mail server is located in California.  So are all my
> other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
> commercial e-mail to my suespammers.org address or any of my other addresses.
> These are my opinions, not necessarily my employer's.  I hate spam.




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