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Messages from 47650

Article: 47650
Subject: question on ISE 5.1 and SMP machines...
From: hombecker1962@hotmail.com (Dan)
Date: 1 Oct 2002 09:57:39 -0700
Links: << >>  << T >>  << A >>
I have a quick question.  We are looking to get a new computer to
simulate Virtex II pro (1 power pc processor).  I was curious as to
recommendations.  I see they recommend 2-3 gigs of ram for this
particular device.  Does anyone out there know if Xilinx ISE 5.1 runs
faster on dual processor SMP machines that are mainly dedicated to
that task (i.o.w. does it use multiple threads)? If so do you suggest
P4 ? AMD XP+?  I would think the large cache on the 2.8 GHz P4's would
be a big advantage.  Also RAMBUS is sort of expensive compared to DDR,
is it worth the  2-3x increase in price ?  We will probably go with 3
gigs of ram either way.  I have quite a bit of experience building
single processor machines, I would think I could build us one quite a
bit cheaper than getting something from Dell or Compaq, but
recommendations on stock machines would be great as well.  I'd read
the XEON was overrated for such applications.

TIA.

Article: 47651
Subject: Re: TCP/IP in FPGA
From: Robert Myers <rmyers1400@attbi.com>
Date: Tue, 01 Oct 2002 17:13:34 GMT
Links: << >>  << T >>  << A >>
geeko wrote:
> What are the chances of implementing a TCP/IP stack using VHDL anybody do
> anything similar.Can the Spartan FPGA be used to hold the design
> 
It's been done.  Check out google on

tcp offload "state machine"

for some perspective.



Article: 47652
Subject: Re: Where can i buy xilinx fpga online?
From: Alan Raphael <alraphael@yahoo.com>
Date: Tue, 01 Oct 2002 13:54:32 -0400
Links: << >>  << T >>  << A >>
Try Avnet at http://www.avnetmarshall.com/dynamic/search   Not all parts are 
available online, but you might find what you need.

Henrique wrote:
> Where can i buy xilinx fpga online?
> Tanks Henrique.


Article: 47653
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: David Rogoff <david@therogoffs.com>
Date: Tue, 01 Oct 2002 18:04:53 GMT
Links: << >>  << T >>  << A >>
1) why can't you just lift the pin? Is it a BGA package?

2) I saw someone do this once on a Virtex where he had more clocks
than GCLK pins. If you only need to clock a few things it may work.
He manually instatiated an SRL16 in the HDL code and wired the CLK pin
to a regular IO.  You'll have to search the Xilinx site for more info.

  David


Dali <dadicool@ifrance.com> writes:

> 
> Dali
> 
> Ho Wong wrote:
> > So is there a way at all to clock this process without having to use the
> > bufg? And is it possible to short the two pins together? (current non-global
> > to a global one)
> > "Dali" <dadicool@ifrance.com> wrote in message
> > news:3D98E4DF.3010100@ifrance.com...
> >
> 
> >>It doesn't work that way. In order to take advantage of the clock tree
> >>brovided by the BUFG primitive you need to use an IBUFG instead of an
> >>IBUF. So a normal IO pins does not do the job.
> >>
> >>For further details, look at the Xilinx Handbook.
> >>
> >>Dali
> >>
> >>Ho Wong wrote:
> >>
> >>>Hello. I'm using a pin to drive a process but the thing is that it's
> >>
> > already
> >
> 
> >>>been soldered onto a normal IO pin. I've been trawling through past
> >>
> > posts
> >
> 
> >>>and newsgroups and I still haven't found a answer yet. I'm just a
> >>
> > beginner
> >
> 
> >>>to fpgas so i'm not very familiar with the low level logics. I tried
> >>
> > doing
> >
> 
> >>>PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN
> >>
> > has
> >
> 
> >>>illegal connection  Would it be possible to short my normal IO to one of
> >>
> > the
> >
> 
> >>>dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
> >>>Webpack.
> >>>
> >>>
> >>
> >>
> >

Article: 47654
Subject: Re: design multiplier
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 1 Oct 2002 20:12:22 +0200
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag
news:3D98E9D5.DFC9BCDE@andraka.com...
> A delay lock loop.  It is an all digital analog to a PLL
                                          ^^^^^^^^^^^^^^
The new in-between technology.
;-))
SCNR.

--
MfG
Falk







Article: 47655
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 1 Oct 2002 20:24:11 +0200
Links: << >>  << T >>  << A >>
"Dali" <dadicool@ifrance.com> schrieb im Newsbeitrag
news:3D98E4DF.3010100@ifrance.com...
> It doesn't work that way. In order to take advantage of the clock tree
> brovided by the BUFG primitive you need to use an IBUFG instead of an
> IBUF. So a normal IO pins does not do the job.

Says Who?
It can be done, and it will work well in most cases. Its just a matter to
tell the software to do so.
The idea of IBUF - BUFG is right.
Since you are using Webpack, which uses XST as VHDL compiler, do the
following.
Instanciate the BUFG, connect it to the normal IO pin. (non-clock pin), use
the output of the BUFG for you processes (will wil then use a global clock
net)
Then you have to set a attribute for this input pin.

attribute clock_buffer: string;
attribute clock buffer of my_clock_input: signal is "ibuf";

These attributes are placed where the signal decalrations are placed too.
Its VITAL to use lowercase for "ibuf". Hello Xilinx, can you remove such
Verilog crap from a VHDL implementation??

--
MfG
Falk





Article: 47656
Subject: Re: Where can i buy xilinx fpga online?
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Tue, 1 Oct 2002 20:26:22 +0200
Links: << >>  << T >>  << A >>
"Henrique" <henrique@bmrio.com.br> schrieb im Newsbeitrag
news:a296425.0210010851.c52fc93@posting.google.com...
> Where can i buy xilinx fpga online?
> Tanks Henrique.

www.nuhorizons.com

--
MfG
Falk





Article: 47657
Subject: Re: Getting started
From: "RCU" <nemesis@icequake.no_spam.net>
Date: Tue, 01 Oct 2002 14:33:36 -0500
Links: << >>  << T >>  << A >>

> Possibly you could consider the B5-X300 board, with Xilinx
> XC2S300E FPGA, from BurchED to get you started
> http://www.burched.biz/b5x300.html

You've got me drooling.  I wish I could afford it.  (student here)

> The XC2S300E FPGA is more-than large enough
> to implement a MIPS core, and many other CPU cores.
> Some free or open source cores that are
> available on the web include 8051, PIC, 68HC11,
> Z80, 6502.  Opencores has some microprocessor projects
> http://www.opencores.org/projects/

Do you have anything maybe a bit smaller at around half the price?  I
just can't drop that much cash right now, as much as I'd like to.

> There is a great book called "Rapid Prototyping
> of Digital Systems - a Tutorial Approach", by

Thanks for that mention!  I will check it out.

> Hope that helps:)  Above all, enjoy and have fun!

Will do.  Thanks for the reply.


Article: 47658
Subject: Re: Where can i buy xilinx fpga online?
From: "Giuseppeł" <gziggio.pleasedontsendmeanything@tin.it>
Date: Tue, 1 Oct 2002 21:35:01 +0200
Links: << >>  << T >>  << A >>
At www.xilix.com online store ?

I bought some cpld and the service is very fast and relible.

Bye
Giuseppe

"Henrique" <henrique@bmrio.com.br> ha scritto nel messaggio
news:a296425.0210010851.c52fc93@posting.google.com...
> Where can i buy xilinx fpga online?
> Tanks Henrique.



Article: 47659
Subject: USB2 in FPGA?
From: "Theron Hicks" <hicksthe@egr.msu.edu>
Date: Tue, 1 Oct 2002 15:49:55 -0400
Links: << >>  << T >>  << A >>
Hello,
    I am developing an instrument that is currently communicating over a
special high speed parallel board.  The data rate is 6.4 million 8 bit words
per second.  The board works great but it costs in excess of $1600 US per
copy.  It also occupies a full sized PCI slot.  We are considering
implementing an alternative I/O arrangement such as USB2 or ethernet
(TCP/IP).  Is anyone aware of free-ware USB2 implemented in VHDL or some
other FPGA friendly technology?  Note: target FPGA  is a Spartan2E (or if
absolutely necessary, Virtex2).

Thanks,
Theron



Article: 47660
Subject: Re: USB2 in FPGA?
From: Jim Granville <jim.granville@designtools.co.nz>
Date: Wed, 02 Oct 2002 07:58:44 +1200
Links: << >>  << T >>  << A >>
Theron Hicks wrote:
> 
> Hello,
>     I am developing an instrument that is currently communicating over a
> special high speed parallel board.  The data rate is 6.4 million 8 bit words
> per second.  The board works great but it costs in excess of $1600 US per
> copy.  It also occupies a full sized PCI slot.  We are considering
> implementing an alternative I/O arrangement such as USB2 or ethernet
> (TCP/IP).  Is anyone aware of free-ware USB2 implemented in VHDL or some
> other FPGA friendly technology?  Note: target FPGA  is a Spartan2E (or if
> absolutely necessary, Virtex2).

USB2 to-the-pins is likely to be a big ask, and probably not cost
effective.
IIRC Philips have a USB2 <-> FIFO interface, that does all the PHY and
lowest layer bit serial stuff, giving the user a 30MHz 16 bit FIFO
interface.

Then Cypress, and TI have USB2 controllers, which are TurboC51 + USB2,
and these have DMA schemes for similar 16 bit interface speeds.
There are also USB2-ATA bridge devices, again mostly with C51 cores.

There are USB2 links from our page
http://www.designtools.co.nz/overview.htm

-jg

Article: 47661
Subject: Re: USB2 in FPGA?
From: "Paul Baxter" <pauljnospambaxter@hotnospammail.com>
Date: Tue, 1 Oct 2002 21:07:44 +0100
Links: << >>  << T >>  << A >>
www.opencores.com is a brilliant place to bookmark. They even have a USB2
core :)

"Theron Hicks" <hicksthe@egr.msu.edu> wrote in message
news:anctr2$2brl$1@msunews.cl.msu.edu...
> Hello,
>     I am developing an instrument that is currently communicating over a
> special high speed parallel board.  The data rate is 6.4 million 8 bit
words
> per second.  The board works great but it costs in excess of $1600 US per
> copy.  It also occupies a full sized PCI slot.  We are considering
> implementing an alternative I/O arrangement such as USB2 or ethernet
> (TCP/IP).  Is anyone aware of free-ware USB2 implemented in VHDL or some
> other FPGA friendly technology?  Note: target FPGA  is a Spartan2E (or if
> absolutely necessary, Virtex2).
>
> Thanks,
> Theron
>
>



Article: 47662
Subject: Re: USB2 in FPGA?
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 01 Oct 2002 16:08:43 -0400
Links: << >>  << T >>  << A >>
Theron Hicks wrote:
> 
> Hello,
>     I am developing an instrument that is currently communicating over a
> special high speed parallel board.  The data rate is 6.4 million 8 bit words
> per second.  The board works great but it costs in excess of $1600 US per
> copy.  It also occupies a full sized PCI slot.  We are considering
> implementing an alternative I/O arrangement such as USB2 or ethernet
> (TCP/IP).  Is anyone aware of free-ware USB2 implemented in VHDL or some
> other FPGA friendly technology?  Note: target FPGA  is a Spartan2E (or if
> absolutely necessary, Virtex2).
> 
> Thanks,
> Theron

I know you asked for an FPGA core, but did you try going back to your
board supplier and explaining to them the cost problem?  If you are
using sufficient quantities to justify a design change, I would bet they
would be willing to come down on the price if they knew they would be
losing a high volume customer.  I don't know what is on the parallel
board, but I bet it can be sold for well, well under $1600.  Unless it
has a large Virtex II part  :)

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 47663
Subject: xilinx free logic analyzer?
From: "luigi funes" <fuzzy8888@hotmail.com>
Date: Tue, 01 Oct 2002 20:21:23 GMT
Links: << >>  << T >>  << A >>
Hi all!
There is some free logic analyzer tool for Xilinx fpga?
I'm looking for anything similar to Signaltap for Altera.
Thank you in advance!

Luigi




Article: 47664
Subject: Re: Nios interrupt latency?
From: lsimsic@altera.com (Lara Simsic)
Date: 1 Oct 2002 13:27:47 -0700
Links: << >>  << T >>  << A >>
Hi Pete,

The Nios Development Kit comes with the nr_installuserisr() routine
which takes care of installing any user ISR and switching the context
when the interrupt occurs.  This means that you can write the ISR in C
and not have to worry about saving and restoring the context.

Matjaz gave a good recommendation of simulating the design in
ModelSim.  I have simulated the 32-bit reference design in the Nios
Development Kit v 2.11 with an ISR I created.  I used the
nr_installuserisr() routine.  The latency for entering the ISR was
around 100 cycles and exiting was 64 cycles.  The latency for entering
the ISR will vary depending on when the interrupt occurs since some
instructions cannot be interrupted.

The ISR handler that the nr_installuserisr() uses has to assume the
worst case and take care of every possibility.  For instance, it must
save all of the global registers to the stack since the ISR routine is
written in C and the compiler may have the ISR routine use the global
registers.  It must also save the ISTATUS register to the stack since
it will be calling the user ISR routine, and doing this will save the
STATUS register to the ISTATUS register.  Of course, there are other
things it must take care of similar to these such as making sure there
is no register window underflow.

If you need your ISR to execute faster than this, then you will need
to write the ISR in assembly.  You can look at the nios_isrmanager.s
file for reference.  SOPC Builder will place this file in the <project
directory>/src/lib directory of every project that requires it.  This
is the file that contains the nr_installuserisr() routine as well as
the code which switches the context.  I would also suggest that you
read the Nios Programmer's Reference Manual (it can be found in the
Nios installation and on the Altera web site at
http://www.altera.com/literature/lit-nio.html).  There is a section
which describes the difference between a simple exception handler and
a complex exception handler.  The simple exception handler can be
implemented without saving the context. If you violate any of the
requirements of the simple exception handler, then you need to make
sure the ISR properly switches the context (without corrupting
anything).

Lara

"Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<anbs98$dm0$1@planja.arnes.si>...
> Tri simulating with Modelsim. In a simple 32 bit configuration (512
> registers) it takes around 75 clk cycles to switch.
> 
> Matjaz
> 
> "Peter Sommerfeld" <peter@vtecna.com> wrote in message
> news:amvoa0$566$1@avvidasystems.com...
> > Does anyone have the ISR switch and release times for Nios? Ideally for
>  Nios
> > 2.1?
> >
> > -- Pete
> >
> >

Article: 47665
Subject: Re: question on ISE 5.1 and SMP machines...
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Oct 2002 20:36:23 GMT
Links: << >>  << T >>  << A >>
Memory needed depends on the size devices you are working with.  2GB is
fine for many, more will help on the really big ones.  Xilinx doesn't take
advantage of the second processor, however we use dual processor machines
so that we can still do some productive stuff on the computer while the
tools are running.  One caveat to that is that you don't want to run
something else that eats memory at the same time.  We just use the
standard SDRAM and a K7+ on an ASUS dual motherboard.  A while back
someone here benchmarked the xilinx tools against a P3 and a P4 and found
that the P4 did not provide anywhere near the speed up one would expect by
the clock rate increase.  Something to do with the instruction set mode
IIRC.

We found several bugs trying to run a large design on a new K7 under win2K
sp3.  First, there is a memory problem that stops the 4.2 mapper cold
running on win2k with sp3 installed.  If you use win2K don't install
microsoft's sp3.  Xilinx's 'fix' is to upgrade to 5.1.  %.1 has it's own
problems.  Our design runs fine under NT4 with 1GB installed memory (takes
a while but it runs), with the mapper running in 1hr 40 min.  The exact
same edif netlist takes a bit over 25 hours to get through map under 5.1
on a machine that is twice as fast and has double the memory.  Apparently,
the large RPMs bug is not really fixed with sp1.  Still trying to get a
solution on that one.



Dan wrote:

> I have a quick question.  We are looking to get a new computer to
> simulate Virtex II pro (1 power pc processor).  I was curious as to
> recommendations.  I see they recommend 2-3 gigs of ram for this
> particular device.  Does anyone out there know if Xilinx ISE 5.1 runs
> faster on dual processor SMP machines that are mainly dedicated to
> that task (i.o.w. does it use multiple threads)? If so do you suggest
> P4 ? AMD XP+?  I would think the large cache on the 2.8 GHz P4's would
> be a big advantage.  Also RAMBUS is sort of expensive compared to DDR,
> is it worth the  2-3x increase in price ?  We will probably go with 3
> gigs of ram either way.  I have quite a bit of experience building
> single processor machines, I would think I could build us one quite a
> bit cheaper than getting something from Dell or Compaq, but
> recommendations on stock machines would be great as well.  I'd read
> the XEON was overrated for such applications.
>
> TIA.

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47666
Subject: Re: DFT , Design For Test HELPPPPP
From: Ray Andraka <ray@andraka.com>
Date: Tue, 01 Oct 2002 20:46:14 GMT
Links: << >>  << T >>  << A >>
FPGAs offer a rather unique opportunity for testing.  If you reconfigure the FPGA
with a test program you can hammer the external interfaces with test sequences
that are much more controllable and that can work at design speed rather than
using boundary scan.  I've been doing FPGAs for 12 years now, and I can say that
internal failures are so rare that even if it did occur, the likelihood of it
showing up in your design with your test vectors is close to nil.  When FPGAs do
fail, it is at an I/O due to externally applied stress such as ESD or contention,
or in the mechanical connections to the pins/balls.  Take advantage of the
reconfiguration to test the interfaces exhaustively and test them hard.  This
checks out the platform, then your application program can be treated like
software in terms of testing (if it works in the first place and meets all timing,
that won't break).  I detail this method and describe the benefits in my paper
entitled "An FPGA Based Processor Yields a Real Time High Fidelity Radar
Environment Simulator", which is available for download at no cost.


Thomas Stanka wrote:

> X-Post without folowup isn't the best choice to spread your lack of
> wisdom :)
> X-Post to caf und clv without followup
>
> "Djohn" <deepucjohn@yahoo.com> wrote:
> >   I am now designing a Uart chip for study purposes. Now I am almost over
> > with my design and VHDL Coding .  I would like to integrate the DFT strategy
> > in the chip .
>
> Interesting excercise. But I have problem with _the_ DFT strategy.
>
> > 2) I have a fair good knowledge of JTAG . So If I integrate a JTAG circuitry
> > in the chip (the tap controller , data registers  and instruction
> > registers), will it become  DFT compatible?
>
> Answer your self: will the design be testable with this cirquit?
> If you just forgot to mention boundary scan, it might be the first
> step to DFT.
> DFT=Design For Testability, not design to fake test.
>
> > 3) What exactly is BIST ? How is it implemented ? Any online  tutorials or
> > good links ...
>
> BIST=Build in Self Test, any logic on chip, that tests your cirquit
> without external hardware is BIST.
>
> > 4) What is ATPG ? how is it implemented? Any online  tutorials .......
>
> Automatic Test Pattern Gerneration. Typical a Programm that generates
> testpattern for your cirquit.
>
> > 6) A comparison between these strategies? any links also welcome
>
> www.google.com is your best friend.
>
> Buzzwords:
> - atpg
> - bist
> - dft
> - marchtest (for RAM)
> - boundary scan
> - scanchains
> - scantest
> - LFSR
>
> For ATPG you could start at the homepage of synopsys or cadence
>
> I think you should start with some books concerning DFT, because it
> might be too complex reading all the papers concerning these themes
> without knowing where to start and where to go along.
> If you have more detailed questions, you might get more answers here.
>
> bye Thomas

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47667
Subject: Re: TCP/IP in FPGA
From: klonsky@hotmail.com (Noel Klonsky)
Date: 1 Oct 2002 13:59:25 -0700
Links: << >>  << T >>  << A >>
Hi, take a look at http://www.xilinx.com/xcell/xl39/xcell39_52.pdf
some multimedia terminal that has TCP/IP in hardware, virtex not spartan.

Noel

"geeko" <jibin@ushustech.com> wrote in message news:<anbq1u$csim4$1@ID-159027.news.dfncis.de>...
> hay
>  iam not looking for such a solution TCP/IP in hardware is it feasible
> 
> 
> "Janusz Raniszewski" <rniski@man.koszalin.pl> wrote in message
> news:3D994313.F5AB54AD@man.koszalin.pl...
> > > What are the chances of implementing a TCP/IP stack using VHDL anybody
>  do
> > > anything similar.Can the Spartan FPGA be used to hold the design
> >
> > Hello,
> > It is simple. You may implement some microcontroller core and ,,,,,, :-)
> > JanuszR
> >

Article: 47668
Subject: Re: xilinx free logic analyzer?
From: Austin Lesea <austin.lesea@xilinx.com>
Date: Tue, 01 Oct 2002 15:16:16 -0700
Links: << >>  << T >>  << A >>
 http://www.xilinx.com/prs_rls/0186chipscope.html

Austin

luigi funes wrote:

> Hi all!
> There is some free logic analyzer tool for Xilinx fpga?
> I'm looking for anything similar to Signaltap for Altera.
> Thank you in advance!
>
> Luigi


Article: 47669
Subject: Re: xilinx free logic analyzer?
From: "luigi funes" <fuzzy8888@hotmail.com>
Date: Tue, 01 Oct 2002 22:52:29 GMT
Links: << >>  << T >>  << A >>

Austin Lesea ha scritto nel messaggio <3D9A1EB0.BECE83A0@xilinx.com>...
> http://www.xilinx.com/prs_rls/0186chipscope.html
>
>Austin


Thank you!
But $495 is not exactly free...

Luigi




Article: 47670
Subject: Re: Nios interrupt latency?
From: kempaj@yahoo.com (Jesse Kempa)
Date: 1 Oct 2002 16:54:04 -0700
Links: << >>  << T >>  << A >>
Simulation is a good idea as this sort of thing will vary based on
your code... the CPU has instruction execution & ALU pipelines, making
individual TRAP instructions vary depending on what's already in the
pipe at the time of IRQ.

The thing to note is that the physical interrupt (TRAP instruction)
will complete pretty quickly... I just simulated an example using
off-chip SRAM for code/data memory, and a UART interrupt - it took 6
clocks from IRQ going high to TRAP being executed, and more 7 clocks
for TRAP to complete (its a really long instruction), for a total of
13 clocks between IRQ going high and jumping to whatever your vector
table is pointing at.

Now comes the ISR funnel - a piece of user code to save registers to
the stack and such. The default SDK includes a file called
"nios_isrmanager.s". The ISR "funnel" routine will get linked in and
its location assigned to the vector table when you initialize an ISR
with the canned "nrinstalluserisr()" routine. This funnel was designed
to be relatively safe at the expense of clock cycles... allot of
stores off to memory. When this code is added in, you get the grand
total between IRQ going high and entry to your ISR routine code (as
Matjaz simulated).

If you need faster ISR entry time, you can modify the funnel code
above and take out anything you don't deem necessary.

- Jesse Kempa


"Matjaz Finc" <matjaz.finc@fe.uni-lj.si> wrote in message news:<anbs98$dm0$1@planja.arnes.si>...
> Tri simulating with Modelsim. In a simple 32 bit configuration (512
> registers) it takes around 75 clk cycles to switch.
> 
> Matjaz
> 
> "Peter Sommerfeld" <peter@vtecna.com> wrote in message
> news:amvoa0$566$1@avvidasystems.com...
> > Does anyone have the ISR switch and release times for Nios? Ideally for
>  Nios
> > 2.1?
> >
> > -- Pete
> >
> >

Article: 47671
Subject: Re: Rounting of non-global IO pad to a GCLKIOB site.
From: Ray Andraka <ray@andraka.com>
Date: Wed, 02 Oct 2002 01:03:43 GMT
Links: << >>  << T >>  << A >>
Bad information.  You certainly can run a clock in on a regular I/O pin.
Instantiate an IBUF at the pin and feed that to a BUFG.  I don't think the tools
will automatically infer the BUFG in this case, but instantiation gets around it
just fine.  The main thing to note is that your clock will not have the controlled
pin to BUFG delay it had with the IBUFG so if your clock relationship with other
I/O pins is critical you need to be careful (and use a CLKDLL).

Dali wrote:

> It doesn't work that way. In order to take advantage of the clock tree
> brovided by the BUFG primitive you need to use an IBUFG instead of an
> IBUF. So a normal IO pins does not do the job.
>
> For further details, look at the Xilinx Handbook.
>
> Dali
>
> Ho Wong wrote:
> > Hello. I'm using a pin to drive a process but the thing is that it's already
> > been soldered onto a normal IO pin. I've been trawling through past posts
> > and newsgroups and I still haven't found a answer yet. I'm just a beginner
> > to fpgas so i'm not very familiar with the low level logics. I tried doing
> > PIN -> IBUF -> BUFG -> signal, but it told me the input pad net of PIN has
> > illegal connection  Would it be possible to short my normal IO to one of the
> > dedicated I,GCK ? I'm using a Spartan 2 programming in VHDL with the ISE
> > Webpack.
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 47672
Subject: Re: USB2 in FPGA?
From: "Theron Hicks (Terry)" <hicksthe@egr.msu.edu>
Date: Tue, 01 Oct 2002 21:40:56 -0400
Links: << >>  << T >>  << A >>
Thanks to all of you for your advice and comments.  The $1600 board is a little
overkill for my application, but I need a board that will pass 16 bits at 3.2
MHz.  It is actually a DATEL A/D board with an unpopulated converter.  Having
dealt with a cheaper and very inferior (and unreliable) board earlier in the
project (at ~$200) I was very concerned about poor reliability in the hands of our
customer.  (So why am I going to a custom USB2 interface???   Sometimes I am not
sure that I should.)  In addition the quantities are quite small at this time (5
to 20 units per year?)   However, at $1600 if I can put together a cheap USB2
solution then I can generate a little more profit for a start-up company on a
shoe-string budget.  The dedicated chip has some real possibilities and the
Phillips chip sounds especially interesting.

Thanks,
Theron Hicks

rickman wrote:

> Theron Hicks wrote:
> >
> > Hello,
> >     I am developing an instrument that is currently communicating over a
> > special high speed parallel board.  The data rate is 6.4 million 8 bit words
> > per second.  The board works great but it costs in excess of $1600 US per
> > copy.  It also occupies a full sized PCI slot.  We are considering
> > implementing an alternative I/O arrangement such as USB2 or ethernet
> > (TCP/IP).  Is anyone aware of free-ware USB2 implemented in VHDL or some
> > other FPGA friendly technology?  Note: target FPGA  is a Spartan2E (or if
> > absolutely necessary, Virtex2).
> >
> > Thanks,
> > Theron
>
> I know you asked for an FPGA core, but did you try going back to your
> board supplier and explaining to them the cost problem?  If you are
> using sufficient quantities to justify a design change, I would bet they
> would be willing to come down on the price if they knew they would be
> losing a high volume customer.  I don't know what is on the parallel
> board, but I bet it can be sold for well, well under $1600.  Unless it
> has a large Virtex II part  :)
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design      URL http://www.arius.com
> 4 King Ave                               301-682-7772 Voice
> Frederick, MD 21701-3110                 301-682-7666 FAX


Article: 47673
Subject: Re: Configuration:Startup
From: Cisa <jjyy@hotmail.com>
Date: Tue, 1 Oct 2002 18:50:27 -0700
Links: << >>  << T >>  << A >>
Thanks.
I don't remove the cclk after configuration completes,so it should have enough cclks.
I use a programmer to download my design into EPROM,and use selectMAP
slave mode to configure from EPROM
in PCB board.I have also noticed that after configuration cs signal of the FPGA is low.Is it irrelevant
for FPGA to start?What's wrong with 
my configuration?Help,Pls.

Article: 47674
Subject: Re: C\C++ to VHDL Converter
From: "Brett Cline" <brett@ForteDS.com>
Date: Wed, 02 Oct 2002 02:36:17 GMT
Links: << >>  << T >>  << A >>
Hi All-

   Synthesis from a C/C++ algorithm is absolutely possible and has been in
use for some time. Even "plain vanilla C" algorithms can be used with the
right synthesis product. Obviously it does take some amount of hardware
knowledge to get reasonable hardware out the backend. All that should be
required is to add the hardware interface structure to the C/C++ algorithm.
For that we recommend using SystemC (there is a reference implementation
available under an open source license at www.SystemC.org). SystemC provides
the necessary abstraction in C++ to add concurrency, bit accuracy, and other
hardware-isms to the C/C++ algorithm.

  To take the algorithm to hardware (RTL Verilog or VHDL) my company offers
a product called "Cynthesizer" for high-level synthesis from SystemC. We've
had a number of customers take generic algorithms (some even from the web)
such as filters, encryption, multimedia, etc. and convert them directly to
RTL Verilog and VHDL. The resulting RTL can be put into any FPGA or ASIC
synthesis tool as well as any other tool that operates on RTL.

For more information check out our web site at www.ForteDS.com or feel free
to email me directly.

Best regards,
Brett


"Ray Andraka" <ray@andraka.com> wrote in message
news:3D894809.ECF33E30@andraka.com...
> Not exactly.  There are several vendors that have  C to hardware
compilers,
> but don't expect to take plain vanilla C and compile it directly to
hardware.
> For the most part, these tools use subsets and extensions to C to permit
> description of hardware and all the parallelism that implies in a C-like
> environment.  It raises the level of abstraction, and as a result you tend
to
> get a design that is more bloated and slower than one done closer to the
> hardware.  The point is that there is no free lunch, there is a
considerable
> engineering effort to convert your software to something that will run at
a
> reasonable speed in an FPGA that you can afford to buy.
>
> mike wrote:
>
> > I can't claim to be an expert, but what I think you want to do isn't
> > going to work.  You can't take any arbitrary C/C++ program and convert
it
> > into VHDL code that will run on an FPGA.  For making something like a
> > hardware mp3 player, you may want to look at something like a
> > programmable DSP board.  Also, you should check on what, if any, analog
> > outputs are avilable from the FPGA you're using.  For example, on the
> > Altera student board, the only analog output is for a VGA monitor, so if
> > you wanted to make an mp3 player using one you'd need to build an
> > interface to convert the decoded digital audio into analog audio.
> > Mike
> >
> > On Tue, 17 Sep 2002 09:27:21 +0000, DJohn wrote:
> >
> > > Hi all VHDL experts,
> > >   Is there any tools which can convert a C\C++ source file to VHDL .
For
> > > example If I have a C source code for a MP3 decoder , Can any tool can
> > > convert it into VHDL equivalent. There is some facility in FPGA
> > > Advantage to generate a wrapper VHDL for a  C File , what exactly is
> > > that ? Does that mean I can synthesize a C\C++ file by creating a VHDL
> > > Wrapper. Please help
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759
>
>





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