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"RISC taker" <RISC_taker@alpenjodel.de> schrieb im Newsbeitrag news:18c289aa.0301260539.56a14029@posting.google.com... > Is there a way to extend a RAM by one bit? I thought of building a > structure with slices. What do you think? Can I use the LUTs for this > purpose, combined with a flipflop for synchronous reading? If so, how Sure. > much logic does it take? 1024 bits needed, divided by 128 bits per CLB > equals 8 CLBs, but I don't know how much I have to add for the For single port RAM using LUTs, you get 16 bit/LUT. For dual port RAM, you get 8 bit per LUTs (more preceice, 16 bit per 2 LUTs) > multiplexing. And is it possible at all? Sure. It depends almost only on your speed requirement . -- MfG FalkArticle: 51926
Hi,
I may not be able to come to FPGA 2003.So you can only see the
abstract of my poster in the proceedings.I am a circuit designer.Not like
you, you concerntrate on the design using FPGAs.I am designing a new
family of FPGA using SiGe technology (not CMOS).My boss may present a
paper in the conference.I am the 3rd author of that regular paper.There
are lots of mistakes in that paper.But the idea is there.
Will Peter Alfke, Ray Andraka go to attend the conference?
sincerely
-------------
Kuan Zhou
ECSE department
On Sun, 26 Jan 2003, Nicholas C. Weaver wrote:
> In article <Pine.SOL.3.96.1030125223015.12231A-100000@vcmr-86.server.rpi.edu>,
> Kuan Zhou <zhouk@rpi.edu> wrote:
>
> > I got a poster in ACM FPGA.ISFPGA means International Symposium on
>
> Most call it "FPGA", eg FPGA 2003. Just as IEEE Symposium on
> Field-Programmable Custom Computing Machines is "FCCM".
>
> What's your poster on?
>
> >.... It's the same thing.Where did you get the hardware
> >information?From manuals?
>
> Manuals, intuition, also a couple designs (The best being the AES core
> I built as a benchmark: 1.3 Gb AES core in 10 BlockRAMs and 800
> slices, Spartan II-100-5 speedgrade (A $10 part). It's 1.7 Gb/s in a
> Virtex E. Remove the pipelining and it is still >500 Mbps regardless
> of feedback modes).
>
> I've developed a pretty good intuition for "Brand X" from doing a few
> designs, none at all for "Brand A".
>
> Also reading Ray Andraka's, Peter Alfke's, and other posts here. Ray
> Andraka especially is very informative.
>
> Also, I'm a bit of a luddite and think in terms of LUTs and flip flops
> and schematics. Which actually helps if you want to push the limits
> of the architecture.
>
> The difference between no pipelining and smart pipelining can be 2x or
> even more. You CAN have tools do that automatically (I'm presenting
> mine at FPGA), but the current systems don't really support that.
>
> Hand layout can easily buy another 20-30% or more.
>
> > Why you want to set a fixed frequency for all the applications?I am
> >curious.
>
> Higher throughput. Designs will ALWAYS meet the array's architectural
> throughput if feed-forward or have sufficient task-level parallelism.
> Not to mention pipelined interconnect to enable higher clock
> frequencies.
>
> Easier to integrate as a coprocessor or system-on-a-chip, as there are
> now only one clock to deal with, no design-dependant clock domains.
>
> Faster tools (route & retime a 6000 LUT design in ~1 minute, route and
> retime an AES core in 12 seconds).
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
>
>
Article: 51927
Hi folks,
I have a big problem with a design based on a Spartan2 FPGA.
I want to write data that is coming from a host via a USB-controller into a
SDRAM via input-FIFOS and an SDRAM-controller from Altera.
I have written a state-machine that initializes the SDRAM-controller and
waits for the Send-command from the host.
The input FIFOs are based on a model from Xilinx and use Dual Port Block-Ram
memory.
Is it right that I need 3 clocks after asserting the read-command (pop)
until data can be assigned to the input of the SDRAM-controller?
How can I handle this delay with my state machine.
The problem is that the SDRAM controller acknowledges my Write-request with
a dedicated signal and needs the FIFO-Data then 2 clocks later.
if acknowledge='1' then
read_fifo<='1';
nextstate<=sendstate;
else
nextstate<=currentstate
end if;
I think something like this doesn't work.
Any hints and tips?
Thanks in advance
Jens Niemann
Article: 51928In article <Pine.SOL.3.96.1030126123015.14025A-100000@vcmr-86.server.rpi.edu>, Kuan Zhou <zhouk@rpi.edu> wrote: >Hi, > I may not be able to come to FPGA 2003.So you can only see the >abstract of my poster in the proceedings.I am a circuit designer.Not like >you, you concerntrate on the design using FPGAs.I am designing a new >family of FPGA using SiGe technology (not CMOS).My boss may present a >paper in the conference.I am the 3rd author of that regular paper.There >are lots of mistakes in that paper.But the idea is there. Pipelined lut or pipelined interconnect? A 20 GHz FPGA is pretty darn useless if you can't route it. Do you have the paper online somewhere? > Will Peter Alfke, Ray Andraka go to attend the conference? Ray Andraka is on the program committe, he probably will be there. Peter Alfke has been there in the past, but I don't know. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 51929
Hello everyone... I'm working on a university design project and i'll be using FPGA. I'm new to this and don't really know where is a good place to get started. Our design project is a mine-detecting robot. The robot will cover a rectangular grid, scanning for metals (using an inductive coil sensitive to different metals). The FPGA will take inputs from the coil and other sensors (for position of the coil and the robot in the grid). The FPGA also controls the servo motors using PWM. Once a metal (mine) is detcted, the FPGA will relay the information regarding the coordinate of the mine to a PDA. Any feedback/help will be greatly appriciated. thank you all in advance cheers, HoumanArticle: 51930
You say you don't want to waste half the BlockRAM so you'll but a sidecar on the x9 structure. Okay. But the BlockRAMs are 2048x9, aren't they? 18 kbit blocks. So you're willing to toss 50% of the depth and add several CLBs rather than toss 44% of the width with no additional resources? If your desire is for a 2048x10 structure then sure - you can ad the extra 2048x1 structure with the appropriate external multiplexing and emulation of the other BlockRAM flexibility you decide to use. Are you seriously using all (most?) of your available BlockRAM elements? I'm used to designs with BlockRAMs that sit idle. I'd say use a 1024x18 BlockRAM complete with its dual-port capabilities and other flexible options rather than building the extra bit into the distributed CLB SelectRAM. Enjoy! "RISC taker" <RISC_taker@alpenjodel.de> wrote in message news:18c289aa.0301260539.56a14029@posting.google.com... > Hi! > > I need a 10 bits wide RAM. Unfortunately, Virtex-II RAMs are just 9 > bits wide (or 18, but in this case it's only half as deep, and I waste > much of it). > > Is there a way to extend a RAM by one bit? I thought of building a > structure with slices. What do you think? Can I use the LUTs for this > purpose, combined with a flipflop for synchronous reading? If so, how > much logic does it take? 1024 bits needed, divided by 128 bits per CLB > equals 8 CLBs, but I don't know how much I have to add for the > multiplexing. And is it possible at all? > > Thanks, > DennisArticle: 51931
Be sure to check the functionality you put into your registers. There are some things you can do in the CLB registers that you can't do in the IOB registers. In the earlier Virtex style devices there are issues with a mix of synchronous and asynchronous resets in an IOB, for instance. Try the FPGA editor and see if you can manually add all the signals you want to an IOB cell. If you can hook up all your I/O as you expect and you don't see any conflicts in the logic implementation from the IOB cell point of view, you might have a tough time of it. In my design flow, there are two places where IOB packing can be forced or excluded: first in my synthesis (embedded in the edif file) and second in the PAR configuration. If it you can't find a problem in either place, I can't think of anything further. "Charles Stuart" <cstuart@cfl.rr.com> wrote in message news:EhBY9.129679$Sa3.3282355@twister.tampabay.rr.com... > This is a general question, but directed at a Virtex 2 family device. I'm > using the ISE 5.1i tools and I want to force a self- contained registered > bi-directional IOB port, i know the IOBs are configurable in that manner, > but I can't get the tools to give it to me with either HDL or Schematic > entry attempts ( with the size of the design I cannot consider FPGA editor) > . Yes, I've forced registers to IOB inputs & outputs. How do I make this > happen? > > Thanks for any help > > Charlie > >Article: 51932
What's a "standard 40 pin package?" If you long for the days of yore when prototyping was done with dips and wire wrap, the new FPGAs have evolved past these slow ancestors. The edge rates delivered by the I/O and the sheer dynamic current demands due to the internals are so strong that the idea of a single VCC and ground pair on opposite corners of the chip would make many of todays engineers chuckle at the absurdity. For today's devices we need a significant number of power and ground pins for both the IO and internal requirements. If you can get by with the densities offered, the lower cost series devices such as the Spartan-II and Spartan-IIE may have some quad flat packs that are more liked by those unhappy with BGAs. It's tougher than socketing a 40-pin dip but you can go much faster than 25 MHz, too. If you want the densities and performance, the fine pitch BGAs are worth the manufacturing hassle in this engineer's opinion. Me, I want more pins on the smaller FPGAs. I've been "buying up" in the Spartan-II(E) series just to get the pin count even though I could get by with a 100K or 150k device for my logic needs. FPGA vendors do a decent job of covering a wide spectrum but there will always be those who want something "far out" (compared to the majority of the market). "David" <gretzteam@hotmail.com> wrote in message news:XMzY9.30074$6a3.282424@wagner.videotron.net... > Hi, > Can anyone explain why do fpgas have such a large number of pins? I > understand that for very large design you might need those 150 pins but > there are some applications where you need a lot of gates but only 10 I/O > pins would be more than enough. The chip takes a lot of place on the pcb and > it is a nightmare to do the layout. Why don't we have some mid-large fpgas > in terms of gate, but say in a standard 40 pin package? > > Thanks > > David > >Article: 51933
Houman wrote: > Hello everyone... > I'm working on a university design project and i'll be using FPGA. I'm new > to this and don't really know where is a good place to get started. > > Our design project is a mine-detecting robot. The robot will cover a > rectangular grid, scanning for metals (using an inductive coil sensitive to > different metals). > The FPGA will take inputs from the coil and other sensors (for position of > the coil and the robot in the grid). > The FPGA also controls the servo motors using PWM. > Once a metal (mine) is detcted, the FPGA will relay the information > regarding the coordinate of the mine to a PDA. > > Any feedback/help will be greatly appriciated. You're implementing just the logic functionality into an FPGA that is not to be met with a microprocessor. Yes, you can implement a microprocessor into an FPGA but that requires advanced knowledge in microprocessors and FPGA, so not recommended to start with. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 51934
Petter Gustad <newsmailcomp4@gustad.com> wrote in message news:<87u1fyl8ey.fsf@filestore.home.gustad.com>... > It would be cheaper to use a plain AMD flash or similar. If you can > control the pins of the processor attached to the flash using jtag you > should be able to program your flash using some clever JTAG software. Yeah, that would work, I just think they already have quite a few of the EPC16's laying around since they were anticipating using them, lol. This project has been handed off to me by the way, so I'm working with other people's schematics. > On the other hand, would it be possible to hold the processor in reset > state (or some other state where the bus is tri-state) until > config_done? > The DSP processor has a !RESET and a !SHZ (which holds all the DSP's pins tristated). I was going to tie both of them to pull-down resistors and to the FLEX10ke so that they'd be pulled down until the flex was programmed, at which point the logic could take over and do the necessary timing to raise one and then the other. Unfortunately, that was with the assumption that the flex's IO pins were tristated during configuration, but they have a weak pull-up during configuration, so I don't think it'll work. I've been thinking of just putting an RC circuit on the !SHZ so it was tristated the proper amount of time on power-up, but I'm not too fond of having to rely on the timing of an analog circuit for that purpose.Article: 51935
I prefer Verilog, I think it partly has to do with linguistics. The issue I have is not with the number of characters typed, I find it much easier to read than VHDL. For instance, which is harder to read "downto" or ":" ? Generally I find fewer characters easier to read to a point. What is a "std_logic_vector" ? The concatonation of three different components confuses me. It really is just one idea, so why represent it with three different meaning components ? If it's a standard, then why do I have to type in 20 characters ? Why can't I just type "vec" ? Having a lot of different strictly defined types is not necessarily a good thing. It all depends upon what the goal is. Without strictly defined types, I find it easier to generalize my understanding of code. If there is something that is complex to understand in the code, then I use the following method: I document it with comments. Something I don't understand about VHDL: why would one use different RTL and behavioural code ? If you're testing something, wouldn't you want the code being tested to be the same as the code synthesized ? VHDL peeves: elsif / when / others and others things quotes around numbers round brackets for indexing etc. RobArticle: 51936
Houman, I think you can do that with an FPGA, but first you need to define very well the different functional blocks of your application. Take, for example, the sensor data: how many bits of resolution will the converted signal from the sensor have? you will have to operate on that data, making comparisons, maybe doing arithmetic operations to adjust values, etc. Then, you will have another block wich generates the PWM to drive the servos. And another block will have to implement RAM to save the coordinates (that I imagine will be sensor data previously fetched in) and to implement the communication protocol with the PDA. Every task defined above can be done with a medium sized FPGA, Xilinx or Altera would do well. Good Luck, Mauricio Lange "Houman" <abrishamkar@ieee.org> wrote in message news:<b11ino$cck2@mercury.cc.uottawa.ca>... > Hello everyone... > I'm working on a university design project and i'll be using FPGA. I'm new > to this and don't really know where is a good place to get started. > > Our design project is a mine-detecting robot. The robot will cover a > rectangular grid, scanning for metals (using an inductive coil sensitive to > different metals). > The FPGA will take inputs from the coil and other sensors (for position of > the coil and the robot in the grid). > The FPGA also controls the servo motors using PWM. > Once a metal (mine) is detcted, the FPGA will relay the information > regarding the coordinate of the mine to a PDA. > > Any feedback/help will be greatly appriciated. > > thank you all in advance > cheers, > HoumanArticle: 51937
Hi,
Following is a Handel-C program which reads a 128-bit data,
substitutes all the 4 bytes with memory lookup and, finally,
the buffer contents are given to the output pins.
The data input/output interface is 32-bit unidirectional.
After implementing the given design on a Xilinx Spartan-II,
Part XC2S200-FG256, I'm getting a clock speed of 57.531MHz.
How can a better clock speed can be achieved?
Is it possible here to use two dual-port BlockRAMs instead of
4 single-port BlockRAMs for 4 parallel memory lookups?
Any assistance appreciated.
Regards,
Saurabh Pal
---------------------------------------------------------------------------
set clock = external;
interface bus_clock_in (unsigned int 32) DIN();
unsigned int 32 bus_out;
interface bus_out () DOUT(unsigned int 32 out = bus_out);
ram unsigned 8 MyRamA[256] with {block = 1};
ram unsigned 8 MyRamB[256] with {block = 2};
ram unsigned 8 MyRamC[256] with {block = 3};
ram unsigned 8 MyRamD[256] with {block = 4};
void main()
{
unsigned 8 data_in[4], data_out[4];
while(1)
{
par {
data_in[0] = DIN.in[31:24];
data_in[0] = DIN.in[23:16];
data_in[0] = DIN.in[15:8];
data_in[0] = DIN.in[7:0];
}
par {
data_out[0] = MyRamA[(data_in[0])];
data_out[1] = MyRamB[(data_in[1])];
data_out[2] = MyRamC[(data_in[2])];
data_out[3] = MyRamD[(data_in[3])];
}
par{
bus_out = data_out[0] @ data_out[1] @ data_out[2] @ data_out[3];
}
}
}
Article: 51938Hi, thanks for the tips! "John_H": <johnhandwork@mail.com> wrote: > So you're willing to toss 50% of the depth and add several > CLBs rather than toss 44% of the width with no additional resources? No! Sorry, I might have explained this wrong. I don't want to waste ANY % of the block RAM. In fact I am dividing the block into two separate RAMs. One port accesses the first half of the depth, the other port independently works on the second half. Now I thought about extending the structure with LUTs by one bit. Single port distributed RAM will do (half-depth twice), as the ports don't address any shared memory, but only their own half. I will try to see if and how it works. > Are you seriously using all (most?) of your available BlockRAM elements? > I'm used to designs with BlockRAMs that sit idle. I'm making a design with several parallel processing elements (PEs). Each PE uses 2 multipliers and 2 block RAMs (so far). They use up more RAM than logic. I consider a XC2V250, so I could fit 10 PEs into it (20 RAMs). The remaining 4 RAMs are needed for a central unit that schedules the work to the PEs. If I throw in a 3rd block RAM, I can only fit 6 PEs (instead of 10). There is still a lot to develop. Right now I have unused LUTs. If I see later that I need much more logic, I still have this option. Thank you! DennisArticle: 51939
Hi, as has been said before, your task seems to be more focused on algorithms, less on logic. You should really consider using a microprocessor / microcontroller in the design. The great thing about FPGA is that you can fit the processor into the same chip with all the rest. Take a look at the PicoBlaze by Ken Chapman. That's a small 8-bit processor that fits in any Xilinx device and takes up a minimum of resources. If you have ever programmed in assembly language, that'll be easy for you. Gray Research has other processors that will also run on non-Xilinx devices. DennisArticle: 51940
"Vladimir" <olsim@online.ru> writes: > Can anyone send me IEEE std 1149.1? You can order it at standards.ieee.org. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 51941
"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> writes: > ... and if you're of > a certain age and you want proof positive of this theory, > just look at TECO and APL. (No, I didn't make them up!) For those who really want to know, excerpt from the Jargon File enry for TECO (http://catb.org/~esr/jargon/html/entry/TECO.html) ---- begin quote ---- As an example of TECO's obscurity, here is a TECO program that takes a list of names such as: Loser, J. Random Quux, The Great Dick, Moby sorts them alphabetically according to surname, and then puts the surname last, removing the comma, to produce the following: Moby Dick J. Random Loser The Great Quux The program is [1 J^P$L$$ J <.-Z; .,(S,$ -D .)FX1 @F^B $K :L I $ G1 L>$$ ---- end quote ---- Cheers, MartinArticle: 51942
Dave wrote: > Hi, > Does anyone know the quality of those tools thant translate a > Matlab/simulink model into vhdl, ready to be programmed in a > targetted fpga. I'm mostly talking about DSPbuilder(Altera) and > SystemGenerator(Xilinx). A couple of years ago, tools like that > were doing a horrible job. How are they now? > Thanks > Dave Hi Dave, sorry for the delayed answer.... I'm currently working with SystemGenerator (on Xilinx' Spartan2). I started with it 18 months ago, and in the very beginning, it was really a horror. Everything started with long lasting installation sessions - it took me more than two weeks until everything worked together. After that, a lot of library models were buggy and couldn't be used. I dropped that project, then, and implemented it manually in VHDL. Meanwhile somebody from Xilinx had contacted me, and he was very successful to convince me that I should give these tools another try. In October last year, I upgraded to the newest version. Installation was still a tough job, and we had to add some scripts which would accomplish the post-processing. Since then, I've been working with SystemGenerator in a project and it does a perfect job: 1. There's nothing to be done manually "between" Simulink and loading the FPGA except pressing "Generate" in Simulink and "Rerun all" in the Xilinx Project Navigator. 2. As soon as the Simulink project's simulation runs, the generated VHDL code is synthesizable; for me this means that I save a lot of time. 3. I enjoy the fact that a simulink model needs almost no additional documentation; and even someone who's not familiar with VHDL or with FPGAs should be able to do slight modifications on a project. 4. I do all simulations within Simulink which seems to me to be more comprehensive or at least intuitive than ModelSim. Need to say that my project is not using most of the ressources of the FPGA and is not too critical in timing. There might be some limitations for critical and/or big projects, because the two-phase optimization might be slightly suboptimal, but for me it's perfect. But: don't expect that the tool would teach you VHDL, or that you would receive readable VHDL code. Instead, it's made of a huge amount of files full of templates, which are autogenerated and keep changing across modifications. Sometimes, it's difficult to find a reason, why Simulink refuses to simulate a project with Xilinx model parts. Xilinx should improve their error feedback messages (I guess, they work on it, but sometimes you need some "enlightenment"). XST produces a lot of warnings during the generator process. Maybe they are important in some special situations: for my part, I've learned just to launch the process, close my eyes, rely on it, and afterwards use the produced file, and it works. If you merely cannot ignore the warnings, there might be a lot of work until they vanish - I don't know. Hope this gives you some impressions, and encourages you. Bernhard -- before sending to the above email-address: replace deadspam.com by foerstergroup.deArticle: 51943
"geeko" <jibin@ushustech.com> wrote in message news:b0qkcq$s39r7$1@ID-159027.news.dfncis.de... > Hi all > I have a problem with developing a AES core with AMBA AHB interface > for programming and data access.I am new to AMBA and AHB.Anybody familiar > with the implementation of AMBA AHB compliant cores.Any documentation > available The AMBA spec can be obtained from the ARM website: http://www.arm.com/.Article: 51944
Hi! Is it possible to convert the old schematics sources (made with XILINX XactStep 1.5i) into any format which can read Mentor HDL-Designer (graphics and/or VHDL)? I thank you all for your tipps! RobertArticle: 51945
hello sirs/friends i am writing vhdl code for PCI bridge to be specific i am trying to implement PLX 9050 bridge. I have understood the protocol. But i donot know the internal design details of that chip. i am total lost. please help me . if you have done any project of this kind please send the design details of it. u can mail it my email id. how to start????.module level?????how??? waiting for ur reply thanks in advance praveenArticle: 51946
Folks, Is there a way to generate the Xilinx Map report as XML? Apologies if this qualifies as something I could have gotten via RTFM. I've been browsing and it looks to be non obvious... Regards, RichardArticle: 51947
Could somebody help me in this matter? I have sources for xilinx made on very old WebPack 2.1 and I need to convert schematics files to version 4.2 or 5.1. Is there any possibility to do this??? Please help. Thanks in advance.Article: 51948
Hi All,
Here demonstrative unit that show incorrect synthesis results in XST.
Post P&R simulation gives incorrect result (output signals DATA(1 to
7) was set in '0' !?)
Synthesis of same unit in FPGA Express show correct results.
It seems that XST incorrect synthesizes arrays of integers.
Best regards, Vladislav Vasilenko.
Test program:
------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity table is
Port (
CLK : in std_logic;
RST : in std_logic;
ADDR : in std_logic_vector(3 downto 0);
DATA : out std_logic_vector(7 downto 0));
end table;
architecture rtl of table is
type t8 is array(0 to 15) of integer;
constant F1 : t8:= (0, 213, 184, 165, 150, 138, 126, 116, 106, 97, 87,
78, 68, 58, 46, 32);
begin
DATA <=CONV_STD_LOGIC_VECTOR( F1(conv_integer(ADDR)),8);
end rtl;
Article: 51949Yes. Modular design is enabled. We have licenses about several Xilinx tools. When I run NGDBUILD, PAR, MAP tools, before running them, I execute a script that enable the Modular Design. Errors about XAPP290 design seem to be implementation errors. (Examples without review). Did you already use Modular Design for Partial Reconfiguration with XAPP290 example? Regards Eduardo
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