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Messages from 52275

Article: 52275
Subject: Re: Clock Enables
From: "Brian Guralnick" <innerdimension@videotron.ca>
Date: Wed, 5 Feb 2003 15:53:14 -0500
Links: << >>  << T >>  << A >>
Looking at my calculator, I thought that 'CE' stands for Clear Everything...


--

____________
Brian Guralnick
innerdimension@hotmail.com



"Jonathan Bromley" <jonathan@oxfordbromley.u-net.com> wrote in message news:b1qjsu$d0o$1$8302bc10@news.demon.co.uk...
> "Jan De Ceuster" <Jan.DeCeuster@elis.rug.ac.be> wrote
> > Gee, I always thought CE stands for Chip Enable...
>
> Nah, you're all wrong.  It's the little logo they stick
> on toys to show that they are [allegedly] compliant with
> all the European consumer-protection legislation.  Never
> let a sensible bit of technical usage get in the way
> of legislative fervour, that's what I say.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services
>
> Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
> Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
> Fax: +44 (0)1425 471573                           Web: http://www.doulos.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.
>
>



Article: 52276
Subject: Java NullPointerException in Xilinx System Generator 2.2
From: Wojciech Zabolotny <wzab@ise.pw.edu.pl>
Date: Wed, 5 Feb 2003 22:09:09 +0100
Links: << >>  << T >>  << A >>
When I compile a relatively big project with System Generator 2.2 I get
"fatal error" and sysgen.log contains:

Running s2x
Running hw expander
java.lang.NullPointerException
        at com.xilinx.sysgen.c.f.a(Unknown Source)
        at com.xilinx.sysgen.c.f.a(Unknown Source)
        at com.xilinx.sysgen.c.l.case(Unknown Source)
        at com.xilinx.sysgen.comp.a.a(Unknown Source)
        at com.xilinx.sysgen.comp.a.a(Unknown Source)
        at com.xilinx.sysgen.comp.GuiMain.run2(Unknown Source)
        at com.xilinx.sysgen.comp.GuiMain.main(Unknown Source)

error in Hardware expander

How to solve it? Is there any workaround?

				TIA & Best regards,
				Wojciech Zabolotny
				wzab@ise.pw.edu.pl



Article: 52277
Subject: Re: Switching synthesis tools
From: Ray Andraka <ray@andraka.com>
Date: Wed, 05 Feb 2003 21:20:26 GMT
Links: << >>  << T >>  << A >>
Synplify does a much  better job at mapping RTL to the special features of
the FPGA.  Xilinx's XST does well in that regard too, but it is restricted
to Xilinx only.

Nicholas Girde wrote:

> Hi,
>
> I've been using Synopsys' FPGA Compiler2 for about a year now (and
> their FPGA Express that came with Xilinx Foundation before that) I
> know lot of people complain that its slower, supports lesser vhdl
> cosntructs etc., but its worked fine for me so far. Could you guys let
> me know if there is any other reason why I should trying the other
> tools out there? (Btw, I work on VIRTEX2 currently and am thinking of
> using STRATIX some time soon.)
>
> Any advice, welcome!
>
> - Nick

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759



Article: 52278
Subject: Re: Java NullPointerException in Xilinx System Generator 2.2 & 2.3
From: Wojciech Zabolotny <wzab@ise.pw.edu.pl>
Date: Wed, 5 Feb 2003 22:46:52 +0100
Links: << >>  << T >>  << A >>
Sorry for replying my own posts, but I have a few new details.
I've tried the 2.3 version, and results are pretty the same.
The only difference is that sysgen.log is a little more informative.
The additional line is:
internal error: found more than one driver in port list

The whole sysgen.log contents is as follows:


Running s2x
Running hw expander
internal error: found more than one driver in port list
java.lang.Exception
        at com.xilinx.sysgen.e.g.do(Unknown Source)
        at com.xilinx.sysgen.e.m.a(Unknown Source)
        at com.xilinx.sysgen.g.j.if(Unknown Source)
        at com.xilinx.sysgen.g.j.a(Unknown Source)
        at com.xilinx.sysgen.c.f.a(Unknown Source)
        at com.xilinx.sysgen.c.f.a(Unknown Source)
        at com.xilinx.sysgen.c.l.try(Unknown Source)
        at com.xilinx.sysgen.comp.a.a(Unknown Source)
        at com.xilinx.sysgen.comp.a.a(Unknown Source)
        at com.xilinx.sysgen.comp.GuiMain.run2(Unknown Source)
        at com.xilinx.sysgen.comp.GuiMain.main(Unknown Source)

error in Hardware expander

 				TIA & Best regards,
 				Wojciech Zabolotny
 				wzab@ise.pw.edu.pl
  



Article: 52279
Subject: Re: Clock Enables
From: vishker@yahoo.com (Vishker)
Date: 5 Feb 2003 14:13:56 -0800
Links: << >>  << T >>  << A >>
I agree with Jussi. I know that CE it controls the data input but then
why is called Clock Enable ? It should be called Data Enable as it is
more close what it does.
When you say Clock Enable, it basically means a signal controlling the
clock. Its  like Clock is turned ON or OFF with CE and the closest
circut I could think of would be like, a clock signal going through a
tri-state gate whose enable is controlled by CE (clock enable). But we
call it as Gated Clock citcuitry.

How can you say a signal that controls or enables the clock, by its
very definition, be Synchronous with the same Clock ? Don't you think
its funny !!!

-Vs




Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b1qegk$l3j$1@news.cc.tut.fi>...
> In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote:
> I've always wondered why they call it CE (clock enable) when in fact its 
> DE (data enable). In the wonderful world of ASICs gated clocks are 
> often preferred, when power consumption is of concern. In these flip-flops 
> clock signals are anded with CE. The hard task is controlling the CE 
> signals...
> 
> regards,
> juza 
> 
> 
> : CE controls a mux that makes the D input either look at the Q output ( clock
> : disabled) or look at the incoming signal ( clock enabled). CE is, therefore,
> : a synchronous signal.
>  
> : Peter Alfke
> : ==========================
> : Vishker wrote:
>  
> :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> :> Pl. justify the answers.
> :>
> :> Thanks
> :>
> :> Vs

Article: 52280
Subject: Re: Targeting the VirtexII version of Picoblaze at a SpartanII....
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Wed, 5 Feb 2003 22:16:03 -0000
Links: << >>  << T >>  << A >>
> Thanks,
>     It looks very interesting.  I notice that the page also lists a USB
> interface module.  What can you tell me about this?  Is it USB or USB2?  I
am
> interested in a possible USB2 I/O for a project.

Theron,

It's based round a FTDI FT245BM device which according to the data sheet
is 'USB 1.1 and 2.0 compatible' , but it claims a max transfer rate of
1M byte/sec so I presume it's actually only USB 1.0.

This was designed to allow quick register access to designs being
debugged on a BurchED board.

There are a few PCBs left so I can make up a few more if anyone's
interested.

Nial.


------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital



Article: 52281
Subject: Re: Clock Enables
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 05 Feb 2003 14:47:40 -0800
Links: << >>  << T >>  << A >>
CE as Clock Enable describes a high-level functionality, it does not describe the detailed mechanism.
Well, it describes it wrongly.

I don't want to dissect every convention.
Why is a RAM called a RAM?  Usually a ROM has random access also... etc.

Peter Alfke
==========
Vishker wrote:

> I agree with Jussi. I know that CE it controls the data input but then
> why is called Clock Enable ? It should be called Data Enable as it is
> more close what it does.
> When you say Clock Enable, it basically means a signal controlling the
> clock. Its  like Clock is turned ON or OFF with CE and the closest
> circut I could think of would be like, a clock signal going through a
> tri-state gate whose enable is controlled by CE (clock enable). But we
> call it as Gated Clock citcuitry.
>
> How can you say a signal that controls or enables the clock, by its
> very definition, be Synchronous with the same Clock ? Don't you think
> its funny !!!
>
> -Vs
>
> Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b1qegk$l3j$1@news.cc.tut.fi>...
> > In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote:
> > I've always wondered why they call it CE (clock enable) when in fact its
> > DE (data enable). In the wonderful world of ASICs gated clocks are
> > often preferred, when power consumption is of concern. In these flip-flops
> > clock signals are anded with CE. The hard task is controlling the CE
> > signals...
> >
> > regards,
> > juza
> >
> >
> > : CE controls a mux that makes the D input either look at the Q output ( clock
> > : disabled) or look at the incoming signal ( clock enabled). CE is, therefore,
> > : a synchronous signal.
> >
> > : Peter Alfke
> > : ==========================
> > : Vishker wrote:
> >
> > :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> > :> Pl. justify the answers.
> > :>
> > :> Thanks
> > :>
> > :> Vs


Article: 52282
Subject: Re: Xilinx Foundation 5.1: reasons to upgrade
From: Andras Tantos <andras_tantos@yahoo.com>
Date: Wed, 05 Feb 2003 15:30:24 -0800
Links: << >>  << T >>  << A >>
On Wed, 5 Feb 2003 17:27:44 +0200, "Alphaboran"
<alphaboran@yahoo-no-spam.com> wrote:

>Hello all,
>
>I just received the new version of the Xilinx Foundation tool. I now use the
>4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express
>3.6.1. My target devices are Virtex-EM.
>
>Are there any good reasons to upgrade my system? Does the new tool offer
>something really new and useful?
>
>I heard that with the new version you can keep the place AND routing of an
>implemented design and use it on later on altered design. If that's true it
>seems very nice because with the 4.1 version even I make minor changes the
>only thing I can do is to keep the placement and not the routing. Is this
>the case or a rumor?
>
>Thanks in advance for your help.
>
>Best Regards,
>Harris
>
>

I had some problems with going from 5.0 to 5.1. Xilinx apparently
changed something in their VHDL compiler (?) that made my tested and
working design completely useless. It compiled but my registers turned
out to be constants and were optimized out :-O completely. Admittedly
I've used quite some generics and done some funky business with loops
and generates to get the circuit I've wanted but it worked and now it
doesn't. I had to redesign and even now I have timing problems. I
assume going from 4.1 to 5.1 the changes would be even greater.

Andras Tantos

Article: 52283
Subject: Re: xilinx virtex II floorplanning
From: d@vcom.com (douglas fast)
Date: 5 Feb 2003 15:39:33 -0800
Links: << >>  << T >>  << A >>
Thanks for the input.  Now if I could just get my design to meet timing ... :)

Doug

Ray Andraka <ray@andraka.com> wrote in message news:<3E405986.F1383758@andraka.com>...
> The difference in left to right or right to left in 4000 series was negligable.
> Basically within a few tens of ps difference as I recall.  We ran our data paths
> in both directions in 4K with no noticable difference.  Depended much more which
> side the pins were on relative to your logic.
> 
> ac wrote:
> 
> > I have asked this same questions to FAEs and they used to recomend left to
> > right
> > for data flow on the 4000s series since you didn't want the output of a flip
> > flop to have to route
> > "back". For Virtex they say that the improved routing resources make this a
> > non-factor
> > as usual you want to make sure that any adders, counters, etc make use of
> > the carry chain
> > which is vertically oriented.
> >
> > "douglas fast" <d@vcom.com> wrote in message
> > news:981fe2ba.0302041214.42e759e6@posting.google.com...
> > > Hello,
> > >
> > > I am in the process of floorplanning an FPGA design which contains an
> > > adder tree.  The Xilinx documentation mention that datapaths should
> > > flow horizontally in order to make the best use of routing resources.
> > > Is there also a preference for left to right flow vs right to left?
> > >
> > > Thanks,
> > >
> > > Doug
> 
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930     Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
> 
>  "They that give up essential liberty to obtain a little
>   temporary safety deserve neither liberty nor safety."
>                                           -Benjamin Franklin, 1759

Article: 52284
Subject: Re: top colleges in VLSI Design education
From: khusid@andrew.cmu.edu (Max Khusid)
Date: 5 Feb 2003 16:10:41 -0800
Links: << >>  << T >>  << A >>
azim_premjii@yahoo.com (azim premji) wrote in message news:<9afc0e91.0302012135.f622c@posting.google.com>...
> plz give me details of top colleges in VLSI Designing and the criteria
> to get admission ( even  for overseas student) . also necessary sites


MIT,
Carnegie Mellon,
Stanford,
Berkley,
UIUC (Urbana Champaign),
etc

see www.usnews.com under computer engineering

Article: 52285
Subject: Redhat versions
From: "Jerry" <nospam@nowhere.com>
Date: Wed, 5 Feb 2003 21:24:31 -0500
Links: << >>  << T >>  << A >>
Got a question or two. I noticed that RedHat is selling version 8.0. The CAD
tools,  simulators, P&R, synthesis, etc, all
spec RedHat 7.1 or 7.2 as supported. Is anyone running either Xilinx ISE or
Altera Quartus under RedHat 8.0? If you
are could you share your experience? I ask cause I'm about to upgrade at
work to Linux and want that to go as smooth as
possible. If I need to get a copy of 7.1 or 7.2 I will, but prefer to stick
with the latest release.

Thanks
Jerry




Article: 52286
Subject: Re: Xilinx Foundation 5.1: reasons to upgrade
From: "Neeraj Varma" <neeraj@cg-coreel.com>
Date: Thu, 6 Feb 2003 08:25:22 +0530
Links: << >>  << T >>  << A >>
You should keep a copy of the 4.2i+SP3 along with your FPGA Express license
running, in order to keep supporting the older XC4K, Spartan/XL if you still
design with those. XST never supported these devices and ISE 5 stopped
supporting these devices from P&R standpoint.

However, now since Synopsys FPGA express is history, going forward if there
would be any improvements it would be in XST and ISE 5, so earlier the move,
better.

"Andras Tantos" <andras_tantos@yahoo.com> wrote in message
news:6c734vkj5uimt4gnhirf2akqeepsbfpfhe@4ax.com...
> On Wed, 5 Feb 2003 17:27:44 +0200, "Alphaboran"
> <alphaboran@yahoo-no-spam.com> wrote:
>
> >Hello all,
> >
> >I just received the new version of the Xilinx Foundation tool. I now use
the
> >4.1 sp3 for my implementations, in the synthesis phase I use FPGA Express
> >3.6.1. My target devices are Virtex-EM.
> >
> >Are there any good reasons to upgrade my system? Does the new tool offer
> >something really new and useful?
> >
> >I heard that with the new version you can keep the place AND routing of
an
> >implemented design and use it on later on altered design. If that's true
it
> >seems very nice because with the 4.1 version even I make minor changes
the
> >only thing I can do is to keep the placement and not the routing. Is this
> >the case or a rumor?
> >
> >Thanks in advance for your help.
> >
> >Best Regards,
> >Harris
> >
> >
>
> I had some problems with going from 5.0 to 5.1. Xilinx apparently
> changed something in their VHDL compiler (?) that made my tested and
> working design completely useless. It compiled but my registers turned
> out to be constants and were optimized out :-O completely. Admittedly
> I've used quite some generics and done some funky business with loops
> and generates to get the circuit I've wanted but it worked and now it
> doesn't. I had to redesign and even now I have timing problems. I
> assume going from 4.1 to 5.1 the changes would be even greater.
>
> Andras Tantos



Article: 52287
Subject: xsvf, CoolrunnerII and XAPP058
From: "Michael" <chinook@TRASHpacific.net.sg>
Date: Thu, 6 Feb 2003 13:52:40 +0800
Links: << >>  << T >>  << A >>
Dear all

I've been having trouble with Coolrunner II ISP programming (XAPP058). Can
anybody confirm successful implementation? What version of development tools
do you use?  I tested WebPack 5 and ISE 4.2 Service Pack 3. Can't even erase
the bugger. Everything is perfect with Spartan II.

Thanks.
Michael.



Article: 52288
Subject: Re: Clock Enables
From: vishker@yahoo.com (Vishker)
Date: 5 Feb 2003 22:25:40 -0800
Links: << >>  << T >>  << A >>
I don't agree with your RAM and ROM example. ROM no doubt is random
accessable but is also Read Only Memory therefore ROM still holds
good. Unlike Clock Enable where it has nothing to do with Clock at
all.

Or may be some non-native english speaking guy might have coined the
term Clock Enable and the Intelligent English Speaking men might have
followed it blindly.


Peter Alfke <peter@xilinx.com> wrote in message news:<3E41948C.2188A3FA@xilinx.com>...
> CE as Clock Enable describes a high-level functionality, it does not describe the detailed mechanism.
> Well, it describes it wrongly.
> 
> I don't want to dissect every convention.
> Why is a RAM called a RAM?  Usually a ROM has random access also... etc.
> 
> Peter Alfke
> ==========
> Vishker wrote:
> 
> > I agree with Jussi. I know that CE it controls the data input but then
> > why is called Clock Enable ? It should be called Data Enable as it is
> > more close what it does.
> > When you say Clock Enable, it basically means a signal controlling the
> > clock. Its  like Clock is turned ON or OFF with CE and the closest
> > circut I could think of would be like, a clock signal going through a
> > tri-state gate whose enable is controlled by CE (clock enable). But we
> > call it as Gated Clock citcuitry.
> >
> > How can you say a signal that controls or enables the clock, by its
> > very definition, be Synchronous with the same Clock ? Don't you think
> > its funny !!!
> >
> > -Vs
> >
> > Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b1qegk$l3j$1@news.cc.tut.fi>...
> > > In comp.lang.vhdl Peter Alfke <peter@xilinx.com> wrote:
> > > I've always wondered why they call it CE (clock enable) when in fact its
> > > DE (data enable). In the wonderful world of ASICs gated clocks are
> > > often preferred, when power consumption is of concern. In these flip-flops
> > > clock signals are anded with CE. The hard task is controlling the CE
> > > signals...
> > >
> > > regards,
> > > juza
> > >
> > >
> > > : CE controls a mux that makes the D input either look at the Q output ( clock
> > > : disabled) or look at the incoming signal ( clock enabled). CE is, therefore,
> > > : a synchronous signal.
>  
> > > : Peter Alfke
> > > : ==========================
> > > : Vishker wrote:
>  
> > > :> Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ???
> > > :> Pl. justify the answers.
> > > :>
> > > :> Thanks
> > > :>
> > > :> Vs

Article: 52289
Subject: Re: JTAG from CAN
From: Martin Thompson <martin.j.thompson@trw.com>
Date: 06 Feb 2003 08:26:52 +0000
Links: << >>  << T >>  << A >>
Tom <T.Otermans_REMOVE_THIS@home.nl> writes:

> Hello,
> 
> I'm currently working on a project that includes updating a node that
> has an altera 10K30 (fpga with configuration eeprom) and a TI 2407 dsp
> onboard (model with bootloader).  The preferred way is to update this
> node via the to the dsp connected CAN bus (both the fpga and dsp must
> be updated).
> 

Sounds like a good plan.

> Has anyone any experience with doing updates (new flash data in the
> dsp and new data in the configuration eeprom) via the CAN bus? if so
> could you give me some tips on tackling this problem.
> 

We've done it - do you have specific problems?

> I'm thinking of writing a new bootloader that initialises the CAN bus
> and flashes the dsp and fpga. 

Sounds like the right approach for the DSP - although you may find
that youy can't execute code from flash while writing to it, so you
may have to do a funky optimised bootloader to run from internal RAM
while you do it.  Or the device may have multiple flash blocks that
can be prorgammed while code is running from another one.

> Currently the dsp and fpga(configuration
> eeprom) are updated via JTAG. An other option for me is to develop (or
> buy) some extra hardware that can do a CAN to JTAG conversion.
> 

Can you connect some of the DSP I/Os to the config EEPROM?  Then use
the DSP to do the JTAG manipulations?  Otherwise, you may have
problems doing it directly from the CAN bus without extra hardware.
I'm afraid I don't know of anything that would do the job directly.

Does any of that help?

Cheers,
Martin

-- 
martin.j.thompson@trw.com
TRW Conekt, Solihull, UK
http://www.trw.com/conekt



Article: 52290
Subject: Re: Clock Enables
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Thu, 6 Feb 2003 08:56:01 -0000
Links: << >>  << T >>  << A >>
"Bob Perlman" <bobsrefusebin@hotmail.com> wrote
> Why stop at asking for help with homework problems?  I can imagine the
> series of posts we'll see in years to come.
[snip a classic post]

ROTFL, I'll be back when I've cleared the coffee spills off the desk.

That one is going in the archives.  Thanks, Bob.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 52291
Subject: Re: Clock Enables
From: Philip Freidin <philip@fliptronics.com>
Date: Thu, 06 Feb 2003 09:03:04 GMT
Links: << >>  << T >>  << A >>
Thanks Bob,

This easily gets my "Best Posting Of The Year" award.

Philip



On Wed, 05 Feb 2003 19:30:58 GMT, Bob Perlman <bobsrefusebin@hotmail.com> wrote:
>On 4 Feb 2003 15:50:15 -0800, vishker@yahoo.com (Vishker) wrote:
>>Is Clock Enable (CE) of Flip-Flop, Synchronous or Asynchronous signal ??? 
>>Pl. justify the answers.
>>Thanks
>
>Why stop at asking for help with homework problems?  I can imagine the
>series of posts we'll see in years to come.
>
>   ...
>   ...  several postings fetched from the news.future.com news server
>   ...
>
>Bob Perlman
>Cambrian Design Works




Philip Freidin
Fliptronics

Article: 52292
Subject: Re: Switching synthesis tools
From: "Jonathan Bromley" <jonathan@oxfordbromley.u-net.com>
Date: Thu, 6 Feb 2003 09:09:35 -0000
Links: << >>  << T >>  << A >>
"Ray Andraka" <ray@andraka.com> wrote:
> Synplify does a much  better job at mapping RTL to the special features of
> the FPGA.  Xilinx's XST does well in that regard too, but it is restricted
> to Xilinx only.

I don't in any way disagree, but to try to keep the discussion
balanced it might be worth mentioning my experience that Leonardo
Spectrum seems to have the widest understanding of VHDL language
constructs of any synthesis tool.  Not necessarily the best quality
of results, though - that's a "your mileage may vary" issue that
you will need to evaluate case-by-case.

Also, don't try to evaluate these tools just by throwing one
standard piece of "benchmark" code at them to see which gives
the densest/fastest/prettiest result.  Each of the major tools
has specific HDL coding styles that it doesn't like and won't
optimise effectively;  details differ for each tool.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.



Article: 52293
Subject: Re: SOLVED! - Bug in Xilinx SysGen (Was: Java NullPointerException
From: Wojciech Zabolotny <wzab@ise.pw.edu.pl>
Date: Thu, 6 Feb 2003 10:25:15 +0100
Links: << >>  << T >>  << A >>
I've found the reason of the error reported. The system generator has
silently truncated the port labels causing two different ports to be
considered as a single one (the design was really big and multilevel).
I've shortened the subsystem name to two letters, and the synthesis has
succeeded.

I'd suggest, that in this case System Generator should
1) Emit a warning message that the labels have been truncated
2) Emit the INFORMATIVE error message if this leads to erroneously
   interpretation of two ports as one (the Java NullPointerException
   as in SysGen 2.2 is really not very informative, the additional info
   given by 2.3 is only A LITTLE better, because there is no information
   about the port & drivers' names)
3) The best solution would be to generate other UNIQUE names and provide
   the warning about replaced names in the log file.

It seems that for now the only solution is to limit the level of hierachy
and keep the component names short.

 
  				TIA & Best regards,
  				Wojciech Zabolotny
  				wzab@ise.pw.edu.pl
 


Article: 52294
Subject: Re: Redhat versions
From: "Alan Fitch" <alan.fitch@doulos.com>
Date: Thu, 6 Feb 2003 09:38:44 -0000
Links: << >>  << T >>  << A >>
"Jerry" <nospam@nowhere.com> wrote in message
news:v43i0qom6e7309@corp.supernews.com...
> Got a question or two. I noticed that RedHat is selling version
8.0. The CAD
> tools,  simulators, P&R, synthesis, etc, all
> spec RedHat 7.1 or 7.2 as supported. Is anyone running either
Xilinx ISE or
> Altera Quartus under RedHat 8.0? If you
> are could you share your experience? I ask cause I'm about to
upgrade at
> work to Linux and want that to go as smooth as
> possible. If I need to get a copy of 7.1 or 7.2 I will, but
prefer to stick
> with the latest release.
>
> Thanks
> Jerry
>
>
>

We've recently upgraded from 6.2 to 7.3, for the reason
you specified (i.e. tools such as Synplify 7.2 and
Quartus actually require a 2.4 series kernel).

I guess that RH 8.0 should be OK. The only thing I'd worry
about is if you have a tool that requires gcc. RH 8 comes
with gcc 3.2 (I believe) which can be an interesting
experience if you're using something like SystemC or
Testbuilder.

But most EDA tools seem to be primarily interested in the
kernel version, and that's basically still a 2.4 kernel.

The other thing that caught us out was that RH 7.3 has
a dud version of NFS in it by default - you have to upgrade
the kernel to get NFS working reliably. Hopefully that's *not*
a problem with RH 8!


regards

Alan

--
Alan Fitch
HDL Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project
Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire,
BH24 1AW, UK
Tel: +44 (0)1425 471223                          mail:
alan.fitch@doulos.com
Fax: +44 (0)1425 471573                           Web:
http://www.doulos.com

The contents of this message may contain personal views which are
not the
views of Doulos Ltd., unless specifically stated.



Article: 52295
Subject: Re: Clock Enables
From: yves.tchapda@phyworks-ic.com (Yves Tchapda)
Date: 6 Feb 2003 01:57:10 -0800
Links: << >>  << T >>  << A >>
Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3E41419E.ADE8C2CF@egr.msu.edu>...
> Peter,
>     You forgot those who sleep through class, either at home or in the
> classroom, as well as those who do not speak the same language as the
> instructor.  This is intended to reference both students and instructors who (in
> the case of the USA) are non-native speakers of English.  This is not intendend
> as a slam to those who do adequately learn the language of the country where the
> instruction is being given.  It is merely a comment on the sad state of affairs
> where instructors and/or students need not and do not learn the language
> sufficiently to be able to communicate technical concepts.  In fact, in some
> cases, the instructor cannot communicate technical data because they themselves
> are technically incompetent.  However, I suspect that the problem you are
> discussing here is one of laziness.  Unfortunately, these people will graduate
> and be hired by unsuspecting companies.  Due to a fear of lawsuits, these same
> people will be passed along to unsuspecting employer after unsuspecting
> employer.
> 
> Enough of the rant...
> 
> Thanks,
> Theron Hicks
> 


Theron,
This is hardly the forum to place your grievance, which goes far
beyond what this newsgroup is intended for, and is very unwarranted.
Let's concentrate on technical issues, and could we please be humble
enough and have patience for those with less knowledge?

"I know one thing: I know nothing"

Dr Yves Tchapda

Article: 52296
Subject: Re: difference between pci2.1 and pci2.2
From: praveenkumar1979@rediffmail.com (praveen)
Date: 6 Feb 2003 01:59:38 -0800
Links: << >>  << T >>  << A >>
Hello sirs/Friends
please tell me the difference.What new thing is added in PCI2.2 when
compared to PCI2.1.I think the protocol is the same...is't it????. so
if i can implement PCI2.1 that is equivalent to PCI2.2.

waiting for reply
Thank in advance
praveen

Article: 52297
Subject: Re: clock ditribution tree
From: "MooCow" <reply@to.group>
Date: Thu, 06 Feb 2003 11:14:31 GMT
Links: << >>  << T >>  << A >>
I give up


"Skillwood" <skillwoodNOSPAM@hotmail.com> wrote in message
news:b1qqmt$15umdr$1@ID-159866.news.dfncis.de...
> Hi all,
> what is a clock distribution tree?
> Skillwood
>
>


Article: 52298
Subject: Re: Switching synthesis tools
From: <khtsoi@pc90026.cse.cuhk.edu.hk>
Date: 6 Feb 2003 11:38:55 GMT
Links: << >>  << T >>  << A >>
Nicholas Girde <hereisjunk@yahoo.com> wrote:
> Hi,

> I've been using Synopsys' FPGA Compiler2 for about a year now (and
> their FPGA Express that came with Xilinx Foundation before that) I
> know lot of people complain that its slower, supports lesser vhdl
> cosntructs etc., but its worked fine for me so far. Could you guys let
> me know if there is any other reason why I should trying the other
> tools out there? (Btw, I work on VIRTEX2 currently and am thinking of
> using STRATIX some time soon.)
Hi,
This may be a little off topic. Have you ever used the register-retiming
feature of FC2? I found that it never work even for the obvious examples
I wrote to test the function. But the document (from Synopsys) states it
loud and clear.
Also, does any one know which synthesis tool are the best *under Linux*?
I mean the stable and functional measure. Does any of them can run
without the WINE (that is, compiled and run for native Linux codes)?
Thanks!

> Any advice, welcome!

> - Nick

-- 
Tsoi Kuen Hung (Brittle)
CSE CUHK

Article: 52299
Subject: NIOS and ACEX1K
From: "Giaccaglini Giorgio" <g.giaccaglini@libero.it>
Date: Thu, 6 Feb 2003 12:49:38 +0100
Links: << >>  << T >>  << A >>
Hi

I'm trying to implement a NIOS CPU on a ACEX1K100-1 from Altera.

The only problem that I have is the fmax that I can use; I need 33MHz while
Quartus II is able to use a fmax of 25Mhz.

ACEX1K family should be able to support  PCI interface ( 33Mhz and 64Mhz) so
I don't understand while the fmax is 25Mhz.

Can somebody help me?.

Thanks





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