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I'm looking for information/papers on CIC Filters using RNS. I appreciate your help, CharlesArticle: 54451
In article <8026e003.0304101416.18c403c8@posting.google.com>, Thomas Jones <bonehead95121@yahoo.com> wrote: > >We have come up with a scheme to use dual-ported RAM for message >passing. I will present a strawman and invite all to take potshots. Do you have a full set of address lines to the RAM (or a data/address latch arrangement) or are you driving the address lines with a counter? If you can easily target a pointer location then you can use 2 words as pointers (one for the writer, one for the reader) that they update as they march through memory. This gives you back a lot of bits (no need for valid on everything anymore). Have you considered using some kind of dedicated FIFO for this? You could implement one with a PIC (eg see the parallel slave mode in the 18F452 to handle one port, the other you could do manually). It could detect overflow for you. You could even re-order the messages by priority or fold duplicates. I'm sure a PAL could do this somehow as well. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 54452
I'm looking at a design with an interesting PCI issue. What I need to know is what does a x86 BIOS (on a compact PCI board) do with a very large base address register: to wit 256 GB? This BAR is far too large to map into the CPU's 4 GB limit. Even if the CPU had the new Intel paged address scheme (4 extra address bits, for 64 GB total??), it still wouldn't have enough address space to map this. What does a BIOS do? Even more to the point, what should a BIOS do? While this BAR is on a bus the CPU sees, the CPU doesn't need to access this memory space. It is for communication between other devices on this PCI-X bus. If the BIOS just left it alone, unmapped, that would be just fine... But does it?? Any suggestions? Hints? Wild guesses? -- Phil HaysArticle: 54453
Hi Duane- Thanks... I checked and it was set to "For Inputs and Outputs". I also tried instantiating a "FD" element. Still no luck. The element gets mapped to a DFF, but not inside an IOB. Any ideas? Jake Duane Clark <junkmail@junkmail.com> wrote in message news:<b74gbp0jna@enews1.newsguy.com>... > Jake Janovetz wrote: > > Hi folks... > > > > It's been a long time since I've posted here. Seems like forever. > > I'm having a bear of a time trying to get a particular design to map > > IOB FFs to registered outputs and was hoping someone here could help. > > > > I've read several items found in Xilinx answers and technical > > documentation and it's not working. I would prefer not to explicitly > > instantiate the IOB FF in my Verilog, but it may be the next step. > > I've turned on IOB FF mapping in XST (it's on auto by default). > > Essentially, my code is: > > There are two places where the mapping has to be turned on. The first is > in the synthesis properties, which you already have. The second is in > the "Process Properties", where you need to select the tab "Map Properties".Article: 54454
Jim Stewart wrote: > Steve Lass wrote: > >> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our >> next major release, which is 6.1i in September. > > But what about Win98? Lots and lots of people use > it and refuse to upgrade. Couldn't take that > much effort to support it since it apparently > runs now with a minor workaround. I use win98 in win4lin in debian linux so i can use windoze legacy crap like eprom programmer software. win4lin or wine solves most remaining problems of going linux.Article: 54455
Thomas Jones wrote:
>
> Hello,
>
> We have come up with a scheme to use dual-ported RAM for message
> passing. I will present a strawman and invite all to take potshots.
>
> The scheme is thus: It is a strictly simplex communication scheme
> utilizing dual-port, synchronous read, synchronous write RAM across a
> completely asynchronous interface. Each process has read/write access
> to the RAM. The message writer writes a message and sets a 'valid'
> bit at its In-Pointer location, then advances its In-Pointer. That is
> to say, the message data AND the valid bit are both in the self-same
> RAM.
>
> The message reader spins on its Out-Pointer location waiting for the
> 'valid' bit to be set. Because of the uncertain nature of potentially
> reading and writing the same location at the same time (and the
> attendant, as yet unspecified metastability issues) the reader will
> not act upon a 'valid' until two consecutive are detected. It then
> invalidates the location and advances its Out-Pointer.
>
> To detect a potential FIFO overrun the message writer reads the
> location simultaneously with the write - each port has separate read
> and write data busses, so the write merely asserts write-enable AND
> read-enable. If the 'valid' bit is set then an overrun condition is
> detected. Writer processes which can back-pressure their up-stream
> logic may also spin lock waiting for the 'valid' bit to drop.
>
> Any thoughts? Is this doomed for failure? Are the two consecutive
> reads necessary? sufficient?
Just a thought. I use DP RAM for message exchange but I use two fixed
size command buffers (32 bytes) plus 4 flag bytes to sort out the mess.
The flags indicate buffer valid and buffer busy both ways. The writer
checks valid before writing and sets both busy and valid after the write
and before sending the interrupt. The reader clears busy after copying
the data elsewhere or processing it. The reader sends an interrupt and
the writer clears valid if busy is clear.
In addition, I use a large message buffer for one side to receive 512
byte special messages. The protocol for this buffer is handled through
the 32 byte command buffers. Since the large message buffer is one way,
there is no contention if the command buffer protocol is followed in the
command. There are some minor traps in this but it does work reliably
when done right with RAMs that blow off the write but never the read in
contention. That is, the read data will always be the old data or the
new data while the write may or may not fail.
There may be easier ways but I have to maintain DP RAM communications
with 4 processors with memory overlaps and it would be confusing to try
to handle all of the error possibilities if I implemented 8 circular
buffers plus the two others for a terminal interface using just low end
8 bit risk processors. In any event, I avoid the double write by making
the protocol interrupt driven. Nobody looks at anything the other guy
can write unless there is an interrupt.
Chuck
--
... The times have been,
That, when the brains were out,
the man would die. ... Macbeth
Chuck Simmons chrlsim@webaccess.net
Article: 54456Eric Smith wrote: > > rickman <spamgoeshere4@yahoo.com> writes: > > If you read the requirements for any of the current Xilinx development > > products you will find that they only support two versions of Windows, > > 2000 and XP. This is not a bug and I suspect the only thing about it > > that is not permanent is Win2000 support. My guess is that they will > > drop that in the next release or two. At that point I expect I will use > > something else for FPGA development. I am a long way from moving to > > XP. > > It works OK under Linux using Wine, and Xilinx has promised that they'll > have a native Linux version in 2003, so that should be within the next > 265 days. :-) I had not heard that until this thread. Did they give any details? For example, will the Linux version support all the debug tools, like downloading using the parallel port cable? IIRC, they can't get that to work under WINE. But I may be remembering this badly. That might be Win2k... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54457
On Thu, 10 Apr 2003 17:47:25 GMT, Ken McElvain <ken@synplicity.com> wrote: >I popped an email off to the compiler folks here at Synplicity about >the vector lengths. They don't see a problem with large >arrays such as your 18432 bits for a block ram or more bits for >initialization of an array of block rams. If you have seen >a problem then please let us know. Yes, I didn't notice any problem (other than the speed and memory usage) with reasonably longish vectors when I tried them. Thanks, Allan. > >- Ken > > >Allan Herriman wrote: > >> On Thu, 03 Apr 2003 09:57:06 -0800, Mike Treseler <tres@fluke.com> >> wrote: >> >> >>>Allan Herriman wrote: >>> >>>>Hi, >>>> >>>>Does anyone have experience with VHDL tool support for bit vectors >>>>(or vectors of other types) that have lots of elements? >>>> >>>>I'm thinking of using one for a generic or a constant (not a signal) >>>>to hold the initialisation value for a Xilinx block ram (18432 bits). >>>> >>>>I'm interested in both simulation and synthesis. >>>> >>> >>>Initialization for a block RAM occurs when the binary >>>image is loaded into into the device. The only way to >>>to control this from VHDL source is with device >>>specific instances and attributes or by inferring >>>a ROM by declaring a constant array of vectors >>>of an appropriate size. >>> >> >> Not quite the "only way". In simulation, one needs to use the INIT_XX >> generics on the block rams. The attributes are ignored. >> >> >>>Sim and synth tools can handle vector widths >>>of several hundred thousand bits, up to natural'high. >>> >> >> Somehow I can't see any tool working with a vector length of 2 ** 31 - >> 1. (At least not under versions of Windows that have problems >> allocating more than 2Gbyte of ram to a process.) >> >> I have seen std_logic_vectors of several hundred thousand bits used in >> Modelsim quite successfully. >> >> Does anyone have any other practical experience? I was rather hoping >> someone from Synplicity would reply. I know they read this news >> group. >> >> Thanks, >> Allan. >>Article: 54458
Jake,
You are not the only one having a problem with Xilinx IOB.
While back, I also had problems with it, and took about two weeks to
figure out XST to duplicate FFs.
The thing about an IOB FF is that, unless the fan out coming out of the
FF is one (1), the FF won't be pushed into the IOB.
If you are not seeing the FFs getting pushed into IOBs, very likely the
fan out coming out is not one.
To see the fan out coming out of a FF, look at an EDIF netlist generated
by the synthesis tool, however, when ISE 4.1 was released, Xilinx
"officially" dropped EDIF netlist generation capability from XST.
But after some experiments, I found a way to get XST to generate an EDIF
netlist, and these two postings explain how to do it.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=aceeac%249fj%241%40newsreader.mailgate.org
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=ad2sbv%248u0%2401%241%40news.t-online.com
After you figure out the FF fan out issue, read this posting,
and follow the instructions I wrote.
http://groups.google.com/groups?hl=en&lr=&ie=UTF-8&selm=cc7b0b5f.0210081256.22ba2b1f%40posting.google.com&rnum=4
I hope the instructions are helpful, and let me know if it
worked or not.
Kevin Brace (If someone wants to respond to what I wrote, I prefer if
you will do so within the newsgroup.)
Jake Janovetz wrote:
>
> Hi Duane-
>
> Thanks... I checked and it was set to "For Inputs and Outputs". I
> also tried instantiating a "FD" element. Still no luck. The element
> gets mapped to a DFF, but not inside an IOB.
>
> Any ideas?
>
> Jake
>
Article: 54459On Thu, 10 Apr 2003 20:47:06 GMT, Ken McElvain <ken@synplicity.com> wrote: >With a current version of Synplify generics on black box instantiations >are passed into the edif so you don't need to do the old trick of >generics for simulation and attributes for edif. > >Knowing how things work in the compiler I would think that using a 2-d >array for the table would be much more memory efficient. > >There has also been a lot of work over the last couple of releases on >decreasing the memory used for large constant tables. I would recommend >trying the 7.3 beta. If that doesn't work for you then let me know. How do I download the 7.3 beta? I can't find any references to it on your web site. Thanks, Allan.Article: 54460
"Jesse Kempa" <kempaj@yahoo.com> schrieb im Newsbeitrag news:95776079.0304101402.384b49ed@posting.google.com... > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message news:<ezbla.141931$fH1.1241184@news.chello.at>... > > > I've been playing with my Altera Stratix NIOS Developer Board and it's > > > really neat to write the configuration to the AMD FLASH using tftp > > > from my Linux machine :-) It only takes a second or so to upload the > > > hexout file. > > > > That's the same way I do with my ACEX/Cyclone boards. If you have a working > > Ethernet connection with your FPGA it's really more fun. But I'm using > > Windows and had to write a few lines of Java for the tftp (For interest send > > me a mail). > > > > Martin > > > > -------------------------------------------------------- > > JOP - a Java Processor core for FPGAs now > > on Cyclone: http://www.jopdesign.com/cyclone/ > > I'm really happy to see that others find the tftp support in the > reference design as cool as I do - no more downloads at 115,200 UART > speeds :) Sorry, but I'm not using the reference design nor do I use Nios. The boards are my own design and the tftp-Server (in the FPGA) was written in Java running on JOP, a soft core Java Processor :-) > > In case you guys did not already know, the bash/cygwin environment > that ships with the Nios kit also has tftp built in... for those using > Windows environments this is helpful. I usually just leave my dev > boards and machines connected to a common ethernet hub and do my > .hexout downloads from the web server, though. > > Jesse Kempa > Altera > jkempa @ altera dot com (nospam: remove spaces) Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 54461
Please see our web at http://www.ipflex.com/english/1_index.html . Makoto Honda IP Flex Incorporated "Jihan Zhu" <jihan@itee.uq.edu.au> wrote in message news:b757me$m2n$1@bunyip.cc.uq.edu.au... > > Hello, > > > > I am wondering if you know any available FPGA devices which are dynamically > reconfigurable. I am doing a project in the area of evolvable hardware and I > am looking to buy a board with dynamic reconfigurable FPGAs. > > > > Thank you in advance for any pointers, > > > > JihanArticle: 54462
> I wrote: > > Does NIOS come with an Ethernet MAC, or is one available that doesn't > > cost an arm and a leg? I was thinking about using a Xilinx part with > > Microblaze, but Xilinx wants big bucks for their Ethernet, so I'd have > > to try to interface the one from OpenCores. > > Never mind, I found it myself. Altera's Ethernet core is even more > expensive that Xilinx's. The one from OpenCores is looking more attractive > all the time. Now I just need to build a PHY module for use with the > Burched board. I think I'll use the Level One (Intel) LXT972. As you need a PHY modul I think it does not make sense to implement MAC in the FPGA. You get an ethernet chip for a few $ with PHY, MAC internal memory buffers. You save a lot of LEs in the FPGA. I'm using the CS8900. Very simple to connect to the FPGA and good application notes. I ported the Linux driver to Java. If you need a connection diagram or the Java driver you can find it on my website :-) Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 54463
Eric Smith <eric-no-spam-for-me@brouhaha.com> writes: > I wrote: > > Does NIOS come with an Ethernet MAC, or is one available that doesn't > > cost an arm and a leg? I was thinking about using a Xilinx part with > > Microblaze, but Xilinx wants big bucks for their Ethernet, so I'd have > > to try to interface the one from OpenCores. > > Never mind, I found it myself. Altera's Ethernet core is even more > expensive that Xilinx's. The one from OpenCores is looking more attractive > all the time. Now I just need to build a PHY module for use with the > Burched board. I think I'll use the Level One (Intel) LXT972. The NIOS Development Board Startix Edition uses LAN91C111. There's also support for a CS8900 in NIOS/SOPC Builder. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54464
thank you for your information, but now I must implementation the standard IEEE 1284 on Altera's FPGA. How I can make? Someone knows gives some indication to me on like writing or finding of the code? Thanks "Georg Acher" <acher@in.tum.de> ha scritto nel messaggio news:b747ns$6pn$1@wsc10.lrz-muenchen.de... > In article <Uhdla.24800$iy5.696256@twister2.libero.it>, > "Fabrizio Mezzetti" <fmezzo@libero.it> writes: > |> Hi my name is Fabrizio and I'm student. I must implementation standard > |> parallel port (slave) ieee1284 on FPGA. > |> someone can gives some idea and to suggest to me some interesting web site > |> one to me to consult? Thanks > > http://www.beyondlogic.org/epp/epp.htm > -- > Georg Acher, acher@in.tum.de > http://wwwbode.in.tum.de/~acher > "Oh no, not again !" The bowl of petuniasArticle: 54465
I started to change from AHDL to VHDL with Leonardo and MAX+Plus some time ago. It was not the very comfortable way with two tools and some problems with Leonard. But I got used to it. Using now Cyclone parts I had to switch to Quartus. Still using Leonardo for synthesis. After getting the mail about the end of Loenardo support I started to use synthesis in Quartus. I got 'almost' the same result. More LEs but a higher fmax. That's good. But there is one problem where the design behaves different! Still searching for the reason. And I'm 'blind' debugging because the post rout simulation does not work for this design in Quartus. I get following error: Internal Error: Sub-system: EDS, File: ./eds_manager.cpp, Line: 616 event_ptr->get_projected_time() >= m_current_time Quartus II Version 2.2 Build 176 02/04/2003 SJ Web Edition Service Pack Installed: 1 For simple projects the simulation works. I can run the simulation in the Leonardo/MAX tool chain, but this does not help. Martin -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Chris Balough" <cbalough@altera.com> schrieb im Newsbeitrag news:d8b8faad.0304081642.192c8d96@posting.google.com... > Hello, > > First, it's important to be clear that there are several high quality > synthesis options available for all Altera products. > > Altera is committed to ensuring our customers have a full range of > synthesis solutions for all of our devices, from our MAX CPLD devices > to our high performance Stratix and Stratix GX families and the > low-cost Cyclone family. Altera has strong partnerships with all of > the major 3rd party synthesis tool vendors, including Mentor, > Synopsys, and Synplicity. We also offer an integrated synthesis option > that is included with all of the Quartus II Design Software packages. > As a further service to our customers, Altera has worked with Mentor > and Synplicity to make available some very attractive promotional > offers for Altera synthesis solutions. > > For more information on the 3rd party synthesis tools available for > Altera devices, please see the following page on our website: > http://www.altera.com/products/software/pld/eda/partners/eda-index.html > > For more information on Altera's integrated synthesis tool, please > download the following application note: > http://www.altera.com/literature/an/an238.pdf > > Cheers, Chris > > Spam Hater <spam_hater_7@email.com> wrote in message news:<96319v4udn64fnkeqp04tr2q50srustpov@4ax.com>... > > Kevin, > > > > Because Xilinx did the same thing a year and a half ago. > > > > Basically, both used OEM'd synthesis tools for their 5V FPGAs. Altera > > used Leonardo, Xilinx used Foundation. > > > > Both have terminated their OEM agreements. > > > > Xilinx currently has -zero- synthesis tools for their 5V FPGAs. And > > no intention to get them. > > > > At last with Altera, you can still use Max+II. > > > > $.02, > > SH > > > > > > On Fri, 04 Apr 2003 23:10:17 -0600, Kevin Brace > > <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: > > > > >Paul, > > > > > >I don't mean to start an A vs. X argument here, if you don't like what > > >Altera did to you, why not switch to Xilinx?Article: 54466
Thomas Jones wrote: > > The scheme is thus: It is a strictly simplex communication scheme > utilizing dual-port, synchronous read, synchronous write RAM across a > completely asynchronous interface. Each process has read/write access > to the RAM. The message writer writes a message and sets a 'valid' > bit at its In-Pointer location, then advances its In-Pointer. That is > to say, the message data AND the valid bit are both in the self-same > RAM. > > The message reader spins on its Out-Pointer location waiting for the > 'valid' bit to be set. Because of the uncertain nature of potentially > reading and writing the same location at the same time (and the > attendant, as yet unspecified metastability issues) the reader will > not act upon a 'valid' until two consecutive are detected. It then > invalidates the location and advances its Out-Pointer. No need for two consecutive reads. It's very easy really, you don't have to be simplex either. Give each side its own data areas for write and read- write to one is read to the other. (this is just your convention, you don't have to physically hide the data on the write side). Have one or more data ready flags in each area, these can be read and written from either side. Wait for the flag to be clear, then write the data, then set the flag. It doesn't matter whether you are just setting it or it's been there for some time, the data is valid. On the read side, wait for the flag to be set. When it is set, read the data then clear the flag. The other side can't write until it's clear, so it doesn't matter whether it is just setting or has been hanging around. The hardware must of course sort out the priority in the case of simultaneous accesses. I first did this with 6809s in 1983, so it's well tried and tested! Paul BurkeArticle: 54467
Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: : Jake, : You are not the only one having a problem with Xilinx IOB. One thing that is missleading in the data sheet is the polarity of the Tristate Output Buffer enable. While it is shown "active high " in the data sheets, it is "active low" in reality. So with al the other prerequisits set, a verilog expression like inout [7:0] busdata; wire busenable; wire [7:0] outdata; assign busdata = (busenable)? outdata: 8'bz; doesn't get pushed into the IOBs, but assign busdata = (!busenable)? 8'bz: outdata; _gets_ pushed into the IOBs. It took me some time to find out. A request to clarify the data sheets is pending... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54468
Russell Shaw <rjshaw@iprimus.com.au> wrote: : Jim Stewart wrote: :> Steve Lass wrote: :> :>> Native Linux (7.3 and 8.0) and Windows2000 will both be supported in our :>> next major release, which is 6.1i in September. :> :> But what about Win98? Lots and lots of people use :> it and refuse to upgrade. Couldn't take that :> much effort to support it since it apparently :> runs now with a minor workaround. : I use win98 in win4lin in debian linux so i can use windoze : legacy crap like eprom programmer software. win4lin or wine : solves most remaining problems of going linux. But it will not run Webpack.... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54469
Allan Herriman <allan_herriman.hates.spam@agilent.com> writes: > I never instantiate "bare" block rams. Instead, I always instantiate > them via a wrapper component. > The wrapper takes generics to indicate the desired width of the > address and data buses, and the fpga family (Virtex-E, Virtex-2, > etc.), and it works out the most efficient way to achieve the result. > I'm just about to start down the Xilinx road and has thought of doing a similar thing myself (I've been spoiled by Altera's LPM_RAM, which does a similar thing for you). Don't suppose you can share the code with us to save reinventing the wheel (probably square to start with in my case :-) Thanks, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 54470
On 11 Apr 2003 09:38:30 +0100, Martin Thompson <martin.j.thompson@trw.com> wrote: >Allan Herriman <allan_herriman.hates.spam@agilent.com> writes: > > >> I never instantiate "bare" block rams. Instead, I always instantiate >> them via a wrapper component. >> The wrapper takes generics to indicate the desired width of the >> address and data buses, and the fpga family (Virtex-E, Virtex-2, >> etc.), and it works out the most efficient way to achieve the result. >> > >I'm just about to start down the Xilinx road and has thought of doing >a similar thing myself (I've been spoiled by Altera's LPM_RAM, which >does a similar thing for you). Don't suppose you can share the code >with us to save reinventing the wheel (probably square to start with >in my case :-) It's proprietry code, sorry. Allan.Article: 54471
Jihan Zhu wrote: > Hello, > I am wondering if you know any available FPGA devices which are dynamically > reconfigurable. I am doing a project in the area of evolvable hardware and I > am looking to buy a board with dynamic reconfigurable FPGAs. AFAIK, they all are dynamically reconfigurable. Not all are partially reconfigurable though. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 54472
The point I was trying to make in my original post was that the Quartus tools fall over all too frequently in new and surprising ways. The support answer usually is 'fixed next release' and then you just get a different set of problems. I can't run a business continually chasing problems with 'almost working' tools. I had to change to ActiveHDL (ModelSIM would also be acceptable to many) because I needed robust simulation. I don't mind paying for robust synthesis tools either, I just object to paying Altera for a full 'suite' of software when all I actually 'need' is the PAR and sometimes programmer support. I found command line Leonardo robust enough though did need to tweak its interface with ActiveHDL to get the right optimisations but now using ActiveHDL for design entry and its control of leonardo, Quartus's PAR and ActiveHDL's simulator, I have (had) a reasonable design flow. I am under the impression that for PAR, I only have Quartus PAR available to me, so have no choice but to begrudgingly pay Altera for the priviledge. Don't get me wrong, Xilinx no doubt have similar problems, as often intimated by Ray's frustration with the floorplanner etc. and in general I am happy to continue using Altera silicon, but I AM frustrated by the lack of value in the Altera subscription offering in all but simple designs. I use it because I am forced to use it for PAR. Paul Baxter, opinions are my own, of course.Article: 54473
Thanks, Uwe- I'll look at this possibility. I found _my_ err, though. Since I don't have the FPGA editor for a little while (offsite, using the Webpack), I was trying to use the floorplanner information to determine if something was pushed to the IOB by looking at the IOB pin mappings. It doesn't appear that this is a valid method to determine IOB packing. Does anyone have any suggestions on how else to see if a FF is inside the IOB? I'm going to try Kevin's EDIF output, but wouldn't expect that to tell me. I definitely only have a fanout of 1. My test case while I play with this is IPAD -> FF -> OPAD. Pretty basic. Cheers, Jake Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:<b75t3g$3ao$1@news.tu-darmstadt.de>... > Kevin Brace <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: > : Jake, > > : You are not the only one having a problem with Xilinx IOB. > > One thing that is missleading in the data sheet is the polarity of the > Tristate Output Buffer enable. While it is shown "active high " in the data > sheets, it is "active low" in reality. So with al the other prerequisits > set, a verilog expression like > > inout [7:0] busdata; > wire busenable; > wire [7:0] outdata; > > assign busdata = (busenable)? outdata: 8'bz; > > doesn't get pushed into the IOBs, but > > assign busdata = (!busenable)? 8'bz: outdata; > > _gets_ pushed into the IOBs. > > It took me some time to find out. A request to clarify the data sheets is > pending... > > ByeArticle: 54474
Jake Janovetz wrote: > Does anyone have any suggestions on how else to see if a FF is inside > the IOB? Set offset timing constraint in the ucf file that will fail unless the FF is inside the IOB. -- Phil Hays
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