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Jeremy, please give us more details: The way I understand it, you have eight data inputs, each with its own clock. All eight clocks have the same frequency, but have different delays (phases). That seems to imply that you have no problem registering each bit in the FPGA, but there is significant skew between these input registers. I suppose you want to get all 8 bits into the same clock domain, and that is your problem (right?) What is the frequency, and what is the max skew ( in ns or in phase angle)? When you wrote: "each with its own frequency (but not phase) related clock", I really had to guess what you possibly might have intended to say... Peter Alfke, Xilinx Applications ====================== Jeremy Whatley wrote: > > I am trying to interface a Virtex2 to an ASIC with very poor clock/data > timing. The data coming out of this ASIC is arriving as 8 distinct > channels, each with its own frequency (but not phase) related clock. There > are too many clocks for me to adjust their phases with DCMs to match the > data. I also cannot use global clock buffers for the same reason, but I do > not need to drive very many flip-flops, so skew is not an issue. > > I need to find a way to manually insert delay in my clock line. Inverting > the clock does not provide the correct phase relationship. I have tried > instantiating some AND2 primitives and placing them in the clock path, but > doing this has a seemingly random effect. Does anyone have any ideas on how > to do this? > > Thanks!!! > > Jeremy Whatley > jeremyw@erlangtech.comArticle: 52901
"Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag news:3e5b9ae9$1_4@corp.newsgroups.com... > Is this normal, that a blank CPLD is driving high the IO-Pin? Usually not, but there are AFAIK some weak pull-up. -- MfG FalkArticle: 52902
Hi all,
I need some help with DCT/IDCT algorithms based on polynomial transforms.
To be more exact, I'm working on algorithms from Duhamel and Prado, as well
on the newer Yonghong Zeng's algorithm.
So far I have furnished the proofs, but haven't been able to simulate them
correctly.
It seems that I'm having problems in organization of compuation or
computation
of polynomial transforms.
Does anybody have any experience with it ? Please contact me.
Also any reference to code (C/C++/VHDL/whatever) implementing these
algorithms
would be highly appreciated.
--
Domagoj Babic
domagoj (et) engineer.com
Article: 52903Stuart Brorson <sdb@cloud9.net> wrote: : Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: : : Stuart Brorson <sdb@cloud9.net> wrote: : : : David Brown <david@no.westcontrol.spam.com> wrote: : : : p.s. Now when is Xilinx going to offer WebPack for Linux? And, no, I : : : don't mean running the command line tools under Wine. . . . . : : One a recent and well configured wine, you can install and run Xilinx : : Webpack even in graphical mode, as I now to with the placer in the : : background :-) : Recent rev of Wine I can manage. Well configured, well . . . . : that's another issue. Maybe it works for you, but it never works for : me. :-( Well worked out error reports and resonable questions mostly get answered on com.emulator.ms-windows.wine or the wine-devel mailing list. But working things out requires some persistance. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 52904
As far as I know one of the limitations in XE starter is the low speed of simulation. Your test just shows that this is true. You should really compare apples to apples. Andras Tantos >> Matt wrote: >> >>And as a little comparison, I recently ran a simulation of a couple >> >>thousand line program on similar machines. A simulation that under >> >>Modelsim SE/Linux took 20 seconds, required 30 minutes under Modelsim >> >>XE-Starter/Windows 2000! Yikes! >> >> >> >>... oops, are we not supposed to post benchmarks ;) >> > >> > >> > ModelSim SE (Linux) vs. ModelSim XE-Starter (Win2K)... huh? And what >> > Scientific method are claiming to use? >> >> I don't believe I made any such claim. I merely found a 90 to 1 >> difference to be rather astonishing. >>Article: 52905
Well what do I have in the design. 1.) I have a blank CPLD 9036XL, at least that's what the impact software 5.1 SP3 is saying. 2.) I have a clock running at 48 MHz 3.) I have a global set reset signal I agree nothing should happen, however in parallel I do have a Spartan-II FPGA That is currently not configured. The spartan-II FPGA has a 16Bit data bus. The Upper 8 Bits are connected to the blank CPLD as well. Using an oscilloscope I Can see that the lower 8 Bit's - from the Spartan-II device - are undriven. The Upper 8 bits - all of them connected to the empty CPLD as well - are high. No Idea why this is so. I will try to load a design into the CPLD in order to See if something is changing. All of the boards do behave the same. All of them Are new boards directly coming out from assembly... I just wonder if something on those CPLD's is damaged ... P.S. I connect an additional CPU print to the 16Bit data bus. This CPU print is Currently not running. I guess it's because of those 8 high driven bits from the CPLD. When I use the same CPU print in an older version of the design everything Works fine. In the older version no CPLD is present ... But the Spartan-II FPGA is Markus "Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:<b3gegp$1lpt6e$1@ID-84877.news.dfncis.de>... > "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag > news:3e5b9ae9$1_4@corp.newsgroups.com... > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > Usually not, but there are AFAIK some weak pull-up. > > -- > MfG > Falk > > > > "Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag news:b3gegp$1lpt6e$1@ID-84877.news.dfncis.de... > "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag > news:3e5b9ae9$1_4@corp.newsgroups.com... > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > Usually not, but there are AFAIK some weak pull-up. > > -- > MfG > Falk > > > >Article: 52906
You might want to look at xapp609, "Local Clocking Resources in Virtex-II Devices". It shows how capture data at the IOBs with ad-hoc clocks, then recapture with a global clock. Perhaps your external timing still won't support this, though, and the pinout has to be right for the incoming clocks. Cheers, Peter MontaArticle: 52907
Markus, when measuring High or Low on a bus or any other output, I usually also attach a 1 kilohm resistor to the opposite voltage. And any voltage change then tells me something about the output impedance, the "stiffness" of the voltage. 1 kilohm does not affect an active output at all, but moves a "weak pull-up or -down" output almost all the way. Peter Alfke, Xilinx Applications ====================== Markus Meng wrote: > > Well what do I have in the design. > > 1.) I have a blank CPLD 9036XL, at least that's what the impact software > > 5.1 SP3 is saying. > > 2.) I have a clock running at 48 MHz > > 3.) I have a global set reset signal > > I agree nothing should happen, however in parallel I do have a Spartan-II > FPGA > > That is currently not configured. The spartan-II FPGA has a 16Bit data bus. > The > > Upper 8 Bits are connected to the blank CPLD as well. Using an oscilloscope > I > > Can see that the lower 8 Bit's - from the Spartan-II device - are undriven. > The > > Upper 8 bits - all of them connected to the empty CPLD as well - are high. > No > > Idea why this is so. I will try to load a design into the CPLD in order to > > See if something is changing. All of the boards do behave the same. All of > them > > Are new boards directly coming out from assembly... > > I just wonder if something on those CPLD's is damaged ... > > P.S. I connect an additional CPU print to the 16Bit data bus. This CPU print > is > > Currently not running. I guess it's because of those 8 high driven bits from > the > > CPLD. When I use the same CPU print in an older version of the design > everything > > Works fine. In the older version no CPLD is present ... But the Spartan-II > FPGA is > > Markus > > "Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag > news:<b3gegp$1lpt6e$1@ID-84877.news.dfncis.de>... > > > "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag > > > news:3e5b9ae9$1_4@corp.newsgroups.com... > > > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > > > > > Usually not, but there are AFAIK some weak pull-up. > > > > > > -- > > > MfG > > > Falk > > > > > > > > > > > > > > "Falk Brunner" <Falk.Brunner@gmx.de> schrieb im Newsbeitrag > news:b3gegp$1lpt6e$1@ID-84877.news.dfncis.de... > > "Markus Meng" <meng.engineering@bluewin.ch> schrieb im Newsbeitrag > > news:3e5b9ae9$1_4@corp.newsgroups.com... > > > Is this normal, that a blank CPLD is driving high the IO-Pin? > > > > Usually not, but there are AFAIK some weak pull-up. > > > > -- > > MfG > > Falk > > > > > > > >Article: 52908
Erik, When using PCI33_5 I/O pads, slew rate cannot be adjusted (That can be adjusted only when you are using LVTTL and LVCMOS I/O pads.). Yes, PCI33_5 I/O pad is slow compared to PCI33_3, PCI66_3, or LVTTL_F_24 I/O pad, but that's just too bad, and you will just have to get used to it. From what you are saying, my guess is that you are not meeting 33MHz PCI's Tval < 11ns requirement. If you are targeting Virtex-4, Virtex-5, or Spartan-II-5, and you are using PCI33_5 I/O pad, very likely you will never meet Tval < 11ns as long as you don't use IOB output FF and IOB tri-state FF. However, if you utilize IOB FFs, you can meet Tval < 11ns easily. In order to utilize IOB output FF and tri-state FF, those FFs will have to have a fan-out of one, however, most of the time, the logic the synthesis tool generates will have a feedback path from the FF to a LUT, and that alone will break the single fan-out rule. Most synthesis tools should be able to duplicate the FFs for you if you ask it to, or you can duplicate the FFs by editing an EDIF netlist generated by the synthesis tool using a text editor. The only problem of editing an EDIF netlist is it takes an hour or so to correctly duplicate the FFs, so I have to admit, I only do so when I really have to. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) Erik Spaenig wrote: > > Hi all, > > I use the Xilinx WebPack (Release 4.2WP2.x - Par E.37) for an SpartanII > > in my prjekt sometimes say the "Pad Report" from "Place & Route" the > SlewRate for the PCI-pads (IO-Standart : PCI33_5) is Slow > and this is the "Default value". > > where can i switch this value permanetly to a fast SlewRate ?? > > Thanks for Help > Erik Spaenig > > ----- > sorry for my terrible english, > my favorit language is assemblerArticle: 52909
Praveen, The Expansion ROM in PCI is to map the expansion ROM code to a specific location of the memory map. I believe a PCI SCSI card with an external ROM use this feature to let the IBM PC/AT compatible BIOS map the external ROM to a location below the 1MB memory area, so that the user can boot the system from a SCSI hard drive. That's just one example, and other devices like an IDE RAID card probably also uses it. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.) praveen wrote: > > Hello sir, > what is use of expansion ROM in case of PCI. Usually there will be > external EPROM for loading the content of configuration part of PCI > bridge. Does the expansion ROM have the same content. So instead of > external EPROM, expansion ROM can be used..... Is it????? > please reply soon > > waiting for reply > praveenArticle: 52910
chris Shaw wrote: > Bertram Geiger wrote: > > > chris Shaw schrieb: > > > I'm trying to rebuild an old ABEL file and I don't seem to be able to > > > get any of the tools - abl2pld, abl2edif, etc - to produce an output > > > netlist. They all fail from 2.1i to 4.1i. > > > > > > What I *do* get is a warning message saying that the tools can't find > > > some file called Xabel.msg > > > > > > > I dont know your software environment, but webpack does all the ABEL > > very well e.g. for the XILINX 9500 devices > > greetings, Bertram > > Thanks to both you & Jim. > > I've now found out, sort of, whats going on. The old BLIF flow that I used > to use via the command line + makefiles is now obsolete and has been > replaced by ABEL-XST. Deeply embedded in it is one of the old programs - > ahdl2blf - but it no longer seems possible to run it from a command line so > I've had to go by the &^%$)**ing GUI. Not only that but our main tool set > is Alliance so we don't actually have XST so I had to download 100MB+ of > WebPACK to get it all to work. No too bad while I'm in the office on a 2Mb > link but its going to be tedious to do from home! > > All I wanted to do was to produce a .pld file which I could convert to a > Verilog simulation model via NGDBUILD/NGD2VER ... sigh. Well, you can run ahdl2blf from the command line.... Of course, we don't document it or support it, so don't tell the apps folks I told you so ;-) But I would still suggest using Webpack. You don't need to download the full configuration - if you're not interested in programming a chip you don't need the implementation tools. VHDL and Verilog simulation is fully supported for Abel sources in a iSE/Webpack project. The basic steps are: 0. Download and install Webpack and the MXE (Modelsim Xilinx Edition) module. 1. Launch iSE Project Navigator. 2. Do File->New Project. Select either the Abel-XST/VHDL or Abel-XST/Verilog flow, depending on your preference. 3. Do Project->Add Source. Select your Abel file. 4. the iSE "Sources in Project" window should automatically update to show your source. If your Abel file includes Abel test vectors, it will automatically add a second (I would call it a "phantom") source for the test vectors. 5. Click on the test vectors source, and the "Processes for current source" window will update to show the available simulation processes. If you've got MXE properly installed, this should include "Simulate Behavioral <HDL of your choice> model". Run this process, and both the Abel equations and vectors should be translated to <HDL of your choice> and MXE launched. Simulate away.... Behind the curtains what is happening is that we run ahdl2blf to generate the old BLIF format file, but then translate it to <HDL of your choice> for both MXE and XST. And of course the old Abel Equation Simulator (blifsim) is still available, it's the process labeled "Generate Blif Simulation Report". The command line(s) used to do all this can be seen in the <module_name>.cmd_log file that iSE creates. A little cutting&pasting and you can be scripting away... -Dennis McCrohan Xilinx CPLD S/WArticle: 52911
I know that altera Maxplus has option of giving a VHDL code for a schematic design,do xilinx has this option.If it has, I am curious to know how i can generate a VHDL code from a schematic design?(It is not part of any homework or a project as some feared ...) with regards, bmsArticle: 52912
Stuart Brorson wrote:
> David Brown <david@no.westcontrol.spam.com> wrote:
>
> : "Stuart Brorson" <sdb@cloud9.net> wrote in message
> : news:v5mt47homuiq4d@corp.supernews.com...
> :> It's easy and fun to get all resentful about licensing policies. I do
> :> think that companies do their utmost to gouge their customers for
> :> software. They do this when they can. However, the marginal cost of
> :> producing another copy of some software package or another is almost
> :> zero. Therefore, by the grim, iron-clad laws of capitalist economics,
> :> the cost of software will tend towards zero in the long run -- as long
> :> as there is competition. And God bless the free software movement,
> :> which is helping to accelerate this trend. The fact that WebPack is
> :> free evinces this tendency.
>
> : I can understand licencing codes for paid-for software - these sorts of
> : tools are expensive to develop, and the developers want to protect that
> : investment. I am also quite happy with the idea of regular payment for
> : regular upgrades. But I dislike the idea of continuous licence renewal for
> : using the same software, and for free downloads I can't even see any
> : benifits for the supplier. But from these replies, it looks like I don't
> : have to worry about this for current versions of the Xilinx WebPack
> : software.
>
> The economics of software is very interesting, and is not well
> understood, IMHO. You are right: the up-front cost of developing some
> software system or another can be quite high, but if the marginal cost
> of production is zero, then competition drives the price on the market
> to zero. Therefore, the question is: How can SW companies make money
> on producing software? I see three ways:
>
> 1. The company needs to be a monopoly of some sort or another.
> Micro$oft is a good example of this.
>
> 2. The company needs to continually innovate so that there is no
> other competitive company offering the same mix of
> features/abilities. (In a sense, this means that the company is again
> a monopoly.)
>
> 3. The company can give the software away (or sell it for cheap), and
> then make money on services instead. This is the Free Software model,
> and is also used by IBM, Computer Associates, etc. This approach
> makes economic sense, because the marginal cost of producing services
> is never zero. (That is, you need to pay the consultant who is working
> for the client.) On the other hand, this kind of business doesn't
> scale well. Ultimately, you can only bill for the number of hours
> worked by your staff, so you can't ramp up production to increase
> revenue like you can with a factory. The revenues you make only scale
> with the number of bodies you employ.
>
> A chip vendor like Xilinx has a fourth way to generate revenues: sell
> chips. Since the marginal cost of producing a chip is non-zero, they
> will never give the chips away. However, they can give their
> synthesis software away, and treat it as a loss-leader for their
> chips.
>
> Anyway, have fun with WebPack!
4. Because of economy of scale, money can still be made and the
market grown by selling the full version for a *reasonable*
price of $100, and extra charged for phone/email support.
Article: 52913David Brown <david@no.westcontrol.spam.com> wrote in message news:b3fn79$4to$1@news.netpower.no... > > I'm not sure about the Xilinx tools themselves, and - as I said - I'm basing > this on printed literature that is a little out of date. But certainly the > ModelSIM module needs/needed renewal every 30 days, and there were a couple > of other parts that also needed renewal every year. I've used ModelSim PE and XE for years, and this is the first I have heard of having to renew the license every 30 days. Perhaps you are thinking of their eval license, which is usually good for 30 days?Article: 52914
If I recall correctly, MT has said the ratio of performances of the different versions is something like this: ModelSim SE = 3 x ModelSim PE ModelSim PE = 5 x ModelSim XE Which, interestingly is proportional to the price. ModelSim XE starter has a 500 statement "soft" limit. ModelSim XE has a 5000 statement limit. JCArticle: 52915
David, Xilinx ISE WebPACK is completely free. All you need to use ISE WebPACK is to register your name and address with Xilinx, and no license file is required. Unlike other firms distributing free tools (Altera and Actel), Xilinx will also let you use a crippled version of ModelSim for free (ModelSim XE-Starter) which was really helpful in my project. ModelSim XE-Starter has no size limitation, however, the simulation speed drops if the design is larger than 500 statements. It will likely be useless if the design being tested is very large. The license you will get from Xilinx for ModelSim XE-Starter is a perpetual license. ModelSim XE-Starter should be good enough for a small project. I used both tools for developing a PCI IP core with initiator (master)/target capability for Spartan-II. Kevin Brace (If someone wants to respond to what I wrote, I prefer if you will do so within the newsgroup.)Article: 52916
I like your analogy... There are "Dog Years"... and now we have "Chip Years" ? Am I coining an expression right now? Clyde Peter Alfke wrote: > What a tempest in a teapot! Just one tiny nosy question, and Altera > blows up... > > The original request was for a > > • low-performance, > • low-volume, > • not cost-sensitive application > • at high temperature extremes. > > In this case, it would be silly and irresponsible to go for the > cheapest, barely available product family. Proper risk management calls > for something mature and with a proven track record in a hostile environment. > > I often compare the life of an IC family with the life of a human being, > and the IC gets obsolete fifteen times faster than a human ages. > > So, an IC family that was first announced 2 years ago is now like a > 30-year old, at the prime of its strength, and readily available to face > any task. > A family announced 4 years ago, is now like a 60-year old senior > citizen, wise and experienced, but often not competitive for the most > demanding tasks. > A 6-year old IC family is like a 90-year old grand-daddy, and should be > fondly remembered, but not used for new designs. The younger families > are so much better... > > This refers to design ins, not availability or reliability. > We keep our parts in manufacturing often for 10 years. > And, unless overstressed, ICs live and perform for 20 years and more. > > Peter Alfke > ============== > Fredrik wrote: > > > > Hi Peter and David. > > Is Cyclone realy abvalible it is! That a cheep shoot Peter and not > > worhy comming from a competitor to Altera (contact some of your > > customers if you would like to see one :) <snip>.......Article: 52917
I am using Webpack 4.2. Agagin, I really appreciate your help. Thanks Scott Theron Hicks <hicksthe@egr.msu.edu> wrote in message news:<3E5B7CDF.C418A11C@egr.msu.edu>... > Are you using the Webpack or some other version of the tools. In any case, you really do use a VHDL > top level code and then link the lower level EDIF. I don't recall all the details but I will ask the > person who did the actual coding. The easiest solution involves using the regular ISE tools. > However, Webpack will work as well. The older ISE tools (pre 4.2) are a little more difficult. > Again, if you can tell me which version of the tools you are using then the answer is pretty simple > to implement. > > Scott wrote: > > > Thanks for your input Theron. It looks like we're going to just use > > the XAPP233 UART from Xilinx and scrap the USB. > > > > I have been trying to understand the whole "black box" concept talked > > about in the XAPP233 application note. To be honest, I am not sure > > how to do that at all. I understand how to instantiate the UART Tx/Rx > > in VHDL, but am confused on how to link that VHDL code to the given > > macros in XAPP233. Since the marcos are EDIF I need to have my > > project be an EDIF project and not a VHDL project. Im really confused > > on how this is to be implemented. I dont know if you are famililar > > with this particular appliation or not, but I would appreciate your > > thoughts. > > > > Thanks again!!! > > > > Scott > > > > "Theron Hicks" <hicksthe@egr.msu.edu> wrote in message news:<b3e4ph$2iln$1@msunews.cl.msu.edu>... > > > Scott, > > > I am looking at a USB application myself and the nicest option I found > > > is the quickUSB option from QuickUSB. They have a daughter card with a > > > built-in USB 2.0 connection. The card can either go to an altera FPGA or to > > > a break-out board. We are also using the spartan2e. They use a cypress > > > chip (EZ-USB). There also a couple of USB source codes in opencores > > > http://www.opencores.org . If I recall correctly, the full USB core takes a > > > fairly big FPGA. It sounds like the real object of the project is > > > compression not USB. Could you live with a standard com port to do the > > > up-load and down load? I know the time to do the upload/download is > > > horrible but would that do what you want for the project? If so, there are > > > several good UARTs out there. (look at Xilinx for a free reliable UART. > > > XAPP223) > > > > > > Theron Hicks > > > > > > > > > "Scott" <scottiecs@yahoo.com> wrote in message > > > news:ad642abe.0302241334.393e834a@posting.google.com... > > > > I am new to FPGA's and its programming language VHDL. I am working on > > > > an electrical engineering senior project and have a few questions. > > > > 1.) is it possible to connect a USB device (ie a digital camera) to > > > > the Spartan 2e FPGA? 2.) If it is possible, could someone give a > > > > quick overview or a good resource for me to research. 3.) If not, any > > > > good suggestions on how i would go about accomplishing my > > > > objective(see below) > > > > > > > > My main goal is to connect a Digital camera directly to the FPGA board > > > > to get a picture from the camera. Once the picture is loaded into the > > > > FPGA memory i am going to compress that image and then send it to a > > > > computer. > > > > > > > > Thanks in advance!! > > > > ScottArticle: 52919
Hello any of the pros/managers please state what would be other prerequisites (aside from being lot cheaper ) an analog/ASIC/Fpga Design House should fullfill in order to be considered for outsourcing ? any advice wellcome ITArticle: 52920
In article <3e5b9ae9$1_4@corp.newsgroups.com>, meng.engineering@bluewin.ch says... > Is this normal, that a blank CPLD is driving high the IO-Pin? > > markus > Yes, if you look at the data sheet for the 9500XL family (table 5), you can see that the IOB-Bus hold circuitry does a pull-up even for the erased device. Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 52921
> > > > I'm not sure about the Xilinx tools themselves, and - as I said - I'm > basing > > this on printed literature that is a little out of date. But certainly > the > > ModelSIM module needs/needed renewal every 30 days, and there were a > couple > > of other parts that also needed renewal every year. > > I've used ModelSim PE and XE for years, and this is the first I have heard > of having to renew the license every 30 days. Perhaps you are thinking of > their eval license, which is usually good for 30 days? > I'm thinking of the module that comes with the WebPack, according to the Xilinx quick-start book I have. Perhaps that is an evaluation version rather than a specific free but limited version for the tools. I suppose ModelSim is a third-party application, rather than Xilinx's own tool. It still seems a bit odd with a 30-day continually renewable evaluation licence - a one-off 30-day evaluation licence makes sense. Perhaps I misread the information and the 30-day limit is a one-off.Article: 52922
"Kevin Brace" <kev0inbrac1eusen2et@ho3tmail.c4om> wrote in message news:b3h87d$6li$2@newsreader.mailgate.org... > David, > > Xilinx ISE WebPACK is completely free. > All you need to use ISE WebPACK is to register your name and address > with Xilinx, and no license file is required. > Unlike other firms distributing free tools (Altera and Actel), Xilinx > will also let you use a crippled version of ModelSim for free (ModelSim > XE-Starter) which was really helpful in my project. > ModelSim XE-Starter has no size limitation, however, the simulation > speed drops if the design is larger than 500 statements. > It will likely be useless if the design being tested is very large. > The license you will get from Xilinx for ModelSim XE-Starter is a > perpetual license. > ModelSim XE-Starter should be good enough for a small project. > I used both tools for developing a PCI IP core with initiator > (master)/target capability for Spartan-II. > > That's a very useful reply, putting to rest my concerns. I have no problem with the ModelSim version being limited - after all, it is a powerful piece of software, available for free. While the project(s) we are doing are small, the price of full pack development tools would be excessive in the development budget, but if we plan on doing very large projects, then the more expensive and more powerful tools are a sensible investment. I guess my book is out of date when refering to 30-day licences for ModelSim - I suppose Xilinx and ModelSim have reached a better agreement since then, which suits me fine.Article: 52923
TI wrote: > Hello > any of the pros/managers please state what would be other > prerequisites (aside > from being lot cheaper ) an analog/ASIC/Fpga Design House should > fullfill in order to be considered for outsourcing ? > Not posting requirements in public NG's for starters. It indicates that one dont know much about the analog/ASIC/Fpga design flow. Kevin Aylward sales@anasoft.co.uk http://www.anasoft.co.uk SuperSpice, a very affordable Mixed-Mode Windows Simulator with Schematic Capture, Waveform Display, FFT's and Filter Design.Article: 52924
One way to configure a xilinx device is to use a flash plus a cpld for address generation. This could be cheaper than the standard single chip solution from Xilinx (serial eeprom). What we want to do is to use a nand-flash device to configure the fpga to further reduce cost plus the nand flash can also be used as a mass storage device. The idea is to use a 16 bit flash , 8 bits containing the configuration code, 6 bits to do error correction (nand flash is not garanteed error free). The error correction and the nandflash interface could be handled by a cpld. Did someone tried this before? Can anyone give some guidelines/ recommendations/remarks on this idea? Best regards Jo Kenens Acunia nv.
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