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"Nicholas C. Weaver" <nweaver@ribbit.CS.Berkeley.EDU> wrote in message news:bj59us$55k$1@agate.berkeley.edu... > The flip flop core exists in one of THREE states: Vdd, Vss (the stable > points) and Vms +/- epsilon (the metastable range, in between Vdd and > Vss). > > The analog circuitry in the flip flop measures the flip-flop state at > Tdelay after the clock edge. > > If it is within Vms +/- a large epsilon (that is, metastable at this > point in time), the analog circuitry forces the flip-flop to Vss, and > also signals that a metastable capture/correction was performed. nweaver@cs.berkeley.edu The problem is that the analog circuitry that is trying to determine if the flip-flop is in a metastable state can itself go metastable if the flip-flop level is near Vms +/- epsilon. Daniel LangArticle: 60026
Hi I'm an embedded systems designer who feels that it's about time he started to learn about using FPGAs. I'm happy using PLDs, designed in something like CUPL but don't know where to start on bigger devices. I only have a small budget for development tools and I'm in the UK. From what I can see my best choice of manufacturer is probably down to Xilinx or Altera. Can anyone suggest an evaluation board that would get me started? I see that devices are sold in terms of their gate count. How efficient is a typical design? For instance, if I want to make a 16 by 16 CPU controlled crosspoint how many FPGA gates will I need? I can see that I need 16 OR gates each with 16 AND array inputs for the output terms, 64 latches to store the selection and some more gates to do the latch address decoding. Is there any easy way to choose the right part? Thanks Brian -- Brian Fairchild B dot Fairchild at Dial dot Pipex dot Com "But apart from that Mrs Lincoln, how did you enjoy the play?"Article: 60027
"Nicholas C. Weaver" wrote: > > In article <3F56292C.E9F89B7F@yahoo.com>, > rickman <spamgoeshere4@yahoo.com> wrote: > >"Nicholas C. Weaver" wrote: > >If you don't see the problem it is because you are not looking hard > >enough. The issue with metastability comes from trying to measure the > >state of a FF or other digital voltage. When a signal is at an > >intermediate value a measurement can be inconclusive. Your ANALOG FF > >can be just as inconclusive as the digital FF. Besides, the result is > >always digital (or more accurately, discreet instead of continuous). > > > >You are suggesting that you add a third state to the measurement, but > >you get the same inconclusive measurement between the metastable state > >and either the one or the zero states. The result is that the output of > >your ANALOG FF would be indeterminate which could result in > >metastability in the next stage. > > > >If I am not grasping your idea, then please provide more details. > > The flip flop core exists in one of THREE states: Vdd, Vss (the stable > points) and Vms +/- epsilon (the metastable range, in between Vdd and > Vss). > > The analog circuitry in the flip flop measures the flip-flop state at > Tdelay after the clock edge. > > If it is within Vms +/- a large epsilon (that is, metastable at this > point in time), the analog circuitry forces the flip-flop to Vss, and > also signals that a metastable capture/correction was performed. > > This may cause a spurrious transition (eg, the metastable state is > measured, it goes high, and then the post-measurement kick drags it > back down to Vss). You are not accounting for the fact that the voltage is being measured by the analog circuit and it can not distinguish between the metastable state and the non-metastable states any better than the original FF could distinguish the two valid states. If the voltage is at the cusp of the metastable range, the analog circuit will have an invalid or indeterminate output and will not drive the FF to a valid state. In fact, it may drive the FF back toward a state with an even longer transistion time. This is very circular. Each measurement has a range in which the measurement is indeterminate within a given amout of time. That is the nature of metastability. It is not just the state of the FF. The FF became metastable because it could not measure the input to be either a 1 or a 0. Trying to measure the state of the FF has the same problem, ad infinitum. > >> The trick with asynchronous logic is that the longest stage WHICH IS > >> IN THE COMPUTATION is the critical path. EG, if 9 of the stages take > >> 1 ns, and the last takes 2ns, but the last only affects 1/2 the data, > >> with the asynchronous circuitry doing the shortcutting, it will be > >> considerably faster than the synchronous one. > > > >Except that sync designs can do the same thing. A multiply accumulate > >typically takes twice as long as the other ops in a calculation. So > >they split it into two stages running at full speed. Or if only half > >the data needs the MAC, then they can do nothing since this will run at > >full speed. > > The promise of the asynchronous is that this can occur on a much finer > grain, eg if all the ops are 1 ns, but the final one is either 1 or > 1.5 ns. > > Of couse, it has never really lived up to this promise, mostly because > the handshaking overhead can be severe, as well as the other problems > (CAD, testing). > -- > Nicholas C. Weaver nweaver@cs.berkeley.edu -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 60028
The problem is with your three level "analog ff", instead of one metastable
region, you now have two, one at each side of your middle state. All it
accomplishes is a redistribution of the metastable state at a cost of
considerably more complexity. It doesn't fix anything at all. As rickman and
others have stated, it comes down to a fundamental limitation in measuring a
quantity. Measurement takes a finite amount of time to do. If the transition
happens within that measurement window, you have a metastable event, which is
to say the measurement was indeterminate. Works for digital logic, works for
electron spins and so on. If you really believe you have a work-around, then
you should publish it. Be prepared to nurture your wounds though. The paths
to the holy metastability grail is littered with bloodied bodies, many of whom
have followed the same trail you are considering.
"Nicholas C. Weaver" wrote:
> In article <3F56292C.E9F89B7F@yahoo.com>,
> rickman <spamgoeshere4@yahoo.com> wrote:
> >"Nicholas C. Weaver" wrote:
> >If you don't see the problem it is because you are not looking hard
> >enough. The issue with metastability comes from trying to measure the
> >state of a FF or other digital voltage. When a signal is at an
> >intermediate value a measurement can be inconclusive. Your ANALOG FF
> >can be just as inconclusive as the digital FF. Besides, the result is
> >always digital (or more accurately, discreet instead of continuous).
> >
> >You are suggesting that you add a third state to the measurement, but
> >you get the same inconclusive measurement between the metastable state
> >and either the one or the zero states. The result is that the output of
> >your ANALOG FF would be indeterminate which could result in
> >metastability in the next stage.
> >
> >If I am not grasping your idea, then please provide more details.
>
> The flip flop core exists in one of THREE states: Vdd, Vss (the stable
> points) and Vms +/- epsilon (the metastable range, in between Vdd and
> Vss).
>
> The analog circuitry in the flip flop measures the flip-flop state at
> Tdelay after the clock edge.
>
> If it is within Vms +/- a large epsilon (that is, metastable at this
> point in time), the analog circuitry forces the flip-flop to Vss, and
> also signals that a metastable capture/correction was performed.
>
> This may cause a spurrious transition (eg, the metastable state is
> measured, it goes high, and then the post-measurement kick drags it
> back down to Vss).
>
> >> The trick with asynchronous logic is that the longest stage WHICH IS
> >> IN THE COMPUTATION is the critical path. EG, if 9 of the stages take
> >> 1 ns, and the last takes 2ns, but the last only affects 1/2 the data,
> >> with the asynchronous circuitry doing the shortcutting, it will be
> >> considerably faster than the synchronous one.
> >
> >Except that sync designs can do the same thing. A multiply accumulate
> >typically takes twice as long as the other ops in a calculation. So
> >they split it into two stages running at full speed. Or if only half
> >the data needs the MAC, then they can do nothing since this will run at
> >full speed.
>
> The promise of the asynchronous is that this can occur on a much finer
> grain, eg if all the ops are 1 ns, but the final one is either 1 or
> 1.5 ns.
>
> Of couse, it has never really lived up to this promise, mostly because
> the handshaking overhead can be severe, as well as the other problems
> (CAD, testing).
> --
> Nicholas C. Weaver nweaver@cs.berkeley.edu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 60029Hi Dan, > Is Xilinx planning on contributing their Microblaze port > back to the GCC project, i.e. have they executed a copyright > assignment so upcoming versions of gcc can supprt Microblaze > out-of-the-box? I'm not sure. > I ask partly because I'm wondering if it's worth folding Microblaze > support into my generic toolchain build script > (http://kegel.com/crosstool) or PTXDist. To do so would be very useful for the microblaze / uClinux community, since currently we are unable to build our own toolchains, and are somewhat reliant on Xilinx for that. We have the source, but aren't really able to build it yet. > This would be somewhat difficult > Microblaze used a special hacked version of gcc... I don't think there's anything too radical in there, but I'm not a gcc expert by any means. Regards, JohnArticle: 60030
There was an open source project called "Camille", which was intended to replace Mentor's "Renoir". But I haven't heard anything of it for some time. Jay <se10110@yahoo.com> wrote: :Ok, : :This is slightly off-topic but what do people in here use to create :their digital logic block diagrams? : :I am hopefully looking for something that runs on Win2000, but I'd :consider Linux/FreeBSD alternatives. : :Currently I am using "SmartDraw" (www.smartdraw.com) but I find my block :digrams look messy and it's not easy to "rubber band" things like clock :signals. I sometimes like to place text in a block (i.e. "Counter") but :also like to leave room for connections like a clock triangle (>) and :text for EN(able) but when I'm finished the results aren't appealing. : :I've also used Edge Diagrammer (from Pacesoft) and found it was "weird" :in many respects. : :Both Edge and SmartDraw are annoying in one particular aspect; if a line :is "attached" to an object, when the object is moved, instead of using :right-angles to re-draw the lines, the connecting line is put at an :angle. : :I know a lot of people in general use Visio, what is considered the :best, most lean version of Visio? I loathe Office and especially :anything beyond Office '97. : :I'm also interested to hear if anyone uses Kivo/Kivo MP. : :Thanks! :Jay.Article: 60031
"Hal Murray" <hmurray@suespammers.org> wrote in message news:vlc0kv1m4flm5f@corp.supernews.com... > >Silly question: I don't see why an ANALOG flip-flop couldn't determine > >that it is in the intermediate state at some fixed interval after the > >clock, and then force the flop one way or another. Of course, it > >might double-glitch in the meantime (flop goes up before logic forces > >it down), but it would make a flop with a fixed-maximum metastabel > >interval. > > DING DING DING > > Nobody has been able to fix metastability yet. If you really have > a fix, it's worth a Nobel Prize. It might be that you can change the shape of the probability vs. time curve, while keeping the area constant. That could reduce the probability of metastability lasting too long for a given clock rate. I don't know the physics well enough to say. Also, it might be pretty expensive to do that. -- glenArticle: 60032
>This isn't FIXING metastability, this is detecting and responding to >it, changing an exponentially decaying bounds into a fixed bounds. If you could build a circuit with a "fixed bounds", that would solve the metastability problem and you would be a hero. (Just set your clock period to that fixed bounds.) I put metastability in the same category as perpetual motion. I assume any proposal is wrong, even if I can't spot the problem right away. Best one I've ever heard of was a bicycle wheel that ran off changes in air pressure. >Yes, but the point is it would fix the maximum metastability window, >which is the key requirement, as "did the data come before or after >the clock edge" is really an irrelevant question at the metastable >capture point, you jsut want it to go to ONE or the other (not stick >around and make up its mind a half clock cycle later), and possibly to >tell you. If you have a circuit that you think will work, please send me the schematic. There is a reasonable chance I (or somebody here) can find the bug in it. No promises. The thing I would look for is runt pulses. The best non EE-geek example of metastability I have seen is rolling a ball over a speed bump. Left of the bump is 0. Right of it is 1. Give it a good shove and it goes over. Give it a gentle shove and it bounces back. For some speed, the ball will teeter on the top for a while, then fall off one side or the other. The initial speed of the ball corresponds to meeting setup/hold times. If the system is continuous, there is some value in the middle that will cause troubles. Setup/hold times and ball speed both seem continuous to me. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 60033
Why don't you just tell it to ignore these? -- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu" "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:bj54ns$7nr$1@home.itg.ti.com... > I found a workaround. If I add a new UCF, it seems like the old one gets > updated with the new design (with missing ports). I just add a new UCF, > delete it right away, and work with the old one. > David > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > news:bj547c$6pr$1@home.itg.ti.com... > > Hi, > > I have a vhdl project and I used a UCF file to assign the package pin to > > each port in the design. This works fine. However, if I change my vhdl > code > > (let's say I remove an output port), I always get the following error when > I > > try to run the UCF editor: > > ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s) > > 'outputA' in the design. To suppress this error specify the correct > net > > name or remove the constraint. > > > > It seems like the UCF doesn't update itself with the new design. I tried > > everything and I always have to start with a new UCF each time. The > removed > > port doesn't exist in the Edit constraints (TEXT) because I didn't add any > > constraint to it. I really don't see how to do it. > > Thanks > > David > > > > > >Article: 60034
peterzhu wrote: >Due to a chip bug, I have to extend a pulse width(negative)from 10ns >to 100ms in CPLD(Altera 7128). But the difficult is that I have no any >clock into the CPLD, so the CPLD is pure combination logic. how to >extend it in such case? > >Help me! > > I have delayed strobe signals several hundred nS with an external series resistor, and used the input capacitance of the chip as the C of the RC network. For mS, you will need an external capacitor, of course. if you want the delay to be asymmetric (like a one-shot), you might need to put a diode in parallel with the R. You feed the signal out one pin, through a series R, to a pin loaded with a cap to ground, and then take the signal in from that pin. This may cause multiple pulses with a delay this long, however. So, you might end up using a 74HC4538 or similar one shot, or a 74HC14 Schmitt trigger to prevent the pulses as the output of the RC crosses the threshold. JonArticle: 60035
Jay <se10110@yahoo.com> wrote in message news:<MPG.19bf56e7871d6a089896dc@news.surfcity.net>... > Ok, > > This is slightly off-topic but what do people in here use to create > their digital logic block diagrams? > > I am hopefully looking for something that runs on Win2000, but I'd > consider Linux/FreeBSD alternatives. > > Currently I am using "SmartDraw" (www.smartdraw.com) but I find my block > digrams look messy and it's not easy to "rubber band" things like clock > signals. I sometimes like to place text in a block (i.e. "Counter") but > also like to leave room for connections like a clock triangle (>) and > text for EN(able) but when I'm finished the results aren't appealing. > > I've also used Edge Diagrammer (from Pacesoft) and found it was "weird" > in many respects. > > Both Edge and SmartDraw are annoying in one particular aspect; if a line > is "attached" to an object, when the object is moved, instead of using > right-angles to re-draw the lines, the connecting line is put at an > angle. > > I know a lot of people in general use Visio, what is considered the > best, most lean version of Visio? I loathe Office and especially > anything beyond Office '97. > > I'm also interested to hear if anyone uses Kivo/Kivo MP. > > Thanks! > Jay. I use Visio 5 Technical (last version before Visio was bought by MS). It is great for all H/W design documentation - I even use it to draw waveforms when designing interfaces. Unlike applications designed specifically to draw waveforms, it allows to violate timing without constatly yelling at me. I've tried to use Visio 2000, but MS had slowed it down and screwed about with the UI; it may be more office-compatible, but it is far less me-compatible. I will stay with Visio 5 until I leave Windows (I use Win2K and have no plans to ever switch to any later Windows version; I'll switch to Linux before using WinXP and its "cute & friendly" UI).Article: 60036
Due to a chip bug, I have to extend a pulse width(negative)from 10ns to 100ms in CPLD(Altera 7128). But the difficult is that I have no any clock into the CPLD, so the CPLD is pure combination logic. how to extend it in such case? Help me!Article: 60037
I have spent some time to study this patent and, to be honest, I have not found much innovation at all. I might have missed something, but this seems a standard 2-D FFT implemented as a 1-D row (column) FFT followed by N 1-D column (row) transforms. The memory requirement for the column transforms is of N words for each transform for a total of N^2. This makes the architecture quite impractical for an FPGA implementation of large size transform. The basic block seems to be related to the sliding 1-D FFT, which has complexity N instead of N log(N). This would reduce the complexity of the 2-D FFT from N^2 log(N) to N^2. (I am using the conditional since I have not spent much time on this.) I have seen very few references in the literature to the sliding FFT; if anyone is interested I can send the copy of an IEEE paper about it. Any other comments? -ArrigoArticle: 60038
"Hal Murray" <hmurray@suespammers.org> wrote in message news:vld55e7r7pvj2e@corp.supernews.com... > >This isn't FIXING metastability, this is detecting and responding to > >it, changing an exponentially decaying bounds into a fixed bounds. > > If you could build a circuit with a "fixed bounds", that would solve > the metastability problem and you would be a hero. (Just set your > clock period to that fixed bounds.) (snip) > If you have a circuit that you think will work, please send me > the schematic. There is a reasonable chance I (or somebody here) > can find the bug in it. No promises. The thing I would look for is > runt pulses. > > The best non EE-geek example of metastability I have seen is > rolling a ball over a speed bump. Left of the bump is 0. Right of > it is 1. Give it a good shove and it goes over. Give it a gentle > shove and it bounces back. For some speed, the ball will teeter on > the top for a while, then fall off one side or the other. > > The initial speed of the ball corresponds to meeting setup/hold times. > If the system is continuous, there is some value in the middle that will > cause troubles. Setup/hold times and ball speed both seem continuous > to me. One thing that I still remember from the first discussions about metastability was that the sharper you make the peak, the smaller the chance of getting into the metastable state, but the longer it stays when you get there. I don't know if the analogy is quite right, but consider a very sharp speed bump. It will deform the ball as it goes over, such that it sticks more. Not so long after that, I was taking a shower at a pool with a valve designed not to stay on. I managed to get it into the metastable (stay on) state, so that I could wash with both hands. (It worked just like the speed bump, where on top of the bump the valve was on.) -- glenArticle: 60039
Hello, has anyone already used a Spartan IIe DLL (PLL) to extract the clock out of a 100MBit/s 8B10B encoded data stream ? Will that work with a Spartan III DCM? Thank you, ThomasArticle: 60040
When I add an interrupt controller to my design I get the following error
when I try to generate libraries:
What does this error mean???
opb_intc (opb_intc_0) -
C:\EDK\hw\iplib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_0_0.mpd:30 -
overriding
C_KIND_OF_EDGE value 11111111111111111111111111111111 to
00000000000000000000000000000000
opb_intc (opb_intc_0) -
C:\EDK\hw\iplib\pcores\opb_intc_v1_00_c\data\opb_intc_v2_0_0.mpd:31 -
overriding
C_KIND_OF_LVL value 11111111111111111111111111111111 to
00000000000000000000000000000001
lmb_v10 (lmb_v10_0) -
C:\EDK\hw\iplib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_0_0.mpd:21 -
overriding
C_LMB_NUM_SLAVES value 4 to 1
lmb_v10 (lmb_v10_1) -
C:\EDK\hw\iplib\pcores\lmb_v10_v1_00_a\data\lmb_v10_v2_0_0.mpd:21 -
overriding
C_LMB_NUM_SLAVES value 4 to 1
opb_v20 (opb_v20_0) -
C:\EDK\hw\iplib\pcores\opb_v20_v1_10_a\data\opb_v20_v2_0_0.mpd:35 -
overriding
C_NUM_MASTERS value 4 to 1
opb_v20 (opb_v20_0) -
C:\EDK\hw\iplib\pcores\opb_v20_v1_10_a\data\opb_v20_v2_0_0.mpd:36 -
overriding
C_NUM_SLAVES value 4 to 3
Checking platform address map...
Verifying Bus Interfaces ...
Checking platform configuration ...
Building Directory Structure for microblaze_0
Checking Processor Rules for microblaze_0
Generating platform libraries and device drivers ...
Copying Library Files ...
Copying BSP Files ...
Running CopyFiles ...
Running DRCs for Drivers and Libraries ...
Running generate for Drivers and Libraries ...
ERROR:MDT - xget_value : A NULL handle was provided
while executing
"xget_value $source_port "NAME""
(procedure "generate" line 48)
invoked from within
"generate 1490864"
Tcl File cpu_v2_1_0.tcl
ERROR:MDT - Error while running "generate" for processor microblaze_0...
make: *** [microblaze_0/lib/libxil.a] Error 2
Done.
Article: 60041Austin Lesea wrote: > > Symon, > > A long time ago, I designed a timing system for telecom that used a rubidium clock. The > reason why this is interesting will become apparent in a moment. > > One function of the system was to measure up to five external sync references (presumably > from traffic bearing lines from other offices). > > The circuit to do this was basically a counter, that was sampled by a rubidium derived > clock. All clocks were syntonous (same frequency, arbitray phase -- aka the SONET/SDH > telepone network). As the phase wandered back and forth, the metastable regions would get > exercised, and the measurement board would report that an input signal had arbitrarily > "slipped" by some random number of bits (due to a metastable transistion of a bit in the > counter/latch). > > This was so frustrating, because in real life, the inputs could slip due to failures, > glitches in the network, etc. So how do you know a real bad slip, from a metastable one? > > In the hope (vain and useless) of reducing the occurence of the metastable sample, we had > three levels of FFs to try to re-synchronize the sample count, along with an elaborate set > of clock enables. We got it to the point where the false slip occurred about evey two > months, in a typical network. Since real outages were far more common, it was not a big > deal. > > In spite of this, we wrote software to identify a real slip, from a false slip. Basically, > if five successive samples were not equal (as the phase can't change that fast) we threw out > that set of measurements, and took another five. This dropped the occurence of a false slip > to below the threshold that we could measure (but it could still happen and probably did - > still does out there somewhere). > > So, metastability can sometimes be beaten into submission, but it never goes away.... > > The ultimate frustration is that one of these references gets used to track the rubidium > (steer it in a phase lockeed loop), so a fake glitch can cause quite a hit, which then > causes slips throughout the network as the rubidium runs off the the "wrong" > frequency/phase. A real glitch can also cause the same behavior, so the locked loop is > quite loosely coupled, and before each update, one checks absolutely everything to be sure > that what you are trying to track is real.... > > I had heard there were some cases with equipment designed by others where the maintenance > folks would just disconnect the inputs, as the bare rubidium ran so clean, that it was > better to not track at all (fewer slips) than to bother with trying to track the references > and falsely running off into the weeds due to metastability and poor reference checking. > > All of this became obsolete when GPS became available, as now precise time (frequency) was > broadcast for free. Very interesting account - worth adding to the FAQ under metastable ? -jgArticle: 60042
Hello Brian, Take a look at these: http://www.digilentinc.com/Catalog/digilab_2e.html http://www.digilentinc.com/Catalog/peripheral_boards.html To start experimenting you'll need a System Board and one of the peripheral boards. The Spartan2e on this board has 200K gates, for your design it should be way too big... to give you an idea of what you can get into it, take a look at the list of applications they give at the Xilinx ip center. Good luck Yves Brian Fairchild wrote: > Hi > > I'm an embedded systems designer who feels that it's about time he > started to learn about using FPGAs. I'm happy using PLDs, designed in > something like CUPL but don't know where to start on bigger devices. > > I only have a small budget for development tools and I'm in the UK. > > From what I can see my best choice of manufacturer is probably down to > Xilinx or Altera. > > Can anyone suggest an evaluation board that would get me started? > > I see that devices are sold in terms of their gate count. How > efficient is a typical design? For instance, if I want to make a 16 by > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > see that I need 16 OR gates each with 16 AND array inputs for the > output terms, 64 latches to store the selection and some more gates to > do the latch address decoding. Is there any easy way to choose the > right part? > > Thanks > > Brian >Article: 60043
Hi, Can anyone recommmend some NVRAM or parallel EEPROM to interface with Spartan2 device.Article: 60044
Brian Fairchild wrote: Hi Brian, > I'm an embedded systems designer who feels that it's about time he > started to learn about using FPGAs. I'm happy using PLDs, designed in > something like CUPL but don't know where to start on bigger devices. > > I only have a small budget for development tools and I'm in the UK. > > From what I can see my best choice of manufacturer is probably down to > Xilinx or Altera. > > Can anyone suggest an evaluation board that would get me started? You might have a look at http://www.silica.com/eval_kits/index.html There are some good evaluation boards that are not so expensive. > I see that devices are sold in terms of their gate count. How > efficient is a typical design? For instance, if I want to make a 16 by > 16 CPU controlled crosspoint how many FPGA gates will I need? I can > see that I need 16 OR gates each with 16 AND array inputs for the > output terms, 64 latches to store the selection and some more gates to > do the latch address decoding. Is there any easy way to choose the > right part? That is very difficult to answer. This issue has been discussed sometimes in this newsgroup already, and will probably be discussed again and again. You should never ever draw some conclusions from the gate-count given by the manufacturers. This is just a marketing number. I started with Lucent (now Lattice) ORCA FPGAs and got a feeling what can be put inside. Then I turned to Xilinx Virtex FPGAs (because of the free development software) and got rather shocked how much less one can put into such an FPGA with a comparable gate count. For instance, they include internal RAM-Blocks in the official gate-count number. That gives a shiny value, but is nonsense if you ask me. My guess is that the Xilinx people that are around here in this newsgroup think similar because they are more engineers rather than marketing people. But apart from that, the Xilinx FPGAs are not bad ones. Instead, have a look at the building blocks, see what they provide and how much of them are available and then draw conclusions whether it is sufficient for your design. And when you made some designs for a specific FPGA series, you will soon develop a feeling which array size could be appropriate for which problem. Once you got some design software, you might also try to synthesize your design (provided it has been finished already) and try to fit it into different FPGA types. There you will also see how much of the FPGAs' capacity would be used. Regards, MarioArticle: 60045
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F55FE76.532A72CE@xilinx.com>... > Luiz, > > Last things first, the LVTTL input does not use the comparator(s) (there are > three different comparators, as well as other ciruits for the various input > standards). > > The comparator is designed to have a relatively high gain, so that it > switches quickly. > > As I said, the offset voltage is due to the Vt mismatch on the pmos and nmos > diff pairs, and since these are built with .35u (VII) or .25u (VII Pro) > transistors, they are pretty darn fast diff-amps. There is a classic gain > stage after the cmos diff-amp (similar to the ones in "CMOS Circuit Design, > Layout & Simulation" by Baker, Li, and Boyce). The offset voltage is > typically less than a few 10's of mV (say 10 to 20 mV worst case). I am sure > that if you vary the voltage difference slowly enough, you could measure the > gain of the diff-amp. It was designed for HSTL and SSTL IO standards, which > as someone already pointed out, are pretty sloppy. What I will point out > here, is that I am not aware of any monolithic separate comparator that is as > fast as the one that is in the input circuit. This comparator is good for > 400 Mbs+ speeds, which is a lot faster than most separate IC comparators.... > > Austin Thankyou Austin. I'm thinking of using this internal comparator for a Delta-Sigma ADC. Luiz Carlos.Article: 60046
>Hi, <p>Can anyone recommmend some NVRAM or parallel EEPROM to interface with Spartan2 device. Look at Xilinx Site : http://www.xilinx.com/isp/compfpgatables/prom_spartan.htm Best Regards, PeterArticle: 60047
Metastability occurs when we don't respect setup and/or hold times. But what does happen when the input for the flip-flop is a DC signal between Vil and Vih? (Or it changes so slowly that looks like a constant.) My guess is there is a voltage, let's say Vth, that: If Vin < Vth => DOUT = 0 after a delay If Vin > Vth => DOUT = 1 after a delay The delay grows as Vin approximates to Vth. Am I right? Luiz CarlosArticle: 60048
Hallo David, i also had this problem. My workaround is to delete the removed ports manually from the ucf-file by using "Edit Constaints(Text)" from theProcesses-Window. This works fine and is fast. best regards Thomas Oehme "David Lamb" <gretzteam_nospam@yahoo.com> schrieb im Newsbeitrag news:bj547c$6pr$1@home.itg.ti.com... > Hi, > I have a vhdl project and I used a UCF file to assign the package pin to > each port in the design. This works fine. However, if I change my vhdl code > (let's say I remove an output port), I always get the following error when I > try to run the UCF editor: > ERROR:NgdBuild:756 - Line 3 in 'constraints.ucf': Could not find net(s) > 'outputA' in the design. To suppress this error specify the correct net > name or remove the constraint. > > It seems like the UCF doesn't update itself with the new design. I tried > everything and I always have to start with a new UCF each time. The removed > port doesn't exist in the Edit constraints (TEXT) because I didn't add any > constraint to it. I really don't see how to do it. > Thanks > David > >Article: 60049
> But the measurement is not instantaneous. So the transistion could > occur during a measurement. Result... inconclusive measurement which is > what metastability is all about. You just need to measure the spins to see the results. You can maintain they stable during this. To carry out the operations the spins interact and you don't need to measure them. But, if you imply a measure in the interaction process, so the measure is instantaneous. Luiz Carlos
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