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Messages from 65750

Article: 65750
Subject: Re: European supplier of Xilinx chips
From: Ryan Laity <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com>
Date: Thu, 05 Feb 2004 15:47:25 -0700
Links: << >>  << T >>  << A >>
Thomas,

This information may also help:
http://www.xilinx.com/company/sales/ww_disti.htm

Ryan Laity
Xilinx Applications

Amontec Team, Laurent Gauch wrote:
> Thomas Womack wrote:
> 
>> There seems to be exactly one supplier of reasonably modern (Virtex II
>> or Spartan II) chips who's prepared to give pricing, and it's plis.ru
>> in Russia.  Farnham only have chips so old they don't appear on the
>> http://www.xilinx.com/products/tables/fpga.htm page.
>>
>> Are plis.ru good people to deal with?  Or am I missing something
>> obvious?  arrow.com have transparent pricing for EP1C and EP1S chips
>> from Altera, but don't have any parts with number XC2*
>>
>> Tom
> 
> 
> for european supplier, try www.memec.com or www.avnet.com !
> for online xilinx pricing try www.nuhorizons.com !
> 
> larry
> www.amontec.com
> 
> 


Article: 65751
Subject: Re: Reconfiguring at runtime internally?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Thu, 5 Feb 2004 15:10:44 -0800
Links: << >>  << T >>  << A >>
Just a clarification -- the Internal Configuration Access Port (ICAP) is
available on some Xilinx FPGAs to aid reconfiguration from within the
device.  However, devices without ICAP can still be partially reconfigured
from internal logic.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

"PO Laprise" <pl_N0SP4M_apri@cim._N0SP4M_mcgill.ca> wrote in message
news:uIxUb.14696$2g.2179@charlie.risq.qc.ca...
> Miguel Silva wrote:
> > Virtex II and Virtex II Pro allow internal reconfiguration through the
ICAP
> > module, the application note XAPP662 as an example that shows how this
could be
> > done
>
> I remember a discussion on this newsgroup a while back touching ICAP and
> its performance.  I believe it was triggered by the fact that ICAP would
> not be in the Spartan3 chips.  You might want to check the archives...
>
> -- 
> Pierre-Olivier
>
> -- to email me directly, remove all _N0SP4M_ from my address --
>



Article: 65752
Subject: Re: European supplier of Xilinx chips
From: Thomas Womack <twomack@chiark.greenend.org.uk>
Date: 05 Feb 2004 23:33:13 +0000 (GMT)
Links: << >>  << T >>  << A >>
In article <4022C7FD.7020008@x-i-l-i-n-x_pleasenospam_dot_com>,
Ryan Laity  <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote:
>Thomas,
>
>This information may also help:
>http://www.xilinx.com/company/sales/ww_disti.htm

I'm probably being unreasonable in expecting electronics distributors
to have sites like Amazon, but the only distributor on that page with
a Web site is Memec, and Memec requires you to burrow three layers
deep for a part-number search, which then returns no results for
something obvious like XC2VP7.

avnet.com seems much better.  nuhorizons.com has a decent search
interface but seems rather like Monty Python's cheese shop -- almost
every query comes up with dozens of responses, all with no stock.

Tom

Article: 65753
Subject: Re: Do Xilinx Fix Their Prices?
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Thu, 5 Feb 2004 23:43:57 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <4022ACEF.80E375D4@xilinx.com>, Peter Alfke wrote:
> The IC business is not so much different from other businesses.

Well, not many other businesses see their products' performance/cost
increase exponentially with time.

[ snip lots of stuff I actually agree with.  ;-) ]

> Once a specific device has been in production a few years, there is
> little chance to lower its manufacturing cost, once the ramp-up problems
> are overcome, the yield has been stabilized and the testing effort has
> been optimized.

I don't doubt this is true, but it only covers the supply half
of the equation.  You also have to look at the demand side,
because if a successful business model demanded cost reductions,
that could probably be arranged on the supply side.

Once an FPGA has been designed into a circuit, engineering
costs of changing to a different part are high (and has non-zero
risk -- management hates that!).  This is a natural form of
"lock-in", or monopoly.  So, without multi-vendor competition
for an existing chip footprint, and prices _can_ stay unnaturally
"high" (or in this case, not drop).

Where competition does kick in is for _new_ designs, which
(duh) involve _new_ parts.  Here the competition is, as Peter
wrote, fierce.  "Design wins" are a very big deal to both brand
A and X.  After a brief period of (they hope) high volume, 
high profile success -- part of which is leading-edge cost
effectiveness from the buyer's perspective -- the business system
settles down to the operating scenario of the previous paragraph.

So the fundamental difference between FPGAs and, say, SRAM
(that leads to the effect that Steve noted and found unnatural),
is the lack of cross-vendor competition for pin-compatible parts.

    - Larry

Article: 65754
Subject: Re: Quartus II and Synthesis
From: sdatta@altera.com (Subroto Datta)
Date: 5 Feb 2004 15:56:51 -0800
Links: << >>  << T >>  << A >>
johnnynorthener@yahoo.co.uk (JohhnyNorthener) wrote in message news:<95e91aaf.0402040328.9824e88@posting.google.com>...
> Any advice please.
> 
> I am creating a parallel uP interface to my fpga and i have separate
> 'processes' for the read and write functions.  My question is : Will
> quartus synthesise separate address decoders - one for the read and
> one for the write, or is it 'clever' enough to munge the two together
> in the same decoder when synthesising ? (not sure of the tech term but
> is this resource sharing ?)
> Any help will be much appreciated

Quartus II 4.0 (which is in manufacturing as I write this) has this
option. It is called Auto Resource Sharing and needs to be turned on.
The default value is off. This option is accessed through the
Assignment->Settings->Analysis & Synthesis Settings->More Settings
dialog.

The help for this option says:
"Allows the Compiler to share hardware resources among many similar,
but mutually exclusive, operations in your HDL source code. If you
enable this option, the Compiler will merge compatible addition,
subtraction, and multiplication operations. By merging operations,
this may reduce the area required by your design. Because resource
sharing introduces extra muxing and control logic on each shared
resource, it may negatively impact the final fmax of your design."

- Subroto Datta
Altera Corp.

Article: 65755
Subject: Update: Open source ARM, Version 0.4
From: eiselekd@web.de (Konrad Eisele)
Date: 5 Feb 2004 16:04:35 -0800
Links: << >>  << T >>  << A >>
Update: version_0.4 of the not yet finished 
synthesizable vhdl ARM model is ready. Slowly but 
shurely we aproach a working version. First full 
release is now sheduled for March.
snap: http://www.tamaki.de/data/vhdl.tar.gz
Implemented as a Integer Unit in Gaisler Research's
Leon-Soc. Check the <leon_basedir>/leon/armxxx.vhd 
files.
 
Note: Because I do not really know the licensing
situation, download at your own risk. License file:
http://www.tamaki.de/data/License.txt

Article: 65756
Subject: Re: Reconfiguring at runtime internally?
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Fri, 06 Feb 2004 11:39:55 +1000
Links: << >>  << T >>  << A >>
Steven K. Knapp wrote:
> Just a clarification -- the Internal Configuration Access Port (ICAP) is
> available on some Xilinx FPGAs to aid reconfiguration from within the
> device.  However, devices without ICAP can still be partially reconfigured
> from internal logic.

Did you mean to write "from external logic"?

There's also another way it could be done, for non-ICAP devices. 
Basically just feed some user IO back into the external SelectMAP pins, 
and create bitstreams with the -g Persist:yes option to keep the 
selectMAP interface alive after configuration.

Your self-reconfig core then drives those user pins (and thus the 
selectMAP interface) as required.

This costs a few pins and requires planning at the board design stage, 
but if you need self-reconfig that badly in a non-ICAP device, then it 
seems a feasible approach.  Have I missed anything?

Regards,

John


Article: 65757
Subject: Re: ByteBlaster fails on Windows 98
From: sesh67@yahoo.com (sesh67)
Date: 5 Feb 2004 17:48:19 -0800
Links: << >>  << T >>  << A >>
"Cameron, Charles B. " <cameronc@aplcenmp.apl.jhu.edu> wrote in message news:<401FA202.5050300@aplcenmp.apl.jhu.edu>...
> Yuri Tregubov wrote:
> 
> > Dear colleagues,
> > 
> > The ByteBlaster works fine with MaxPlus 9.4 / Windows 95 but fails
> > with MaxPlus 10.2 / Windows 98.
> > 
> > "Unrecognized device or socket is empty"
> > 
> > Any clue ?
> > 
> > Nordic regards,
> > Yuri
> There is a new driver, the ByteBlaster II, which I found I needed for MaxPlus 10.2 on Windows 2000.  I don't know whether Windows 98 is supported or not.  It was a royal pain to find the driver, install it, and get it working.  There's probably a FAQ somewhere to cover this information step-by-step but I don't know where it is.
> 
> Charles B. Cameron


Check out http://www.altera.com/support/software/drivers/dri-index.html

Seshan
Altera Corp

Article: 65758
Subject: Re: asynchronous counter an Xilinx FPGA for a newbie
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Fri, 06 Feb 2004 03:17:56 GMT
Links: << >>  << T >>  << A >>
Georges Konstantinidis wrote:

> Dear all
> I'm deseprately trying to make an asynchronous counter to count the number
> of inputs I have on a pin. I also want a reset input.
> I copied the last version of my code at this e-mail .
> The synthesis looks good but an error comes at the implementation design. I
> don't kow to to do any more.
> Thank you for fixing my bugs, Georges.

(snip of VHDL code)

If you write it in Verilog I might be able to tell you.

I don't think it looks like an asynchronous (ripple) counter,
though.  It might be that you can't make ripple counters
on the system your synthesis is targeting.

-- glen


Article: 65759
Subject: Symmetric encryption mechanism in smart cards
From: arul_utm@yahoo.com.sg (Arul)
Date: 5 Feb 2004 19:58:58 -0800
Links: << >>  << T >>  << A >>
I would like to know what exactly are the proceses and the sequance
that takes place in the process of data encryption in a processor
smart card. For examples what hardware and software modules are
required and how data is moved around from the beginning to the end of
the process.

Any help and infomation will be most appreciated.

Article: 65760
Subject: Re: How do I fix this type of errors?
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Fri, 6 Feb 2004 12:57:29 +0800
Links: << >>  << T >>  << A >>
Sean:

I removed the MODE, PLACE and GROUP on the fixed module only. My fixed
module cover 80% of the whole chip.
The reconfigurable module still has these "closed" constraints, but they
cover only 20% on the left side of the chip...
I haven't tested them in hardware yet.

#AREA_GROUP "FIXEDMODULE" MODE= RECONFIG;
#AREA_GROUP "FIXEDMODULE" PLACE=CLOSED;
#AREA_GROUP "FIXEDMODULE" GROUP=CLOSED;

Hope this helps...

Kelvin



Sean Durkin <23@iis.42.de> wrote in message news:4021f082$1@news.fhg.de...
> Kelvin @ SG wrote:
> > Sean:
> > I found that at the final assembly stage, when I removed the "Closed"
> > constraint in the Place & Route on the
> > fixed module. And then my design ran without errors.
> Which "closed" constraint do you mean? The "MODE = RECONFIG"-constraint?
> If I remove that, the design flow finishes without a problem, but of
> course the result is unusable, since lots of nets from the fixed module
> cross the module boundary to the reconfigurable module.
>
> --
> Sean Durkin
> Fraunhofer Institute for Integrated Circuits (IIS)
> Am Wolfsmantel 33, 91058 Erlangen, Germany
> http://www.iis.fraunhofer.de
>
> mailto:23@iis.42.de
> ([23 , 42] <=> [durkinsn , fraunhofer])



Article: 65761
Subject: Virtex 2: Partial Bitstream Generation with bitgen -r
From: "Kelvin @ SG" <kelvin8157@hotmail.com>
Date: Fri, 6 Feb 2004 13:26:12 +0800
Links: << >>  << T >>  << A >>
Hi, there:

Does "bitgen -r initial.bit second.ncd" generate correct runtime
reconfiguration bitstreams?

If I am not wrong, even though I followed the modular approach, there was
still slight differences
in the fixed module area between the two assemblies...basically the DCMs and
BUFGMUX...
meaning the difference bitstream might cause problems...

Thanks for your advice...

kelvin










All messages from thread
Message 1 in thread
From: Ryan Fong (rfong@vt.edu)
Subject: Virtex 2: Partial Bitstream Generation

View this article only
Newsgroups: comp.arch.fpga
Date: 2002-04-23 07:50:56 PST

Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i
tools, without using the Modular Design tools?  I am interested in run-time
partial reconfiguration to change areas of an FPGA while keeping others
areas unchanged.

Thanks.

Message 2 in thread
From: Austin Lesea (austin.lesea@xilinx.com)
Subject: Re: Virtex 2: Partial Bitstream Generation

View this article only
Newsgroups: comp.arch.fpga
Date: 2002-04-24 07:46:14 PST

Ryan,

Here is the answer from the expert:

"Hi Austin,
    The -r switch is currently a hidden switch, but it will be visible in
the next major release.  The switch will make bitgen read in an existing
bitstream, and then when the bitstream for the new design is created, only
the frames that
are different between the two bitstreams will be written.

   The -r switch takes a bitstream as an argument.  An example command line
would be:

$ bitgen -w -r old.bit new.ncd

The -r switch is useful if you have a limited number of possible
reconfigurations."



Austin



Ryan Fong wrote:

> Is it possible to generate partial bitstreams using the Xilinx ISE 4.2i
tools, without using the Modular Design tools?  I am interested in run-time
partial reconfiguration to change areas of an FPGA while keeping others
areas unchanged.
>
> Thanks.

Message 3 in thread
From: Martin Subject: Re: Virtex 2: Partial Bitstream Generation

View this article only
Newsgroups: comp.arch.fpga
Date: 2002-05-07 08:02:44 PST

Hi Ryan,

brief answer: No, you can't.

The partial reconfiguration flow is a subset of the Modular Design flow. For
each of the reconfiguration-modules you need to run the implementation on
the single module. After you have the implementation data for each module
you'll need to stitch the files together and create the initial and partial
bitstreams. The latter one can be done either by comparing the bitstreams
which each other and creating small bit-streams with only the differences or
you can create the re-configuration bitstream from the
floorplanning-information.

From the timing point of view you can save yourself quite some time for the
re-configuration of the device.
I did a test once with a Virtex-E 600 and a MultiLINX Cable on the serial
port (slowest BAUD-rate). The complete configuration took about 1.5 minutes.
Re-configuration with a small bit-stream took about 8 seconds. As you can
see there can be quite a difference in configuration time.
(BTW: Normal Configuration via MultiLINX and USB took about 13 seconds,
re-configuration was only a glimpse.)

but as you can surely imagine, the time for re-configuration is very
dependend on the changes you are doing. If you are only doing minor changes
re-configuration will be quicker than if you'd do major changes.

Martin


2004 Google



Article: 65762
Subject: How may I restrain the P&R to only a small area...
From: "Tungsten-W" <kelvin8157@hotmail.com>
Date: Fri, 6 Feb 2004 14:04:55 +0800
Links: << >>  << T >>  << A >>
Hi, there:

I am doing a design which only covers 10% of the slices...but after P&R, it
spreaded all over the FPGA.
How may I constrain it into, say, one corner...

How may I "nail down the logic into a known location"(Somebody told me this
trick)?

BTW, I am doing reconfigurable design, so the AREA_GROUP constraints can't
be used...

Kelvin




Article: 65763
Subject: Re: Xilinx PAD name to (X,Y) RPM coordinate
From: "CyberFunk" <htchang@comcast.net>
Date: Fri, 06 Feb 2004 07:09:49 GMT
Links: << >>  << T >>  << A >>
Thanks for the reply.
But the XY coordinate printed out by partgen doesn't match with
EPIC's RPM grid shown when I click the pad.  Is it partgen software bug?
Is there anyone representing Xilinx can answer this question?
Thanks.

"John Williams" <jwilliams@itee.uq.edu.au> wrote in message
news:40222fe9$0$10532$61ce578d@news.syd.swiftdsl.com.au...
> CyberFunk wrote:
> > Hi there,
> > Is there any way to convert PAD name (package pin name) to
> > (X,Y) RPM coordinate used in Xilinx FPGA editor.
> > TIA
>
> Try running "partgen -v partname"
>
> where partname is, e.g. cx2v1000-fg456-4
>
> then open up the partname.pkg file.
> For example, from xc2v1000-fg456-4.pkg: (watch the wrap)
>
> pin     PAD1         B4        0   IO_L01N_0              X1Y79     0S
>         0
> pin     PAD2         A4        0   IO_L01P_0              X1Y79     0M
>         0
> pin     PAD3         C4        0   IO_L02N_0              X1Y79     1S
>         0
>
> Thus pin B4 is located at slice X1Y79, and so on..
>
> You could look at the part in FPGA editor to confirm.
>
> Regards,
>
> John



Article: 65764
(removed)


Article: 65765
(removed)


Article: 65766
Subject: project navigator fails to detect inputs to the module
From: hashmi1947@yahoo.com (Atif Hashmi)
Date: 5 Feb 2004 23:12:35 -0800
Links: << >>  << T >>  << A >>
Dear All,
I have recently started fpga programming. The problem I am facing is
that I have made a module that has certain inputs but these inputs are
not detected by the project navigaor i.e they dont appear in the
constraint file automatically and when I try to connect them to an
output by using
    NET "input" LOC = "P85";

Project Navigator gives an Error 
ERROR:NgdBuild:755 - Line 23 in 'FIR.ucf': Could not find net(s)
'next' in the
   design.  To suppress this error specify the correct net name or
remove the
   constraint.  The 'Ignore I\O constraints on Invalid Object Names'
property
   can also be set ( -aul switch for command line users).

Secondly, when I compile without constraint file everything works fine
except that I get warnings
All outputs of the instance <fa4x16b0_fa4x1b0> of the block
<fullAdder4X1Bit> are unconnected in block <FIR>.
   This instance will be removed from the design along with all
underlying logic

but I have connected the outputs of this adder.
The adder module heirarchy is as follows:

module fullAdder4X16Bit(a,b,c,d,cin0,cin1,sum,carryout0,carryout1);
(top level)
module fullAdder4X1Bit(a,b,c,d,cin0,cin1,sum,cout0,cout1); (called
from fullAdder4X16Bit)

PLease help me in this regard.

Thanks 
Gul

Article: 65767
Subject: Re: Is it possible that a Virtex II device performs below its spec?
From: msm30@yahoo.com (William Wallace)
Date: 5 Feb 2004 23:24:16 -0800
Links: << >>  << T >>  << A >>
"MM" <mbmsv@yahoo.com> wrote in message news:<bvmaua$u760t$1@ID-204311.news.uni-berlin.de>...
> I have a design, which is supposed to work in XC2V2000-5 at 50 MHz. The
> timing analyzer reports the clock period to be below 19ns. However, in
> practice, only one device out of 3 works at this speed. Two others were
> happy when I slowed the clock to 45 MHz (I didn't try any intermediate
> frequencies). The design basically consists of a 3rd party IP core, for
> which I don't have a source (I believe it was designed in schematic),

Do a post PAR simulation.  Note that xilinx uses the same times for
min/typ/max in their sdf files.  (Do a search in their web database
for ways to get min sdf timing).  Do min and max timing simulation.

> some
> state machines, a bus interface and some Coregen memories. The bus runs at
> slower clock, but it is fully decoupled from the IP core (through the
> memories). 

What are the two clock rates?  Are you using dual ported FIFOs?  Are
they getting full?

> The IP core is a fully synchronous design according to its
> author. 

Trust but verify (do post PAR timing sim).

> The clock comes directly from an external crystal oscillator. I
> tried looking at unconstrained paths in the timing analyzer, but couldn't
> see anything suspicious...
> 
> Any ideas to where to look?

Get a scope out and look for reflections on your signals, especially
clocks.

Take the device that works and use a hair dryer to warm it, see if it
fails.

Look at using a DCM.

Are you gating any clocks?

> 
> Thanks,
> /Mikhail

Article: 65768
Subject: Re: Modelsim Error Code 211
From: msm30@yahoo.com (William Wallace)
Date: 5 Feb 2004 23:27:04 -0800
Links: << >>  << T >>  << A >>
Modelsim has excellent technical support in my experience.  Give them a call.

Also, try running the sim from a new, clean directory.  Recreated your wave.do file.

BrakePiston <brakepiston@REMOVEyahoo.co.uk> wrote in message news:<pde4201b5trk4bi9hsesbhlg3qbu5idkvn@4ax.com>...
> Hi everybody, 
> 
> I am experiencing a weird problem with Modelsim 5.7d
> 
> When i run my .do file with a "add wave" command, the program shuts. I
> have run it in command mode and I get that the error code is 211.
> Unfortunately, I have not found much about it on the modelsim website.
> 
> Can anyone help?
> 
> Thanks!

Article: 65769
Subject: Re: Altera Nios UART communication
From: msm30@yahoo.com (William Wallace)
Date: 5 Feb 2004 23:32:42 -0800
Links: << >>  << T >>  << A >>
hauyuanwen1980@yahoo.com (Jasmine Hau) wrote in message news:<fc6016ce.0402040012.4cfa5e01@posting.google.com>...
> Hi, can anybody tell me how to send/receive a multi-bit (Eg.160-bit or
> 512-bit)data between Altera Nios FPGA board with Visual Basic Program
> running on PC? Do i need any handshakind signal between the C source
> code which will downloaded into the embedded system with the VB
> program?

No, you don't need to use the modem control signals.  Books exist on
RS232 and Visual Basic, though I haven't read them.  Try amazon. 
You'll need to decide if you want a protocol (e.g., a checksum or CRC
at the end of your packet), or if you just want to accept the first N
bytes received.


>        And, can anyone recommen me any website to gain information
> regarding serial port communication interface and C source code of it?
> Thank you very much.

google.  Also, look for application notes for UARTs.

Article: 65770
Subject: Re: Power extimation?
From: msm30@yahoo.com (William Wallace)
Date: 5 Feb 2004 23:36:41 -0800
Links: << >>  << T >>  << A >>
raghurash@rediffmail.com (Raghavendra) wrote in message news:<1776d39.0401290453.3bd7cbe9@posting.google.com>...
> Hi All,
> How to manually estimate dynamic power consumption of the design in the FPGA?
> Thanks in advance,
> Raghavendra.S

Launch XPower from Xlinx project navigator, if you're using Xilinx.

Article: 65771
Subject: Re: Xilinx ILA -> supported FPGA ?
From: antti@case2000.com (Antti Lukats)
Date: 6 Feb 2004 00:46:40 -0800
Links: << >>  << T >>  << A >>
"Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote in message news:<402212ed$1@news.vsnet.ch>...
> Hi,
> 
> For a new product, I have to provide an on-board logic Analizer. I will 
> use ILA with JTAG port.
> The question is I don't know which SPARTAN I have to use to do the JOB.
> 
> We have to up to 130 Mhz acquisition for 64 bit vectors.
> The fifo data depth is not very important -> 16-32k will be enough.
> 
> The FPGA will just be used for Logic Analizer JOB, so which FPGA?

http://wiki.openchip.org/index.php/ChipScope

ChipScopePro 5.1 supported Spartan II/E, Virtex/E/II/Pro

sample width 64 is OK
maximum depth 16K

remember that alls samples goto internal BRAM so as example for
8 bit trigger 64 sample width 16k depth you need 65 BRAMS
so this will limit the selection of suitable FPGA
remember that ChipScope is not free and the ILA cores can not
be used without valid ChipScopePro software license 995$
so by using ChipScope you instantly add 1000$ to the product price.

antti
www.openchip.org

Article: 65772
Subject: Re: European supplier of Xilinx chips
From: "Dave Garnett" <dave.garnett@metapurple.co.uk>
Date: Fri, 6 Feb 2004 08:49:48 -0000
Links: << >>  << T >>  << A >>
Digikey.co.uk ! Excellent service, online stock situation and pricing (I
never use devices in design that I cannot buy 'off the shelf' - I have been
bitten too many times ...)

Dave

"Thomas Womack" <twomack@chiark.greenend.org.uk> wrote in message
news:LPs*Uslcq@news.chiark.greenend.org.uk...
> In article <4022C7FD.7020008@x-i-l-i-n-x_pleasenospam_dot_com>,
> Ryan Laity  <ryan_dot_laity@x-i-l-i-n-x_pleasenospam_dot_com> wrote:
> >Thomas,
> >
> >This information may also help:
> >http://www.xilinx.com/company/sales/ww_disti.htm
>
> I'm probably being unreasonable in expecting electronics distributors
> to have sites like Amazon, but the only distributor on that page with
> a Web site is Memec, and Memec requires you to burrow three layers
> deep for a part-number search, which then returns no results for
> something obvious like XC2VP7.
>
> avnet.com seems much better.  nuhorizons.com has a decent search
> interface but seems rather like Monty Python's cheese shop -- almost
> every query comes up with dozens of responses, all with no stock.
>
> Tom



Article: 65773
Subject: need desperate help!
From: filippdavid@yahoo.com (filippo)
Date: 6 Feb 2004 02:04:08 -0800
Links: << >>  << T >>  << A >>
I' m having great troubles making a small project on FPGA in Verilog.
I have to do it for an exam at university, it shoul be simple but it's
becoming hell.

facts:

- FPGA SPARTAN II xc2s100-5pq208
- Xilinx webpack ISE + modelsim
- uP:   AVRmega163

problem:

all simulations with modelsim are good, but it just doesn' t work on
the real FPGA and i don't know where to find a solution (or where is
the real problem).

of the 10+ modules one seems to be the most troublesome, our
IO_control, here is the code ,please help.

---------------------------------------------------------------------------------
module IO_control(ALE,NWR,NRD,DIR,DA,MIN,MAX,SEL,TYPEFIL,AMPLIF,DIVFRQ,clk);

    input ALE;

    input NWR;

    input clk;

    input NRD;

    input DIR;

    input [7:0] MIN;

    input [7:0] MAX;

    inout [7:0] DA;

    output [7:0] SEL;

    output [7:0] TYPEFIL;

    output [7:0] AMPLIF;

    output [7:0] DIVFRQ;

    parameter uno = 8'b0000_0001;



    reg [7:0] ADDR_REG;

    reg [7:0] DO_REG;

    reg [7:0] SEL_REG=uno;

    reg [7:0] TYPEFIL_REG=uno;

    reg [7:0] AMPLIF_REG=uno;

    reg [7:0] DIVFRQ_REG=uno;



    

	 assign SEL = SEL_REG;

	 assign TYPEFIL = TYPEFIL_REG;

	 assign AMPLIF = AMPLIF_REG;

	 assign DIVFRQ = DIVFRQ_REG;



	 assign DA = (DIR) ? 8'bzzzz_zzzz : DO_REG;

	  

	 always @ (posedge clk)

	  begin 

	   if (ALE)	ADDR_REG <= DA;

	   if (~NWR)   

	    case (ADDR_REG)

		    8'b0000_0001 :   SEL_REG <= DA;

		    8'b0000_0010 :   TYPEFIL_REG <= DA;

                    8'b0000_0100 :   AMPLIF_REG <= DA;

                    8'b0000_1000 :   DIVFRQ_REG <=DA;

		    default DO_REG <= 8'b1111_1111;

		endcase

  	   if (~NRD) 

		case (ADDR_REG)

		    8'b0000_0001 :  DO_REG <= SEL_REG;

		    8'b0000_0010 :  DO_REG <= TYPEFIL_REG;

                    8'b0000_0100 :  DO_REG <= AMPLIF_REG;

                    8'b0000_1000 :  DO_REG <= DIVFRQ_REG;

		    8'b0001_0000 :  DO_REG <= MIN;

		    8'b0010_0000 :  DO_REG <= MAX;

		    default DO_REG <= 8'b1111_1111;

		  endcase

	  end



endmodule

Article: 65774
Subject: Re: Do Xilinx Fix Their Prices?
From: news@sulimma.de (Kolja Sulimma)
Date: 6 Feb 2004 02:22:22 -0800
Links: << >>  << T >>  << A >>
Austin, there also is another effect:
I do not recall that nuhorizons for example ever changed the prices
listed on their website for any FPGA. I see a similar effect when
asking for low quantity quotes with insight in germany.

But when the chips get older, it becomes easier to make the distri
agree on a lower price for medium quantities.

For short: The distributors buy at lower prices over the lifetime of a
an FPGA but this does not mean that they change the price lists.

Kolja Sulimma



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