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Messages from 64725

Article: 64725
Subject: Xilinx JBit v1.x
From: osa_work@rambler.ru (wasp)
Date: 12 Jan 2004 07:53:06 -0800
Links: << >>  << T >>  << A >>
Who can share Xilinx JBit v1.x? or change it on JBit 2.8.

Article: 64726
Subject: Re: fpga database?
From: Larry Doolittle <ldoolitt@recycle.lbl.gov>
Date: Mon, 12 Jan 2004 16:07:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <me8500t4km81as3006nposc2bsib2klrme@4ax.com>, bob wrote:
> Hi Has anyone found a fpga database?
> 
> I would like to compare (mostly xilinx) FPGA and CPLDs on
> functionality and price and packaging  and other options.

Trust this as far as you can throw it.  At least some of the
prices (in US$, from distributor's web pages) are probably out
of date.  It's easy for me to parse and sort with awk, other
people may have trouble.  I don't promise all parts listed are
actually available.  No CPLDs and no Altera.  YMMV. IANAL. etc.

# Part            I/O   cells   RAM     price   multipliers
# Export toggle for XC2Sxx-5: 276.9 MHz
XC2S50-5PQ208C    140    1536    32     14.75
XC2S100-5PQ208C   140    2400    40     19.55
XC2S150-5PQ208C   140    3456    48     21.60
XC2S200-5PQ208C   140    4704    56     26.25

XC2S50-5FG256C    176    1536    32     16.65
XC2S100-5FG256C   176    2400    40     24.65
XC2S150-5FG256C   176    3456    48     27.00
XC2S200-5FG256C   176    4704    56     32.45

XC2S100-5FG456C   196    2400    40     31.00
XC2S150-5FG456C   260    3456    48     35.10
XC2S200-5FG456C   284    4704    56     39.10

# Export toggle for XC2SxxE-6: 357 MHz
XC2S50E-6PQ208C   146    1536    32     14.55
XC2S100E-6PQ208C  146    2400    40     19.15
XC2S200E-6PQ208C  146    4704    56     25.15
XC2S300E-6PQ208C  146    6144    64     38.60

XC2S50E-6FT256C   182    1536    32     16.45
XC2S100E-6FT256C  182    2400    40     28.75
XC2S200E-6FT256C  182    4704    56     36.25
XC2S300E-6FT256C  182    6144    64     47.50
XC2S400E-6FT256C  182    9600   160     91.52

XC2S100E-6FG456C  202    2400    40     30.40
XC2S200E-6FG456C  263    4704    56     37.50
XC2S300E-6FG456C  329    6144    64     57.60
XC2S400E-6FG456C  329    9600   160    111.10
XC2S600E-6FG456C  329   13824   288    139.00

XC2S400E-6FG676C  410    9600   160    141.90
XC2S600E-6FG676C  514   13824   288    194.70

# Export toggle for XCVxxE-6: 357 MHz
XCV300E-6FG256C   176    6144   128    160.00
XCV400E-6FG676C   404    9600   160    269.00
XCV600E-6FG676C   444   13824   288    454.00

# Export toggle for XCVxxE-7: 400 MHz
XCV50E-7FG256C    176    1536    64     51.45
XCV100E-7FG256C   176    2400    80     77.70
XCV200E-7FG256C   176    4704   112    134.00
XCV200E-7FG456C   284    4704   112    138.00
XCV300E-7FG256C   176    6144   128    204.00
XCV300E-7FG456C   312    6144   128    236.00
XCV400E-7FG676C   404    9600   160    376.00

# price each for quantity 25-99
# Export toggle for XC2Vxx-4: 653.59 MHz
XC2V500-4FG456C   264    6144   576    134.00      32
XC2V1000-4FG256C  172   10240   720    177.00      40
XC2V1000-4FF896C  432   10240   720    230.00      40
XC2V1000-4FG456C  324   10240   720    194.00      40
XC2V1500-4BG575C  392   15360   864    353.10      48
XC2V1500-4FF896C  528   15360   864    403.70      48
XC2V3000-4FG676C  484   28672  1728    598.00      96
XC2V3000-4BG728C  516   28672  1728    658.00      96
XC2V3000-4FF1152C 720   28672  1728    718.00      96
XC2V4000-4FF1152  824   46080  2160   1975.00     120
XC2V6000-4FF1152C 824   67584  2592   2669.00     144
XC2V8000-4FF1152C 824   93184  3024   6769.00     168

# price each for quantity 25-99
# Export toggle for XC2Vxx-5: 751.31 MHz
XC2V40-5FG256C     88     512    72     46.95       4
XC2V80-5FG256C    120    1024   144     59.45       8
XC2V250-5FG256C   172    3072   432    122.00      24
XC2V250-5FG456C   200    3072   432    132.00      24
XC2V500-5FG256C   172    6144   576    206.00      32
XC2V500-5FG456C   264    6144   576    226.00      32
XC2V1000-5FG256C  172   10240   720    332.00      40
XC2V1000-5FG456C  324   10240   720    364.00      40
XC2V1000-5BG575C  328   10240   720    285.00      40
XC2V1000-5FF896C  432   10240   720    322.00      40
XC2V1500-5BG575C  392   15360   864    495.00      48
XC2V1500-5FG676C  392   15360   864    471.90      48
XC2V1500-5FF896C  528   15360   864    565.40      48
XC2V2000-5FG676I  456   21504  1008    877.00      56
XC2V3000-5FG676C  484   28672  1728    838.00      96
XC2V3000-5FF1152C 720   28672  1728   1184.00      96
XC2V4000-5FF1152C 824   46080  2160   1975.00     120
XC2V6000-5FF1152C 824   67584  2592   3737.00     144
XC2V8000-5FF1152C 824   93184  3024   9477.00     168

# price each for quantity 25-99
# Export toggle for XC2VPx-5: 1050 MHz
XC2VP2-5FG256     140    2816   216       ?        12
XC2VP2-5FG456     156    2816   216       ?        12
XC2VP2-5FF672     204    2816   216       ?        12
XC2VP4-5FG256C    140    6016   504    113.30      28
XC2VP4-5FG456C    248    6016   504    124.30      28
XC2VP7-5FG456C    248    9856   792    176.00      44
XC2VP20-5FF896C   556   18560  1584    327.00      88

# price each for quantity 25-99
# Export toggle for XC2VPx-6: 1200 MHz
XC2VP4-6FF672CES  348    6016   504    350.00      28
XC2VP7-6FF672C    396    9856   792    473.00      44
XC2VP30-6FF1152C  644   27392  2448    808.00     136
XC2VP40-6FF1152C  692   38784  3456   1206.00     192
XC2VP50-6FF1152C  692   47232  4176   1880.00     232

# price each (no stock) for quantity 25-99
# Export toggle for XC3Sxx-5: 326 MHz
XC3S50J-4PQ208CES 124    1536     0     27.45       0
XC3S50J-4TQ144CES  97    1536     0     23.85       0
XC3S400-5FT256C   173    7168   288       ?        16
XC3S400-5FG456C   264    7168   288       ?        16
XC3S1000-5FT256C  173   15360   432    191.40      24
XC3S1000-5FG676C  391   15360   432       ?        24
XC3S1000-5FG456C  333   15360   432       ?        24  
XC3S1500-5FG456C  333   26624   576       ?        32

Article: 64727
Subject: Re: min propagation delay in xilinx cpld
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 12 Jan 2004 09:02:41 -0800
Links: << >>  << T >>  << A >>


guille wrote:
> Uh? That's the first time I heard about timing changing due to age
>
And hopefully you will nrvrt hear this kind of nonsense again.
Different from humans, silicon does not get slower with age, or more
tired. Doesn't get any smarter either. ;-) 
 It just stays the way it is, unless somebody overstresses it (mainly in
the I/O)
Peter Alfke, Xilinx
>

Article: 64728
Subject: The Fifo in xapp258
From: Kjetil Eriksen Vistnes <kjetiler@ifi.uio.no>
Date: Mon, 12 Jan 2004 18:02:46 +0100
Links: << >>  << T >>  << A >>
I'm using the Fifo in Xilinx application note xapp258,and
the following problem occurs during Behavioral simulation:

The last value in the queue doesn't read out. The same thing happens
if I'm
writing only one value to the queue, and sets "read_enable_in" high for
one clock cycle: No data
out. A burst read on eg. the last elements in the Fifo reads out perfectly
fine. The last element is beeing read out.

Is it something I'm doing wrong in simulation?
Have anyone had this problem with this Fifo or know a solution to it?

Kjetil Vistnes


Article: 64729
Subject: Re: How to generate a CSA tree?
From: Peter Alfke <peter@xilinx.com>
Date: Mon, 12 Jan 2004 09:06:26 -0800
Links: << >>  << T >>  << A >>
The most automatic way to design a fast multiplier is to just use the
one that exists as a hard macro ( i.e. dedicated logic) in the newer FPGAs.
I bet you cannot beat its speed...
Peter Alfke
==================
Sleep Mode wrote:
> 
> Hi all,
> 
> I am trying to design a 16-bit integer multiplier in VHDL and I want to use
> a Carry-Save-Adder (CSA) tree for generating the interim subproducts
> and -then- with an additional CPA (or other) adder to add them to the final
> 32-bit product; i.e. I want to build a full-tree multiplier.
> 
> My question is whether there is some automatic (core) generator for the
> CSA-tree interconnections since it is rather complicated to do it by hand...
> If not, is there any fast method of drawing it manually (pen-and-paper) so
> that I can translate it to VHDL later on?
> 
> Thanks in advance guys,
> Chris

Article: 64730
Subject: IOB costraints
From: "Max" <maximoj@libero.it>
Date: Mon, 12 Jan 2004 18:33:13 +0100
Links: << >>  << T >>  << A >>
can I syncronize some I/o port of the spartan2E why commute at the same
time? Creed that must use one costraints, do you know which?



Article: 64731
Subject: to generate steps in phase
From: "Max" <maximoj@libero.it>
Date: Mon, 12 Jan 2004 18:40:56 +0100
Links: << >>  << T >>  << A >>

I must generate 4 able steps to command some Dff.In this way:

PCk0<=CLK0_S and CLK270_S;
PCk90<=CLK90_S and CLK0_S;
PCk180<=CLK90_S and CLK180_S;
PCk270<=CLK180_S and CLK270_S;

I use a DLL.
how I can obtain marks them clean and in phase?



Article: 64732
Subject: Power plane assignments in a Xilinx PCI card
From: "Dan DeConinck" <pixelsmart@sympatico.ca>
Date: Mon, 12 Jan 2004 10:56:00 -0800
Links: << >>  << T >>  << A >>
Hello ,

I was looking at someone else's ( 4 layer ) design and I noticed that they
had the ground plane on layer two: ( I always have ground on LAYER 3 )

LAYER 1 = component
LAYER 4 = solder side

Well , does the layer assignment matter  ? ( in terms of noise or impedance
... )

Here is an idea. If ground is on layer two then the signals on layer 1 might
be more isolated from noise in the power plane on layer 3, ( note: I have
almost all signals routed on layer 1; layer 4 is almost bare )

Is that a real benefit ?

Would the ground plane have noise too ? I always think of the ground plane
as being clean and the power plane as having the noise but perhaps this is a
false notion ?

Also should the power and ground planes extend down into the PCI bus edge
connector fingers ? Or is that a rather insignificant concern one way or the
other.

Sincerely Dan



Article: 64733
Subject: ANNOUNCE: Impulse CoDeveloper for MicroBlaze & Nios FPGAs now available
From: "David Pellerin" <david.pellerin@ImpulseC.com>
Date: Mon, 12 Jan 2004 11:02:03 -0800
Links: << >>  << T >>  << A >>
Impulse Accelerated Technologies is pleased to announce the release of
CoDeveloper for Altera Nios, Xilinx MicroBlaze and other FPGA-based
computing platforms. CoDeveloper is a hardware/software codesign product
that allows highly parallel applications to be developed entirely in the C
language and compiled to mixed processor/FPGA platforms. This is useful for
FPGA-based acceleration of software applications as well as fast prototyping
and testing of FPGA-based algorithms.

Evaluation licenses are available, and product details can be found at
www.ImpulseC.com/ImpulseC.htm.

See also http://www.soccentral.com/results.asp?entryID=4051

David Pellerin




Article: 64734
Subject: using signal as clk source
From: Tobias =?iso-8859-1?Q?M=F6glich?= <Tobias.Moeglich@gmx.net>
Date: Mon, 12 Jan 2004 20:51:37 +0100
Links: << >>  << T >>  << A >>
Hello

I use Xilinx ISE Foundation 6.1.

Is it possible to use a signal as a clk source?
The problem I got is: if I assign a special Pin (LOC constraints), the
mapper tool claims:

"ERROR:MapLib:93 - Illegal LOC on IPAD symbol "IOSTRB_DSP" or BUFGP
symbol
   "IOSTRB_DSP_BUFGP" (output signal=IOSTRB_DSP_BUFGP), IPAD-IBUFG
should only
   be LOCed to GCLKIOB site"


(-> the signal_name is IOSTRB_DSP)

If I don't make a constraint for the signal, the report say: used: Type:
GCLKIOB.
Why does ISE not connect it to an GCLKIOB as I put in a LOC constraint
for the signal IOSTRB_DSP?

I have to tell "place & route" where to connect the signal to.
What should be filled in the constraint file?
Or what should be chosen in PACE?

Thanks for any help.


Tobias Möglich




Article: 64735
Subject: Re: Synthesis in VHDL vs. Verilog
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Mon, 12 Jan 2004 20:13:38 GMT
Links: << >>  << T >>  << A >>
On Mon, 12 Jan 2004 16:06:54 +1100, Allan Herriman
<allan.herriman.hates.spam@ctam.com.au.invalid> wrote:

>Verilog 2001 supports attributes.  However, even in this latest
>version of the language, it still isn't possible to have an attribute
>whose value is a string that is a function of e.g. a genvar.
>
>Details here:
>http://groups.google.com/groups?threadm=mB7gb.12033%24dH7.6968%40newssvr25.news.prodigy.com
>
>[Sarcasm] Clearly the language committee understands the needs of
>users.

That's a very interesting thread; I missed it the first time around.
Thanks for pointing it out.

Bob Perlman
Cambrian Design Works


Article: 64736
Subject: V2Pro Rocket IO Primitive- Parameter and Port Settings
From: "Adarsh Kumar Jain" <adarshkumarjain@hotmail.com>
Date: Mon, 12 Jan 2004 15:18:08 -0500
Links: << >>  << T >>  << A >>
Hi,
I am trying to use the Rocket IO transceiver as a receiver only (no clock
correction, no channel bonding, no CRC). I do need to do 8b/10b decoding.
Looking at the macro available, and from the Transceiver User Guide, there
are so many parameters and ports which need to be configured. I am new to
the Transceiver Designs and hence am not able to make out what all I need to
do.
I tried to do a simulation of a very basic design using these RocketIOs but
all i get out is XXXXs.
I am using ISE6.1SP3 and Active   HDL 6.1 SP2
Any help will be appreciated.
Thanks in advance,
Adarsh



Article: 64737
Subject: Making XAPP134 synthesizable
From: "Simone Winkler" <simone.winkler@gmx.at>
Date: Mon, 12 Jan 2004 21:44:07 +0100
Links: << >>  << T >>  << A >>
Hello!

I'm using the Xilinx XAPP134 for a SDRAM controller. It is quite ok and
works in the functional simulation, but I don't manage to make it
synthesizeable. There's a special directory in the xapp that is called
synth - I suppose this should be the synthesizable source files - but I
tried to simulate that and "nearly everything" is red lines. :-(

I'm using Xilinx ISE Webpack 5.2i Service Pack 3 together with Modelsim XE
Starter 5.6e.

The source code can directly be downloaded at the Xilinx homepage:
ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip
Documentation (but unfortunately not a very good one):
http://direct.xilinx.com/bvdocs/appnotes/xapp134.pdf

Additionally I changed the xapp in order to only have a data with of 16 bit
at the output (while leaving the input and internal part unchanged, so no
special change). But I also tried to simulate the original 32bit-version ->
it was the same!

Can somebody help me???
I really don't have any experience in making vhdl models synthesizable - I
don't know where to start, what to look at - maybe you also have a kind of
tutorial that gives an introduction to "making synthesizable vhdl models" or
something similar.

Thank you VERY much!! :-))

Simone


Article: 64738
Subject: Re: Synthesis in VHDL vs. Verilog
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: 12 Jan 2004 22:31:47 +0100
Links: << >>  << T >>  << A >>
Jim Lewis <Jim@SynthWorks.com> writes:

> their IP in Verilog and translates to VHDL has imposed
> the strong typing rules of VHDL onto their Verilog

But, there is only one type -- "wire"...

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 64739
Subject: Re: Altera Cyclone data is incomplete or messy
From: Rene Tschaggelar <none@none.none>
Date: Mon, 12 Jan 2004 21:38:37 GMT
Links: << >>  << T >>  << A >>
Ralph Malph wrote:
> Rene Tschaggelar wrote:
> 
>>Browsing the 'cyclone device handbook' I spent a great
>>length to find :
>>-the max current for each supply ( VCCIO & VCCINT )
>>-the expected clocking frequency at the input. I'm aware
>>  that 1MHz may not be sufficient to PLL it up to 400MHz
>>  or such.
>>
>>to little avail. While I can live with 2 switchmode supplies
>>generating 1.5V and 3.3V at 2A each, and a generic 8pin
>>socket to swap oscillators for a prototype, the documentation
>>is somehow inclomplete.
> 
> 
> I don't think anyone publishes a *max* current for FPGAs.  This depends
> greatly on the design and the clock speed.  It even depends on the
> loading on the IO lines.  But one way you can set a ceiling is to figure
> out the maximum dissipation the package can provide and assume that can
> come from either of the two supplies.  The may be very conservative, but
> it will give you a *maximum*.

At least the earlier Altera FPGAs had graphs. Usually 1/8 th of the
cells used, current vs clock. Just multiply by 8 and you're about
there.

I somewhat doubt everyone makes the prototypes with leads to be
connected to a laboratory power supply.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net


Article: 64740
Subject: Re: Synthesis in VHDL vs. Verilog
From: Jim Lewis <Jim@SynthWorks.com>
Date: Mon, 12 Jan 2004 15:05:11 -0800
Links: << >>  << T >>  << A >>
Robert,

The paper is paper 6.1:
   AVOIDING ANOTHER VERILOG/VHDL WAR:
   GOOD CODING PRACTICES FOR SOFT IP VENDORS
   Dhanendra Jani, Tensilica Inc., Santa Clara, CA
   Alain Raynaud, Tensilica Inc., Santa Clara, CA

   The quoted number came from the presentation and I could
   not find it in the paper.  The paper is copyrighted, so
   I can't send you a copy.  You may be able to find the paper
   on Tensilica's website.  If you went to DVCon or have access
   to a disk, it is paper 6.1.

 > Maybe you meant precise?
Exactly.

My brain just blew a fuse when with the ironic statement:
"Verilog is a very simple language so it's easier for
the tools guys to get it right."

Historically the problem with Verilog was that it
executes differently on different platforms unless
you follow some adhoc coding rules.  How quick we
forget.

VHDL never had race conditions and never will.

Cheers,
Jim



Robert Sefton wrote:

>>VHDL is a very consise language.  Code written and
>>simulated in one simulator will behave exactly the
>>same in another simulator.
>>
> 
> 
> Jim -
> 
> Concise means succinct, i.e., the opposite of verbose. I've never heard
> anyone make that claim about VHDL. Maybe you meant precise?
> 
> Do you have a link to that DVCon paper? I'd like to read it. If not, can
> you briefly summarize some of the rules this company imposed?
> 
> Thanks,
> 
> Robert
> 
> 

-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Jim Lewis
Director of Training             mailto:Jim@SynthWorks.com
SynthWorks Design Inc.           http://www.SynthWorks.com
1-503-590-4787

Expert VHDL Training for Hardware Design and Verification
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~


Article: 64741
Subject: Re: FPGA CAD researchers: documentation, APIs, file formats & tutorials for academics to interface to Quartus
From: a_r_marquardt@yahoo.com (Alexander Marquardt)
Date: 12 Jan 2004 15:22:36 -0800
Links: << >>  << T >>  << A >>
That looks super cool!!! I think I need to go back and do a Ph.D. just
so I can try to beat you guys using my new "transmorgrofiying 3D
wire-cutting placement algorithm" idea (now that you have made it so
easy to make comparisons)!!

Seriously, I didn't even know that this was coming out, and it looks
great! What a great idea ... the only problem is I think that you are
going to put the "academic" version of VPR out of business, which
could hurt your chances at becoming a professor in the future after
you have finished getting that Altera stock price up high enough to
make me a millionaire ..


Alexander Marquardt

Former Altera Engineer
Current MBA Student in Spain (http://mba.iese.edu)
Future Bartender in South America



vbetz@altera.com (Vaughn Betz) wrote in message news:<48761f7f.0401062338.4ce4f3d3@posting.google.com>...
> I am pleased to announce that Altera has opened up its Quartus II CAD
> suite to university researchers.  The Quartus University Interface
> Program, or QUIP, toolkit is designed to enable university (or other)
> researchers to plug new CAD tools and ideas into the Altera Quartus II
> CAD flow.
> 
> QUIP describes Altera's devices, interfaces by which data can be sent
> into the Quartus II software at various points in the CAD flow, and
> data formats in which data can be dumped out of the Quartus II
> software.  QUIP also includes tutorial and sample programs showing how
> to use the various APIs and data file formats.  This toolkit enables
> researchers to write point CAD tools that perform one CAD optimization
> in a new or better way, and integrate their new CAD tool into a
> complete CAD flow so they can get realistic results on how this new
> idea improves circuit timing, routability, device utilization, compile
> time, or other metrics.
> 
> You can augment or replace virtually any phase of the Quartus II CAD
> flow (e.g. all of  synthesis, or logic optimization, or technology
> mapping, or placement, etc.) or add new phases (floorplanning,
> wire-type routing, physical synthesis, etc.).  You can then get
> statistics back from the Quartus II CAD suite showing how much your
> new tool or algorithm improves circuit timing, routability, device
> utilization, or other metrics.  You can quickly test new CAD ideas in
> an industrial strength tool flow, and avoid having to write a complete
> CAD suite to test your ideas.
> 
> The benefit to academics is the ability to focus more on innovative
> CAD algorithms and tools, and less on putting together entire CAD
> flows to test out these new algorithms and tools.  In my PhD I spent
> five years writing a place and route system, including timing
> analyzer, etc., so this would certainly have helped me graduate
> faster!
> 
> The benefit to us at Altera is (we hope!) more FPGA CAD research, and
> research not just on simplified FPGA architectures and on simple
> benchmark circuits, but on the full range of problems presented by
> today's complex FPGA architectures, and the complex hardware designs
> going into those FPGAs.
> 
> For more details on QUIP, and to download all the documents,
> tutorials, APIs, etc, see
> http://www.altera.com/education/univ/quip/quip-overview.html.  Feel
> free to contact me, or mail quip@altera.com, or post to this
> newsgroup, if you have any questions.
> 
> Regards,
> 
> Vaughn Betz
> Altera

Article: 64742
Subject: System Generator and Microblaze
From: mnownby21@tntech.edu (Matt)
Date: 12 Jan 2004 15:23:43 -0800
Links: << >>  << T >>  << A >>
I'm working on a research project and my goal is do design hardware
using system generator and the software using microblaze. How can you
put a microblaze design into a system generator design (the system
generator is the top design).

Thanks
Matt

Article: 64743
Subject: Re: Synthesis in VHDL vs. Verilog
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Tue, 13 Jan 2004 11:35:05 +1100
Links: << >>  << T >>  << A >>
On Mon, 12 Jan 2004 15:05:11 -0800, Jim Lewis <Jim@SynthWorks.com>
wrote:

>VHDL never had race conditions and never will.

It's actually quite easy to make races in VHDL.  Experience indicates
that even simple examples may produce different results on different
LRM compliant simulators.


signal clk1, clk2 : std_logic;
signal sig1 : std_logic;

...

clk2 <= clk1;  -- clk2 lags clk1 by 1 delta

process (clk1)
  ...
  sig1 <= foo;
  ...

process (clk2)
  ...
  bar <= sig1;
  ...


Astute designers will modify their coding standards to disallow clock
assignments such as the one above.  

Jim, when discussing the relative merits of Verilog and VHDL it is
important not to make false claims about either language.

Regards,
Allan.

Article: 64744
Subject: Re: Xilinx ECS - connecting a single net to multiple bus lines?
From: ad.rast.7@nwnotlink.NOSPAM.com (Alex Rast)
Date: Tue, 13 Jan 2004 01:27:45 -0000
Links: << >>  << T >>  << A >>
at Sat, 10 Jan 2004 09:53:18 GMT in
<ugivvvstto8ckvaeml8resjb200jghkvsv@4ax.com>, philip@fliptronics.com
(Philip Freidin) wrote : 

>On Wed, 07 Jan 2004 21:36:15 -0000, ad.rast.7@nwnotlink.NOSPAM.com (Alex
>Rast) wrote: 
>
>A)
>>What's the way to do this? It's common for me to run into situations
>>where I have a bus or bus pin, and I need to connect the same net to
>>different lines on the bus.
>
>B)
>>Another common one is I have 2 busses, both of which have 
>>a line that should connect to a single net. The documentation doesn't
>>seem to give any hints. Thanks for any input.
>
>While I have not used ECS, the way we did this in previous schematic
>systems was to pass the source single through multiple "BUF" symbols.
>...
>The BUF is a primitive that uses no logic resources. It is used to alias
>one signal name to another, and is trimmed out during the P&R process

It seems stupidly cumbersome to have to do this. Since I'm not thrilled 
(read "mistrust the software" about relying on something to be trimmed out 
during P&R - incidentally, why do no S/W packages seem to want to allow an 
easy way for you to define P&R manually, when P&R is the one thing that a 
computer does the least well - so I created the following general-purpose 
VHDL "component"

entity ConnectLine2Bus is
    Generic (BusWidth : integer := 8);
    Port ( 
    		InputSignal : in std_logic;
		OutputBus : out std_logic_vector((Buswidth-1) downto 0));
end ConnectLine2Bus;

architecture StraightThrough of ConnectLine2Bus is

signal ConnectInt : std_logic;

begin

ConnectInt <= InputSignal;
ConnectSignals: for LineNo in 0 to (Buswidth-1) generate
	OutputBus(LineNo) <= ConnectInt;
end generate;

end StraightThrough;

and then used the "Generate Schematic symbol" to create a symbol for it. 
You can then make connections of arbitrary size, which works nicely and as 
you can see from the VHDL description, I'm simply wiring straight through.

Still, the whole thing seems ridiculous,  IMHO something Xilinx should fix 
in future revisions.

-- 
Alex Rast
ad.rast.7@nwnotlink.NOSPAM.com
(remove d., .7, not, and .NOSPAM to reply)

Article: 64745
Subject: Re: Anybody know what the REAL story is?
From: "Dipl.-Ing. Andreas Schmidt" <as@asic.cc>
Date: Tue, 13 Jan 2004 01:31:34 GMT
Links: << >>  << T >>  << A >>


Hi all,

I have worked 2 years for GIBSON in Sunnyvale as a Senior ASIC engineer in the
MaGIC design team together with Jeffrey Vallier...
I could answer a lot of questions asked here into detail, but I'm bond to
confidentiality...
I'm still 'theoretically' a GIBSON employee, but in a 'transition state' after
3 months of unpaid-leave-of-absence...

Without sacrificing confidentiality I can say:
- that the original plan was to have a GIBSON ASIC as the final solution...
- I and Jeff favoritized Xilinx because of various reasons as a platform
- I mentioned multiple times to management that using FPGAs would be the best
solution
  when it comes to required flexiblity and the number of chips required per
year
  ( to get a real total cost advantage of an ASIC solution compared to an FPGA
solution
    you have to use an advanced process line together with a 100.000
chips/year....
    vendors of this process lines require a multi-million dollar revenue in
order to run your design,
    neglecting some additional NRE costs that are required...)
- there will be definately no GIBSON ASIC soultion in the next months....
  (based on the design status and normal ASIC vendor lead times and
requirements)
- for most of the time there were 2 people working on the design (Jeffrey and
me)
- in the last year there was an additional 3rd person working partially on the
design
  (he was revising/changing the MaGIC spec continiously...)
- Jeffrey left GIBSON and joined a company in Korea 3 months ago...
- the original code was highly portable, scalable and parametrizable using an
OOHD design technique
  that was synthesizable easy and fast with FPGA Express or Synplify
  (incorporation of RAMs and the usage special architecture features could be
changed easily
   before resynthesis for a new platform without sacrifying architecture
optimization
   [the instantiation of RAMs is different for each ASIC and FPGA vendor])
- the team worked the whole time with budget and tool restrictions...

Hopefully I was able to add some more detailed parts to the puzzle to make it
easier to see the whole picture...
Happy puzzling...

cul8r, AS (Andreas Schmidt)
aka 'The Wild German Guy'
as@asic.cc
http://www.asic.cc

Patrick MacGregor wrote:

> Last year X announced a cool design win using their parts in a new Gibson
> guitar line.  Neat stuff.
>
> Couple days ago I see that A has a press release saying they stole the
> business with NIOS + Cyclone.
>
> Today I see X saying S3 is the clear winner and Gibson is using it
> exclusively.
>
> Anyone know what is really going on?
>
> Just curious.  The Gibson product is kinda cool regardless of who's part is
> in it.
>
> PM





Article: 64746
Subject: Re: Power plane assignments in a Xilinx PCI card
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Tue, 13 Jan 2004 01:55:47 GMT
Links: << >>  << T >>  << A >>
> Here is an idea. If ground is on layer two then the signals on layer 1
might
> be more isolated from noise in the power plane on layer 3,

The problem is much more complicated than this.  There is no such thing as
"isolation".  Keep that in mind.  You could have a badly designed ground
layer right below your signal layer and make a mess out of the whole thing.
Also, operating frequencies and signal standards are important.

Think "return path" for every single signal.  Try to visualize how current
will be delivered to the chip in question.  Then to the pin driving a trace.
And from the pin to the. Which is a capacitor that needs to be
charged --among other things. And then discharged.  The return path is
important.  At high speeds power delivery to the chip can be (it is usually
the goal) localized by means of small decoupling capacitors and inter-plane
energy storage.  At lower frequencies energy can be delivered from farther
out.


> Would the ground plane have noise too ? I always think of the ground plane
> as being clean and the power plane as having the noise but perhaps this is
a
> false notion ?

Absolutely.  "Ground" is a product of our imagination.  Pick a spot.  Call
it your reference.  I can pick a different one.  Probably just as valid.
Current flowing through a conductor will result in resistive and inductive
effects.  Capacitive effects are added when many conductors are in close
proximity.  This means that the "ground" layer will have different
potentials at different point at different times.  The ground layer can
actually oscillate and resonate.  Imagine 200 pins switching form low to
high in unison in 1ns at the far end (w/respect to the power connector) of
the board.  Bad things can happen.  This is why the SI community resorts to
fancy simulation tools.


> Also should the power and ground planes extend down into the PCI bus edge
> connector fingers ? Or is that a rather insignificant concern one way or
the
> other.

How would you get power into the board otherwise?  Are you saying that you'd
run a trace from the PCI edge connector's power/gnd pins into the
power/ground planes?  No.  The planes need to go everywhere.

You might want to pickup a good high-speed design book (Howard Johnson's
"High Speed Digital Design, a Handbook of Black Magic") and/or search the
WWW for articles on the subject.


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"




Article: 64747
Subject: SPARK now supports Windows & Xilinx XST
From: "Sumit Gupta" <sumitg@ics.uci.edu>
Date: Mon, 12 Jan 2004 18:00:24 -0800
Links: << >>  << T >>  << A >>
We have released a new version of the SPARK C-to-VHDL tool that is available on the Windows, Solaris, Linux platform and produces VHDL that is synthesizable by Xilinx XST. 
SPARK can be downloaded from: 
http://www.ics.uci.edu/~spark/download.shtml 

Sumit 
sumitg@cecs.uci.edu 
http://www.ics.uci.edu/~sumitg 



Article: 64748
Subject: Re: Power plane assignments in a Xilinx PCI card
From: "Matt" <bielstein2002@comcast.net>
Date: Tue, 13 Jan 2004 02:46:55 GMT
Links: << >>  << T >>  << A >>
I would add this one to Martin's recommendation. (I've read both.)

http://www.speedingedge.com/rtft_book.htm

Matt



"Dan DeConinck" <pixelsmart@sympatico.ca> wrote in message
news:0szMb.6213$881.755369@news20.bellglobal.com...
> Hello ,
>
> I was looking at someone else's ( 4 layer ) design and I noticed that they
> had the ground plane on layer two: ( I always have ground on LAYER 3 )
>
> LAYER 1 = component
> LAYER 4 = solder side
>
> Well , does the layer assignment matter  ? ( in terms of noise or
impedance
> ... )
>
> Here is an idea. If ground is on layer two then the signals on layer 1
might
> be more isolated from noise in the power plane on layer 3, ( note: I have
> almost all signals routed on layer 1; layer 4 is almost bare )
>
> Is that a real benefit ?
>
> Would the ground plane have noise too ? I always think of the ground plane
> as being clean and the power plane as having the noise but perhaps this is
a
> false notion ?
>
> Also should the power and ground planes extend down into the PCI bus edge
> connector fingers ? Or is that a rather insignificant concern one way or
the
> other.
>
> Sincerely Dan
>
>



Article: 64749
Subject: Re: using signal as clk source
From: "Jay" <yuhaiwen@hotmail.com>
Date: Tue, 13 Jan 2004 10:52:23 +0800
Links: << >>  << T >>  << A >>
BUFGP is IBUFG + BUFG, and IBUFG can only be used by signal from GCLK pins.

just use BUFG only.
"Tobias Möglich" <Tobias.Moeglich@gmx.net>
??????:4002FAC9.24DEF52E@gmx.net...
> Hello
>
> I use Xilinx ISE Foundation 6.1.
>
> Is it possible to use a signal as a clk source?
> The problem I got is: if I assign a special Pin (LOC constraints), the
> mapper tool claims:
>
> "ERROR:MapLib:93 - Illegal LOC on IPAD symbol "IOSTRB_DSP" or BUFGP
> symbol
>    "IOSTRB_DSP_BUFGP" (output signal=IOSTRB_DSP_BUFGP), IPAD-IBUFG
> should only
>    be LOCed to GCLKIOB site"
>
>
> (-> the signal_name is IOSTRB_DSP)
>
> If I don't make a constraint for the signal, the report say: used: Type:
> GCLKIOB.
> Why does ISE not connect it to an GCLKIOB as I put in a LOC constraint
> for the signal IOSTRB_DSP?
>
> I have to tell "place & route" where to connect the signal to.
> What should be filled in the constraint file?
> Or what should be chosen in PACE?
>
> Thanks for any help.
>
>
> Tobias Möglich
>
>
>





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