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"Nicolas Matringe" <nicolasmatringe001@numeri-cable.fr> wrote in message news:412219B6.2070303@numeri-cable.fr... > Hello > I am trying to implement a PCI design in a Spartan3 device. Everything > went quite well until I decided to use a DCM to remove the last timing > problems I got. what PCI core are you using and why did you want to use DCM? DCMs are not normally used in the PCI cores. So may advice is: remove the DCM and get the core implemented in way that it passes timing. > Since I put the DCM in my design, ISE refuses to P&R. > Here is what I got in the P&R report file: > > WARNING:Ncd:218 - The component "pci_clk_in" specified in the .PCF file the safest way always is to use one .UCF and text editor for the constraints:) .NCF and .PCF files sound like trouble... at least the .NCF does sometimes make problem (with ChipScopePro) recheck your design and reports again to see that the nets by that exact name exist and have not been renamed and nothing isnt trimmed etc.. antti http://www.openchip.org/ebay/FreePCI_Cores_Report.htmlArticle: 72401
Hi everyone, Can anyone tell me where can i buy NAND flash memory chips from? I am interested in samsung ones, but any other NAND chip can be helpfull. I can see them on samsung website but dont know how i can buy small quantities of them given that i am in australia. thanksArticle: 72402
Hello , I am an engineering student and am working on testability issues in FPGA devices. Can anybody throw light on the BIST schemes used by Xilinx in their devices ; i.e. how do they achieve 100% fault coverage;whether they use soft BIST or hard BIST. Any information will be appreciated. Thanks in advance. Regds. VarunArticle: 72403
ted644@hotmail.com (Ted) wrote in message news:<cd8a739a.0408120853.6a3147a8@posting.google.com>... > I was trying to use the SDRAM controller > without using the NIOS. I am now using the vhdl file generated from > SOPC builder. > > Things are great during simulation i.e. However, when I try to > synthesize it. I receive the following warning message: > > Warning: Can't pack node sdram_0:sdram_con_inst|m_addr[10] to I/O pin. > +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and > I/O node zs_addr[10] -- logic cell cannot be packed as I/O register > +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and > I/O node sdram_0:sdram_con_inst|m_addr[10] -- logic cell cannot be > packed as I/O register > +Warning: Can't pack logic cell sdram_0:sdram_con_inst|m_addr[10] and > I/O node sdram_0:sdram_con_inst|i~28445 -- logic cell cannot be packed > as I/O register > > The m_addr[10] ties to the address pin of the RAM. Bits 9 and 8 are > the same as well. Can't seem to find out the reason. > > I understand that a register is inserted at the pins to optimize > timing. If this this node is not packed, does it mean to say that it > is bypassed to the pin. In a sentence, how does this impact > functionality? > > Timing analyzer tests indicate that +ve slack so in the end, timing > seems up to scratch. Ted, Warnings like this normally come from the fitter, and indicate that an assignment (generally a FAST_INPUT_REGISTER or FAST_OUTPUT_REGISTER assignment) that requested that a register be placed in an IO cell could not be honoured. You should check the sub-messages around this message (by clicking on the "+" to expand the sub-messages, if you're running in the GUI) and right click on the messages to get on-line help on why the register couldn't go in the IO cell. If you met all your timing constraints anyway, the design will still work fine. Putting the registers in the IO cell is purely a performance optimization to improve IO timing. You should make sure that the timing constraints are complete though (i.e. you have timing constraints on everything you care about), since the timing analyzer only analyzes what you ask it to. Vaughn AlteraArticle: 72404
Brad, These FPGA vendors never make our life simpler. LVCMOS33 is supposed to refer to 3.3V LVCMOS I/O Standard. I too am a little confused on this. Recently, on a Lattice CPLD I was using, the tool selected the default i/o standard as lvcmos18. I generated the jed file and tested and everything was running cool. Only later did I realise that i selected 1.8v io standard on the cpld whereas all the ios on my board are 3.3v :( I think the cpld didnt burn because it requires a VCCIO and that is 3.3V.... I know how to set the default io standard option in Lattice constraints file. For xilinx.... will let ya know when I know it myself. Narasimha. "Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:<10i4ems19um78ed@corp.supernews.com>... > Thanks for the article, Narasimha. > > Still need information about (or if possible) to set the default IO > standard, getting rid of an old group, and it just occured to me that I am > assuming that the 33 after LVCMOS refers to the Vcco but I never confirmed > that. Might it be something else like the Voh? > > Brad >Article: 72405
Raj, just looking at the kernel command line I would say that these are two different Linux kernels. In one case you try to boot from NFS in the other from a RAM disk. - Peter rajendra k singh wrote: > Hi All, > I am trying to boot linux on virtex 2 pro P7-ff672 board. My problem is > that I am able to boot the linux image(ppc) on bitstream generated by EDK > 6.1 but not with bitstream generated by EDK 6.2 (SP2). Does anyone had > similar experience ? I wonder if the problem is EDK 6.2 or I need to change > my liuux image which should not be the case as I am using the same version > of cores. Following is the only message I get on bitstream generated by 6.2 > EDK. > > loaded at: 00400000 0045D1E4 > board data at: 0045A13C 0045A154 > relocated to: 00405600 00405618 > zimage at: 00405AFB 00459C4F > avail ram: 0045E000 02000000 > > Linux/PPC load: root=/dev/nfs rw ip=on > Uncompressing Linux...done. > Now booting the kernel > > > While the same Image produce following message on 6.1 bitstream > > loaded at: 00400000 005C71D0 > board data at: 005C4128 005C4140 > relocated to: 00405608 00405620 > zimage at: 00405B24 0045A2AA > initrd at: 0045B000 005C3E44 > avail ram: 005C8000 02000000 > > Linux/PPC load: root=/dev/ram > Uncompressing Linux...done. > Now booting the kernel > Linux version 2.4.18_mvl30-ml300 () (gcc version 3.2.1 20020930 (Mo > ntaVista)) #7 Mon Mar 1 19:31:21 MST 2004 > Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc. > (source@mvista.com) > > On node 0 totalpages: 8192 > zone(0): 8192 pages. > zone(1): 0 pages. > zone(2): 0 pages. > Kernel command line: root=/dev/ram > Xilinx INTC #0 at 0xD0000FC0 mapped to 0xFDFFEFC0 > Calibrating delay loop... 299.82 BogoMIPS > ........ > > Any pointers or suggesitions are appreciated. > > Thanks > raj > >Article: 72406
Gerd wrote: > Are you sure it's instruction fetches that get corrupted? Because > about the SRLs/LUTs the standing explanation is that readback and > write access collide, not readback and read access - so I wonder if > it really was the readback + read-instr.fetch combination that > caused the problems, or whether it may have been write accesses > (reentry points for function calls, loop counters or whatever) > getting corrupted. It might be writes as well, good point. The thing just was that everything worked fine when debugging, but didn't when you just ran the program regularly. And as soon as I left out the BRAM portions during readback, everything was OK, so I assume it must've something to do with the readback interfering with the program execution in some way... cu, SeanArticle: 72407
Not sure what to do here. I ran the wizard for a Single DCM which generated a XAW file. Although this is a "New Source" it doesn't act like one. One can generate VHDL code from this XAW file which I did. I then tried to add the VHDL code as a source and got an error message. Something about a conflict between the two files. So I deleted the XAW file and now the VHDL file, by itself, seems to work, that is, it will synthesize and download. I haven't been able to verify the clock outputs yet. Is the XAW file suppose to be part of the project source?Article: 72408
> what PCI core are you using and why did you want to use DCM? It's a VHDL core, not one of X's cores. I wanted to use the DCM to remove clock delays that caused the design not to meet some timing constraints. > DCMs are not normally used in the PCI cores. I suppose it depends on the cores... > So may advice is: remove the DCM and get the core implemented in way that it > passes timing. My problem is that it doesn't pass. > the safest way always is to use one .UCF and text editor for the > constraints:) That's what I usely do. The only risk is to misspell some signal name. > .NCF and .PCF files sound like trouble... at least the .NCF does sometimes > make problem (with ChipScopePro) I didn't touch these, they are automatically generated (and that's why I am really puzzled) > recheck your design and reports again to see that the nets by that exact > name exist and have not been renamed and nothing isnt trimmed etc.. Why do you think I used the constraints editor and not a simple text editor? :o) I finally removed all the ISE-generated files (I only kept the VHDL, UCF and the NPL files) and reran the whole process and it worked fine. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 72409
On Fri, 13 Aug 2004 14:11:32 GMT, Subroto Datta <sdatta@altera.com> wrote: > You can use the free Quartus II Web Edition which has a good schematic > editor for Altera parts. But you should refrain from using records in your port declarations if you use it, because the tool can NOT handle them. Subroto, is this something Altera considers to include in the next version of Quartus? \Manfred -- A LE! gotcha :-)Article: 72410
You can get the Toshiba NAND flashes from digikey.com. Martin -- ---------------------------------------------- JOP - a Java Processor core for FPGAs: http://www.jopdesign.com/ "Student" <shinuda@hotmail.com> schrieb im Newsbeitrag news:7034ff0f.0408172044.3fa00292@posting.google.com... > Hi everyone, > > Can anyone tell me where can i buy NAND flash memory chips from? I am > interested in samsung ones, but any other NAND chip can be helpfull. I > can see them on samsung website but dont know how i can buy small > quantities of them given that i am in australia. > > thanksArticle: 72411
> The final result is 16bits which is being captured at 48kHz. > Currently I am using SignalTap and using this I'm able to capture a max of > 8k samples, however this is not enough (as RAM is finite) and I was > wondering is there anyway of real-time spooling this data back to PC? > > I'm using Nios Development Board (Cyclone FPGA) and ByteBlaster II. > You could use the PC-interface part of our 'dlk' system construction kit, capable of doing data rates about 400-500 Kbytes/sec via the PC parallel port. All components of the ' dlk ' system construction kit including the source code can be used free of charge for not commercial applications or for evaluation purposes. description see: http://www.seng.de/dlk_.html So if you have enough I/O´s left for implementing a parallel link to the PC, adapting our sources to Your (Cyclone) needs should do the work. with best regards, Peter Seng ############################# SENG digitale Systeme GmbH Im Bruckwasen 35 D 73037 Göppingen Germany tel +7161-75245 fax +7161-72965 eMail p.seng@seng.de net http://www.seng.de #############################Article: 72412
I'm working with a Nios II processor on an Altera fpga. Mostly, I'm doing fine, but there is one feature of the Eclipse interface to gdb that I seem to be missing - a gdb command window. There is a "nios2-gdb-server output" option for the Console window, but that's for output only. I want to be able to type my own commands. When using other gui front-ends for gdb, including gvd, insight and ddd, there is no problem doing this, but I can't find any way to get it in Eclipse. If I can't get this working, does anyone know of information about using gdb directly from the command line on the Nios2, such as references for the nios2-gdb-server parameters? -- David "I love deadlines. I love the whooshing noise they make as they go past." Douglas AdamsArticle: 72413
Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<4122353f$0$2518$ba620e4c@news.skynet.be>... > colin wrote: > > I would like to embed a device that has a PCI inteface with an FPGA > > (preferably a SPARTAN 3). > > > > Two questions have arisen before I start > > > > 1) Many PCI based chips (including the one I want to use) can be > > purchased as a PCI card to speed up development. I have had a good > > google without success but does anyone know of an FPGA development > > platform that includes a PCI card site, I could then develop the > > firmware without designing a PCB. > > By PCI site, you mean a slot where you can put PCI cards or a PCI edge so > that you can use it your FPGA board as a PCI device. > > Look at the avnet spartan 3 kit. I have it and it's real nice ;) > Err. You seem to have missed the point. I want to buy a PCI card with the silicon I want to use on it and plug it into an FPGA development board. The avnet card looks like just another FPGA based PCI card, I've googled and I've found many of them. My FPGA will be a high performance slave with just enough mastering to do the config cycles to the other chip (unfortunately the config registers reset to zeroe's else I wouldn't need to do this) and to set up the DMA's By the loud silence I assume the FPGA board I want doesn't exist.Article: 72414
ok, my mistake. I didnt tell that I had two linux image just to avoid any confusion. But I tried both the images (one with root=/dev/nfs and other with root=/dev/ram) and both hangs after "Now booting the kernel message". -raj "Peter Ryser" <peter.ryser@xilinx.com> wrote in message news:4122EBF2.4030304@xilinx.com... > Raj, > > just looking at the kernel command line I would say that these are two > different Linux kernels. In one case you try to boot from NFS in the > other from a RAM disk. > > - Peter > > > rajendra k singh wrote: > > Hi All, > > I am trying to boot linux on virtex 2 pro P7-ff672 board. My problem is > > that I am able to boot the linux image(ppc) on bitstream generated by EDK > > 6.1 but not with bitstream generated by EDK 6.2 (SP2). Does anyone had > > similar experience ? I wonder if the problem is EDK 6.2 or I need to change > > my liuux image which should not be the case as I am using the same version > > of cores. Following is the only message I get on bitstream generated by 6.2 > > EDK. > > > > loaded at: 00400000 0045D1E4 > > board data at: 0045A13C 0045A154 > > relocated to: 00405600 00405618 > > zimage at: 00405AFB 00459C4F > > avail ram: 0045E000 02000000 > > > > Linux/PPC load: root=/dev/nfs rw ip=on > > Uncompressing Linux...done. > > Now booting the kernel > > > > > > While the same Image produce following message on 6.1 bitstream > > > > loaded at: 00400000 005C71D0 > > board data at: 005C4128 005C4140 > > relocated to: 00405608 00405620 > > zimage at: 00405B24 0045A2AA > > initrd at: 0045B000 005C3E44 > > avail ram: 005C8000 02000000 > > > > Linux/PPC load: root=/dev/ram > > Uncompressing Linux...done. > > Now booting the kernel > > Linux version 2.4.18_mvl30-ml300 () (gcc version 3.2.1 20020930 (Mo > > ntaVista)) #7 Mon Mar 1 19:31:21 MST 2004 > > Xilinx Virtex-II Pro port (C) 2002 MontaVista Software, Inc. > > (source@mvista.com) > > > > On node 0 totalpages: 8192 > > zone(0): 8192 pages. > > zone(1): 0 pages. > > zone(2): 0 pages. > > Kernel command line: root=/dev/ram > > Xilinx INTC #0 at 0xD0000FC0 mapped to 0xFDFFEFC0 > > Calibrating delay loop... 299.82 BogoMIPS > > ........ > > > > Any pointers or suggesitions are appreciated. > > > > Thanks > > raj > > > > >Article: 72415
Hi all, If you have a Spartan-III development board and want to upload BIT files from Linux, you may want to check out JOLT (a GPL'ed program): http://www.science-and-technology.nl/research/jolt/ It differs from the recently announced program by Andrew Rogers in that it can upload BIT files directly, giving you a second alternative to complete your Linux-only Xilinx FPGA toolchain. JOLT resets the FPGA's perfectly; in fact, it emulates the proprietary IMPACT program bit-for-bit in the way it uploads the bit-image to the FPGA. This was achieved by recording and analyzing the JTAG stream as sent by IMPACT. A tidbit of useless info: it takes IMPACT (and JOLT) 1,699,882 jtag clocks to upload a X3S400 bit image, 1,699,136 of which are used to transfer the configuration data. JOLT _might_ work with Spartan-II / Virtex devices, but I don't have those available for testing. Also, it currently requires the FPGA to be the second JTAG chain device (the FPGA sits after the PROM on most modern dev. boards). Other coming attractions may include PROM programming. These requirements could easily be overcome if I had some more hardware available for testing, but alas (hint, hint...) Many kudos to my employer (Science and Technology BV in The Netherlands) for providing me the opportunity to work on this, and allowing distribution of this under the GPL. Best regards, and I'd appreciate your feedback, Sidney Cadot <cadot at science hyphen and hyphen technology dot nl>Article: 72416
Hello I am porting a PCI design from an Altera Stratix to a Xilinx Spartan3 and I am experiencing timing problems. I think the design is a bit underconstrained. Can somebody give me ISE equivalents for these Quartus constraints: FAST_INPUT_REGISTER FAST_OUTPUT_REGISTER TH_REQUIREMENT (probably something like IOBDELAY) DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS DECREASE_INPUT_DELAY_TO_OUTPUT_REGISTER I am also trying to figure out how to separate the clock-to-pad delays for the output enable and the output register paths. I only find the OFFSET = OUT ... AFTER constraint. I am using a FROM-TO but I feel this is not quite right. Thanks -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 72417
colin wrote: > Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com> wrote in message news:<4122353f$0$2518$ba620e4c@news.skynet.be>... > >>colin wrote: >> >>>I would like to embed a device that has a PCI inteface with an FPGA >>>(preferably a SPARTAN 3). >>> >>>Two questions have arisen before I start >>> >>>1) Many PCI based chips (including the one I want to use) can be >>>purchased as a PCI card to speed up development. I have had a good >>>google without success but does anyone know of an FPGA development >>>platform that includes a PCI card site, I could then develop the >>>firmware without designing a PCB. >> >>By PCI site, you mean a slot where you can put PCI cards or a PCI edge so >>that you can use it your FPGA board as a PCI device. >> >>Look at the avnet spartan 3 kit. I have it and it's real nice ;) >> > > Err. You seem to have missed the point. I want to buy a PCI card with > the silicon I want to use on it and plug it into an FPGA development > board. The avnet card looks like just another FPGA based PCI card, > I've googled and I've found many of them. > My FPGA will be a high performance slave with just enough mastering to > do the config cycles to the other chip (unfortunately the config > registers reset to zeroe's else I wouldn't need to do this) and to set > up the DMA's > > By the loud silence I assume the FPGA board I want doesn't exist. Look for a passive PCI backplane. I have one that came with a Intel dev board. SylvainArticle: 72418
Jim Granville wrote: > Eirik Seljelid wrote: > <snip> > >> Could be, but I suppose it would come up with an error message asking >> for valid keys or something like that. When I cutted down the source >> it would compile. > > > I haven't really set up an old dos environment yet so I > > think I will try this as soon as I get the time to do it. > > Sounds close - at this point I would try something trivial like > 8 NAND gates in a test file ( uses every pin ), and confirm you > get what looks like a valid JED file. > > >> AFAIK CUPL is a different HDL than Abel, which means I have to rewrite >> the source to CUPL syntax. My HDL programming experience is somewhat >> limited. I've written some PLD-cicuits in PALASM and another >> GAL-assembler called GALASM. Very basic, no high-level coding. >> Although I probably understand most of the code I'm really not so keen >> on translating it. The equipment using the FPLA also incorporates a >> serious amout of other PLD devices, mostly 22V10's and EP600's, all >> documented with Abel source code. > > > CUPL was suggested, should you hit a brick wall with ABEL, right now it > sounds more like a speed-bump..... :) > -jg > Finally got the time to set up a box with DOS. Didn't help much though. I guess you were right about the need for a licence key. It seems like it worked for smaller designs, perhaps for evaluation purposes. EirikArticle: 72419
Manfred, I am unclear by what you mean by records in port declarations in a achematic editor. Can you elaborate? - Subroto Datta Altera Corp. "Manfred Muecke" <manfred_dot._muecke@cern_dot._ch> wrote in message news:opscw4g0xqbo04fc@news.cern.ch... > On Fri, 13 Aug 2004 14:11:32 GMT, Subroto Datta <sdatta@altera.com> wrote: > > You can use the free Quartus II Web Edition which has a good schematic > > editor for Altera parts. > > But you should refrain from using records in your port declarations if you > use it, because the tool can NOT handle them. > Subroto, is this something Altera considers to include in the next version > of Quartus? > > \Manfred > > -- > A LE! gotcha :-)Article: 72420
On an embedded test-platform we have to configure a remote Altera Cyclone device via its JTAG chain. Our test-platform also has an Altera Cyclone fpga with a NIOS I SOC. We like to program the remote Cyclone via its JTAG. Right now we think the best method is to port the Altera Jrunner software to the NIOS I. Questions: 1- has anybody done this before (the NIOS port)? 2-what is the max.configuration time if using a .rbf from about 185KB?? 3-any other method suggested??? thanks Ron ProveniersArticle: 72421
Hi all,
Something that may be of interest when converting Verilog ASIC designs
to Xilinx FPGAs. I noticed this when trying to convert a customer's
ASIC design. When trying to set a clock to out constraint on an
output that is being driven by an inout (see sample below), the place
and route tool ignores the constraint, and gives the following msg:
WARNING:Timing:2667 - CLK does not clock data to metoo
WARNING:Timing:2666 - Constraint ignored: TIMEGRP "metoo" OFFSET = OUT
10 nS AFTER COMP "CLK" ;
//EXAMPLE CODE
module test (CLK, RST, ENABLE, IN, BIDIR, METOO);
input CLK, RST, ENABLE, IN;
inout BIDIR;
output METOO;
reg test_reg;
always @(posedge CLK or posedge RST)
if (RST)
test_reg <= 1'b0;
else
test_reg <= IN;
assign BIDIR = ENABLE ? test_reg : 1'bz;
assign METOO = BIDIR;
endmodule
I was able to get around it by making the following easy change.
//MODIFIED EXAMPLE
module test (CLK, RST, ENABLE, IN, BIDIR, METOO);
input CLK, RST, ENABLE, IN;
inout BIDIR;
output METOO;
reg test_reg;
always @(posedge CLK or posedge RST)
if (RST)
test_reg <= 1'b0;
else
test_reg <= IN;
assign BIDIR = ENABLE ? test_reg : 1'bz;
assign METOO = ENABLE ? test_reg : BIDIR;
endmodule
With all the constraints being checked, I was able to move on to some
"real" problems.
Article: 72422On Wed, 18 Aug 2004 14:05:29 GMT, Subroto Datta <sdatta@altera.com> wrote: > Manfred, I am unclear by what you mean by records in port declarations > in a achematic editor. Can you elaborate? Sorry for being imprecise. If you write a module in VHDL having records in its port declaration, Quartus does not allow to generate a symbol for it (which one might like to use in the schematics afterwards). I was told once, that this is due to limitations within the Quartus schematic editor. \Manfred -- A LE! gotcha :-)Article: 72423
Varun, Search the USPTO for our patents on BIST in PLD. Austin Varun Jindal wrote: > Hello , > > I am an engineering student and am working on testability issues in > FPGA devices. Can anybody throw light on the BIST schemes used by > Xilinx in their devices ; i.e. how do they achieve 100% fault > coverage;whether they use soft BIST or hard BIST. Any information will > be appreciated. Thanks in advance. > > Regds. > VarunArticle: 72424
############################################################################# # FIRST CALL FOR PAPERS # # International Workshop on Applied Reconfigurable Computing (ARC 2005) # # Algarve, Portugal, February 22, 2005 # # URL: http://w3.ualg.pt/~jmcardo/arc2005 # # held in connection with IADIS International Conference Applied Computing # (http://www.iadis.org/ac2005/) ############################################################################# Reconfigurable computing architectures are becoming especially important for many computing systems. Their use might lead to characteristics - such as high-performance, energy efficiency, and flexibility - not achieved by other forms of computing. Furthermore, these architectures can be an important support to microprocessors in the next generation of computing devices. With so many amenities, this has become an exciting and promising research area. This one-day workshop aims to bring together practitioners and researchers from academia and industry, especially interested on the use of reconfigurable computing platforms as the mechanism choice to perform computing. The workshop is an associated event of the IADIS International Conference Applied Computing 2005 and it will take place in Algarve on February 22, 2005. Algarve is located in the south of Portugal, bordered by the Atlantic ocean, and it is well known by its mild and mellow climate (with a radiant sun), beautiful and impressive beaches and landscapes, golf courses, delicious dishes (including seafood and fresh fish dishes), and a relaxed life style. TOPICS OF INTEREST: Suggested topics of interest include, but are not restricted to: - Methods and Tools (High-Level Compilers, Simulation, Estimation, Design space exploration, Languages to program reconfigurable systems, etc.) - Architectures (Fine-grained, coarse-grained, and mixed-grained, Multiprocessor-based reconfigurable platforms, Microprocessors with tightly-coupled reconfigurable hardware, etc.) - Applications (High-Performance Systems, Use of reconfigurable computing in embedded systems, robotics, digital signal processing, etc.) - Teaching reconfigurable computing - Surveys and Future Trends - Benchmarks (papers presenting benchmarks publicly available to be used by the reconfigurable computing community are especially welcome) SUBMISSIONS: Authors are invited to submit original work in the following formats: - Full papers (8 pages at the maximum): they should include mainly accomplished results; - Short papers (4 pages at the maximum): they should be mostly composed of work in progress reports or fresh development; - Posters (2 pages at the maximum); - One-hour tutorials: Tutorials can be proposed by scholars or company representatives. A proposal of maximum 250 words is expected. Submissions should be sent as an e-mail attachment in pdf format to: jmcardo@ualg.pt - in order to maintain a blind review no information about authors should be included in the papers being submitted - the format of the papers should be according to IADIS format rules - the email should include the title of the paper being submitted, the names and affiliations of the authors, and should identify if it is a full, short, poster, or tutorial submission. EVALUATION: - Each paper will be reviewed by at least three members of the program committee. IMPORTANT DATES: - Submission deadline: 15 October, 2004 - Notification to authors: 19 November, 2004 - Final Camera-Ready Submission and Early Registration: 3 December, 2004 - Late Registration: After 3 December, 2004 - Workshop: 22 February, 2005 PUBLICATION: - The proceedings of the workshop will be published as a book with ISBN and the papers will be included in the CD-ROM of the IADIS International Conference Applied Computing. WORKSHOP CHAIR: - Joao M. P. Cardoso, University of Algarve, Portugal, Email: jmcardo@ualg.pt PROGRAM COMMITTEE: - Antonio Ferrari, University of Aveiro, Portugal - Eduardo Marques, USP, Brazil - George Constantinides, Imperial College, UK - Gordon Brebner, Xilinx, USA - Hor=E1cio Neto, INESC-ID/IST, Portugal - Jos=E9 Nelson Amaral, University of Alberta, Canada - Jos=E9 Sousa, INESC-ID/IST, Portugal - J=FCrgen Becker, Universit=E4t Karlsruhe (TH), Germany - Marco Platzner, Swiss Federal Institute of Technology (ETH), Switzerland - Markus Weinhardt, PACT Informationstechnologie AG, Germany - Mihai Budiu, Carnegie Mellon University, USA - Milan Vasilko, Bournemouth University, UK - Nader Bagherzadeh, University of California, Irvine, USA - Pedro Diniz, University of Southern California/ISI, USA - Peter Athanas, Virginia Tech., USA - Peter Cheung, Imperial College, UK - Ranga Vemuri, University of Cincinnati, USA - Reiner Hartenstein, University of Kaiserslautern, Germany - Roger Woods, The Queen's University of Belfast, UK - Roman Hermida, Universidad Complutense, Madrid, Spain - Russell Tessier, University of Massachusetts, USA - Serge Vernalde, IMEC vzw, Belgium - Stamatis Vassiliadis, Delft University of Technology, The Netherlands - Tim Callahan, SRC Computers, USA - Wayne Luk, Imperial College, UK WORKSHOP SECRETARIAT - secretariat@iadis.org
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