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Messages from 43600

Article: 43600
Subject: How can I create an encrypted netlist for Altera?
From: Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com>
Date: Sun, 26 May 2002 21:32:41 -0500
Links: << >>  << T >>  << A >>
        I primarily use Xilinx's software for an IP core development.
One nice thing (From my perspective) about Xilinx's software is that
when a design in EDIF netlist gets read by NGDBUILD, NGDBUILD invokes
EDIF2NGD which converts an EDIF netlist to a Xilinx proprietary format
called NGO (Native Design Object).
I am sure some people hate a proprietary design file format, but from my
perspective as an IP core developer, it is desirable since almost no one
will be able to obtain the original EDIF netlist which is highly
portable.
Although I am not a huge fan of Altera, largely because I have had lots
of bad experiences with MAX+PLUS II-BASELINE and Quartus II Web Edition,
I do still have some interest in porting my IP core to Altera's devices.
So, my question is, how can I convert an EDIF netlist generated by
LeonardoSpectrum-Altera (I hate that tool, too, because the GUI is
buggy, but it's free, and can generate an EDIF netlist.) to an encrypted
Altera proprietary format like what I did with Xilinx's software?



Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)

Article: 43601
Subject: automatically generate timing diagrams
From: d2fabrizio@aol.com (Dan Fabrizio)
Date: 26 May 2002 19:54:14 -0700
Links: << >>  << T >>  << A >>
Hello All,

I'm collecting ideas for timing diagrams that are commonly used. 
I will include them with the TimingAnalyzer.

The timing diagrams are automatically generated with manufacturer
delays and constraints. The user can add the particulars for the
design under consideration to the diagrams and quickly perform timing
analysis. 

Please email me with any timing diagram needs related to standard
bus interfaces, like PCI, VME, ....

Thanks,
Dan Fabriziio

dfabrizio11@comcast.net

The TimingAnalyzer:   www.timinganalyzer.net

Article: 43602
Subject: Re: Xilinx chip scope: Comments
From: kayrock66@yahoo.com (Jay)
Date: 26 May 2002 20:58:05 -0700
Links: << >>  << T >>  << A >>
While there is no substitute for using simulation to find bugs,
sometimes there is no substitute for viewing the real system operate. 
Get it, it rocks.  You'll wonder how you lived without it.  I use it
with the USB cable, and get an error every time I connect, but after
that it seems to work alright.  Also, sometimes while waiting for a
trigger, it will false trigger and provide no trace data.

p.s. I think the Altera equivalent product is included free with
Quartus 2.


"H.L" <alphaboran@yahoo.no-spam.com> wrote in message news:<aci7ln$1k7l$1@ulysses.noc.ntua.gr>...
> Hello all,
> I have read few weeks ago in xilinx site about the Chip Scope, seems like a
> good solution for testing a FPGA. I am thinking to purchase it but first I
> would like some comments about this tool from someone who have used it. Can
> someone help me on this?
> 
> Greetings,
> Harris

Article: 43603
Subject: Re: P&R times
From: kayrock66@yahoo.com (Jay)
Date: 26 May 2002 21:13:13 -0700
Links: << >>  << T >>  << A >>
The P&R times seem to go up exponentially after you cross a certain
design density threshold.  Our experence has been that our time was
better spent doing logic reduction to get back behind knee in the
curve instead of twiddling the control knobs or building faster
machines.

Can you convert any of those distributed rams to block ram?

Regards

"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<acdjad$otrng$1@ID-84877.news.dfncis.de>...
> Hello,
> 
> we have a design with a XCS30XL, which is utilized to 96%.
> Bad thing is, P&R takes about 30!!! minutes on a Athlon 500. The design uses
> a lot of TBUFs and DP-RAMS.
> Are there some tricks to speed up things? Some floorplanning? Timing
> constraints?

Article: 43604
Subject: Re: SOPC for machine vision
From: "Victor Schutte" <victors@mweb.co.za>
Date: Mon, 27 May 2002 06:41:38 +0200
Links: << >>  << T >>  << A >>
Resolution?
Colour?
Frame?
Format of video (PAL,NTSC,CCIR)? Keep in mind that there are nice CMOS (DRAM
like) sensors available (e.g. from HP- go to www.beyondlogic.org ) that will
nicely interface with a large and fast FPGA.

What is your output from the system (modified picture, pattern, "The object
is a ..." type output,  megabytes of data pouring out the other side per
second....)?

SOPC solution? I am using NIOS (very impressed with it) but my current board
can only do about 50MIPS per CPU  (with the Stratix chips Altera promises
125MHz but I have not verified this). With a 20k100 I can get in 1 CPU, with
a 20K1000 roughly 12 CPUs (but with a serious number of pins and bus
mastering) .  With NIOS 2.x you can have multiple masters but I don't thinks
you will easily reach 1000MIPS. They also have  ARM and MIPS in the
Excalibur series running a single 166MHz (~MIPS).

Memory requirements?

Final size of product?

Selling price? (profit margin)

How many will you be able to sell (market)?

How much time do you have to develop?


1000MIPS? Do you also require floating point?  Can you implement some of the
functions in logic (e.g. hardware FFT instead of software FFT)? I have seen
several high end systems (many MIPS) going down to a couple of specialized
chips with a 8051 driving it, so by designing you system correctly you might
not need 1000MIPS.

I think you should first build a NON SOPC system (e.g. a Windoze PC with a
grabber card) and sort out where your problems/bottlenecks are.



Victor


"Manfred Muecke" <Manfred.Muecke@NOevkSPAM.co.at> wrote in message
news:3cee528f.22292316@news.inode.at...
> On Fri, 24 May 2002 16:33:14 +0200, Laurent Gauch
> <laurent.gauch@amontec.com> wrote:
>
> >Which video interface do you want, 1394, s-video or other ?
> CameraLink would be perfect.



Article: 43605
Subject: Re: XC4000 series pin compatability
From: Andreas Wassatsch <wassatsch@mppmu.mpg.de>
Date: Mon, 27 May 2002 08:16:25 +0200
Links: << >>  << T >>  << A >>
This is a multi-part message in MIME format.
--------------0A543C7FA9B1B2671836C353
Content-Type: text/plain; charset=us-ascii
Content-Transfer-Encoding: 7bit

Hi,

there is a device family from atmel (at40k), which is pin-compatible to
the 40xxe in a pc84 package with the advantage of a higher possible gate
count.

the atmel p&r tools can do his job on a synthesised netlist for the
xc40xxe series.


Article: 43606
Subject: Re: evaluation boards for virtex
From: "Felix Bertram" <f.bertram@trenz-electronic.de>
Date: Mon, 27 May 2002 08:25:45 +0200
Links: << >>  << T >>  << A >>
> We are going to use Virtex(-E) device. In order to get
> start to Xilinx, I need help with evaluation boards
> with Virtex-e.

The Xilinx Virtex family of devices utilizes the same architecture as the
Spartan-II family of devices, both families even use the same synthesizer.
The same relationship is true for Virtex-E vs. Spartan-IIE. As Spartan-II is
fully supported by the free Xilinx WebPack ISE software, there are a lot of
Spartan-II based boards out there.

> Actually, I am looking for the Xilinx counterparts of the
> following Altera boards,
>
> 2-) Altera SOPC board.


we just introduced our new FPGA development board which should be similar to
what you are looking for. The board is based upon a 300k-gate Spartan-IIE,
which is accompanied by the following peripherals:
- 256kx16 SRAM
- 512kx16 Flash
- 2x16 LC-display
- USB interface
- RS232 interface
- VGA output
- VG96 connector

For a convenient desktop or laboratory setup, the board is powered and
configured via USB. The Flash memory is used to store non-volatile
configurations and data. The board fits into industry-standard 19" racks
with VG96 connector. For easy expansion, there are up to 100 user I/Os with
may be assigned freely.

For further information, refer to the following links:
http://www.trenz-electronic.de/prod/proden12.htm
http://www.trenz-electronic.de/prod/proden10.htm
http://www.trenz-electronic.de/prod/ps-TE-XC2Se.pdf


The board is in stock and may be ordered via our online shop. We offer
discounts for orders of two or more boards. Contact us!

Best regards

Felix
_____
Dipl.-Ing. Felix Bertram
Trenz Electronic GmbH
Brendel 20
D - 32257 Buende
Tel.: +49 (0) 5223 4939755
Fax.: +49 (0) 5223 48945
Mailto:f.bertram@trenz-electronic.de
http://www.trenz-electronic.de




Article: 43607
Subject: footprint competabilty in virtex-II devices
From: nahum_barnea@yahoo.com (Nahum Barnea)
Date: 26 May 2002 23:44:51 -0700
Links: << >>  << T >>  << A >>
Hi.
I oredered virtex-II in FF1152 package and I see that the lead time are long,
I fear it will delay the integration of my project.

I read in xilinx site that FF1152 and FF896 are footprint compatible.

Does it mean that I can use avaliable FF896 device or do I need to do
special adjustments ??

Bye,
Nahum.

Article: 43608
Subject: Re: SOPC for machine vision
From: Manfred.Muecke@NOevkSPAM.co.at (Manfred Muecke)
Date: Mon, 27 May 2002 09:27:33 GMT
Links: << >>  << T >>  << A >>


>1000MIPS? Do you also require floating point?  Can you implement some of the
>functions in logic (e.g. hardware FFT instead of software FFT)? I have seen
>several high end systems (many MIPS) going down to a couple of specialized
>chips with a 8051 driving it, so by designing you system correctly you might
>not need 1000MIPS.
Sorry, I was unspecific about the 1000MIPS. Implementing the algorithm
in a DSP requires a computing power of about 1000MIPS (no floating
point). Most of the instructions are needed for image pre-processing
which can be transferred to logic. As an estimate, a combined system
FPGA+DSP would need a computing power of only 100-200MIPS.
The embedded ARM in the Excaliburs most propably fits my needs (I
haven't yet checked the PPC Xilinx uses in the VIRTEX II Pro), that is
why I consider a combined system.
What I need is the freedom to use the same board for different tasks
which are quite similiar in structure and required computing power but
differ in the final algorithm to be implemented. I think for using
specialized chips (such as for FFT) the needed MIPS are too low and
the required diversity is to high. DSP+FPGA as separate chips would be
a solution, but a SOPC would be a better one (interfaces, board,
flexibility).


>I think you should first build a NON SOPC system (e.g. a Windoze PC with a
>grabber card) and sort out where your problems/bottlenecks are.
Done. The bottleneck is that I wasn't able to find a board for image
processing using a SOPC although I think that it would be the perfect
platform for my needs.

>What is your output from the system 
Just a few good/bad decissions



\Manfred

Article: 43609
Subject: Re: How can I create an encrypted netlist for Altera?
From: Rene Tschaggelar <tschaggelar@dplanet.ch>
Date: Mon, 27 May 2002 12:23:50 +0200
Links: << >>  << T >>  << A >>
Impressive list of groups you wrote to - I'll respond to one.
What makes you so sure your IP is protected with a proprietary
format ? Were you able to set a private key ?

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Kevin Brace wrote:

>         I primarily use Xilinx's software for an IP core development.
> One nice thing (From my perspective) about Xilinx's software is that
> when a design in EDIF netlist gets read by NGDBUILD, NGDBUILD invokes
> EDIF2NGD which converts an EDIF netlist to a Xilinx proprietary format
> called NGO (Native Design Object).
> I am sure some people hate a proprietary design file format, but from my
> perspective as an IP core developer, it is desirable since almost no one
> will be able to obtain the original EDIF netlist which is highly
> portable.
> Although I am not a huge fan of Altera, largely because I have had lots
> of bad experiences with MAX+PLUS II-BASELINE and Quartus II Web Edition,
> I do still have some interest in porting my IP core to Altera's devices.
> So, my question is, how can I convert an EDIF netlist generated by
> LeonardoSpectrum-Altera (I hate that tool, too, because the GUI is
> buggy, but it's free, and can generate an EDIF netlist.) to an encrypted
> Altera proprietary format like what I did with Xilinx's software?
> 


Article: 43610
Subject: Re: FPGA, VHDL : RAM initialization
From: Martin <>
Date: Mon, 27 May 2002 03:49:16 -0800
Links: << >>  << T >>  << A >>
When you want to initialise the contents to '0' then you're fine off as this is done by default.
So you just need to initialise the RAM for functional simulation.

But if you'd like to initialise the RAM with some values different from '0' you have to do some more work. 
a) init for simulation
b) init for synthesis
see the code below:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--pragma translate_off
--unisim library for simulation. Here a behavioural model of the BRAM is stored.
library unisim;
use unisim.vcomponents.all;
--pragma translate_on

entity brama is
    Port ( clk, we, en : in std_logic;
	 di1:in std_logic_vector(3 downto 0);
	 		addr: in std_logic_vector(9 downto 0);
	 		addr2: in std_logic_vector(9 downto 0);
	 		dummy:out std_logic;
				data: out std_logic_vector(3 downto 0);
				data2: out std_logic_vector(3 downto 0)				
				);

end brama;

architecture Behavioral of brama is

component RAMB4_S4
-- synopsys translate_off

--declaration of the RAM-contents to have some pre-laoded values. These values will be 
--used for SIMULATION in all components if they are not overridden by direct values for
--the instantiated component.
  generic (
       INIT_00 : bit_vector := X"AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
       INIT_01 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_02 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_03 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_04 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_05 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_06 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_07 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_08 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_09 : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0a : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0b : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0c : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0d : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0e : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
       INIT_0f : bit_vector := X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF");

-- synopsys translate_on

port (DI     : in STD_LOGIC_VECTOR (3 downto 0);
        EN     : in STD_logic;
        WE     : in STD_logic;
        RST    : in STD_logic;
        CLK    : in STD_logic;
        ADDR   : in STD_LOGIC_VECTOR (9 downto 0);
        DO     : out STD_LOGIC_VECTOR (3 downto 0)); 
end component;

attribute INIT_00: string;
attribute INIT_01: string;
attribute INIT_02: string;
attribute INIT_03: string;
attribute INIT_04: string;
attribute INIT_05: string;
attribute INIT_06: string;
attribute INIT_07: string;
attribute INIT_08: string;
attribute INIT_09: string;
attribute INIT_0a: string;
attribute INIT_0b: string;
attribute INIT_0c: string;
attribute INIT_0d: string;
attribute INIT_0e: string;
attribute INIT_0f: string;
   
--pre-loaded values for BRAM myBRAM. These will be the ones used for synthesis
attribute INIT_00 of myRAMB : label is "AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
attribute INIT_01 of myRAMB : label is "FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF";
attribute INIT_02 of

Article: 43611
Subject: Why there is no clear signal in BRAM?
From: muthu_nano@yahoo.co.in (Muthu)
Date: 27 May 2002 06:05:42 -0700
Links: << >>  << T >>  << A >>
Hi,

In virtex-II block RAMs, reset signal is there. that will reset the
output bus value to all "zeros" after giving reset. But it is
understood that, it will not affect the Memory cell contents.

In most of the situations, during running time we need to clear the
memory contents. But there is no provision, in BRAM to clear the
memory contents of the BRAM. So, we have to waste the more memory
write cycles, to make the memory cell contents to zeros.

My question is: Why there is no clear bit in BRAM? Is that possible or
not?

Is any other memories (other than virtex_II, BRAM), having a clear bit
like this ?

Thanks in advance.

Best regards,
Muthu

Article: 43612
Subject: ALtera SOPC Builder
From: Georg Heinrich <Georg.Heinrich@eas.iis.fhg.de>
Date: Mon, 27 May 2002 15:30:07 +0200
Links: << >>  << T >>  << A >>
Hi Folks,
I am just wrtiting my thesis concerning HW-SW-Codesign and related stuff and need some
expieriences about the SOPC Builder from Altera and the target architectures Excalibur
(NIOS & ARM).

If anybody uses the SPW-development-System from Cadence or the Innoveda
System-Level-Design-Tools :

Any Hints & Storys appreciated

Best regards from Dresden

Georg

--
#  mail from: Georg Heinrich                #
#  mailto:    Georg.Heinrich@eeaass.iiiiiss.ffhhgg.de #
#  visit:     http://www.xgeorg.de          #
#############################################




Article: 43613
Subject: Re: Small FIFOs in Spartan
From: "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no>
Date: Mon, 27 May 2002 17:12:43 +0200
Links: << >>  << T >>  << A >>
Thanks for your replies,

My application is an audio oversampler. I parallelize the design to the
point where I can have 3 or 4 MAC units working in parallel. Each MAC has a
coefficient ROM and a data RAM. The FIFOs are just there to pass data
between MACs working in parallel. The RAM cells don't need to be awfully
large, 256 words of 24 bits is likely to be the largest one. The smallest is
probably around 16 words of 24 bits. And yes, there are 24x24 or 24x20 bit
MACs in there.

I plan to put this in a Spartan or Spartan IIE. I'll need a lot of logic, it
seems, but with just a few DAC chips using series data, the IO need is
actually minimal. The reason I wrote Spartan instead of SpartanII is that
I'm a little afraid of BGA mounting. That's one thing I can't do with my SMD
iron and microscope.

Regards,
BÝrge

"Ulf Samuelsson" <ulf@atmel.REMOVE.com> wrote in message
news:4dJH8.354$t4.824@nntpserver.swip.net...
> "BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> skrev i
> meddelandet news:1022230585.37631@halvan.trd.sintef.no...
> > I will need some really small FIFOs for my next project. The word length
> > will be 24 bits, but the depth of the FIFO is not requirred to be more
> than
> > two to sixteen.
> >
> > Could dedicated parts of the Spartan be used for such small FIFOs? I
plan
> to
> > program the thing in VHDL.
> >
> > Regards,
> > BÝrge
> >
> >
>
> This is an excellent application for the Atmel AT40K.
> For each 16 macroblocks, you have a small Dual Port RAM 32 x 4.
> The H/W Macrogenerator can be used to create a 32 x 24 FIFO.
> You will have 16 of the 32x4 DP SRAMs in the smallest 5 k gate FPGA,
> (Only 12 can be used as DPRAM though)
> If you need more than two FIFOs then there are larger FPGAs available.
>
> Maybe you could also use the FPSLIC which has an internal AVR processor.
>
> --
> Best Regards
> Ulf at atmel dot com
> These comments are intended to be my own opinion and they
> may, or may not be shared by my employer, Atmel Sweden.
>
>
>



Article: 43614
Subject: request for vcd and Symphony 1.5 lst files
From: "Dan Fabrizio" <dfabrizio11@comcast.net>
Date: Mon, 27 May 2002 15:16:56 GMT
Links: << >>  << T >>  << A >>
Hello all,

I have developed a waveform viewer for Symphony version 1.5 ( free version )
and
VCD files.  It is written with Tcl/Tk and C.  The intention is to use this
program
to translate user selected parts of the vcd and lst file into .tim for the
TimingAnalyzer.

I'm looking for Symphony lst and vcd files to do as much testing as
possible.
The program will available for anyone to use after I complete testing and
debugging.

If you have ideas for improvements or new features, let me know.

Please email any files to dfabrizio11@comcast.net

Website:   www.timinganalyzer.net

Thanks in advance,
Dan Fabrizio





Article: 43615
Subject: Re: ALtera SOPC Builder
From: Prager Roman <rprager@frequentis.com>
Date: Mon, 27 May 2002 16:05:18 GMT
Links: << >>  << T >>  << A >>
Georg Heinrich <Georg.Heinrich@eas.iis.fhg.de> wrote:
> Hi Folks,
> I am just wrtiting my thesis concerning HW-SW-Codesign and related stuff and need some
> expieriences about the SOPC Builder from Altera and the target architectures Excalibur
> (NIOS & ARM).
Well, I am using it. What kind of information do you exactly want to hear?
I use the NIOS core, until now I did not use the Mercury devices.
One of my biggest problems is that the NIOS core consumes too much space in the
FPGA. Therefore it is much cheaper to use an external microcontroller if you
are not just doing prototyping. 
However, I think the idea of the SOPC- builder is really great. It is quite
easy to implement a working system within very short time. 
Maybe with the new Stratix- Devices the chip ressources are no longer such an
issue and I can use the NIOS core for volume production, too.


> If anybody uses the SPW-development-System from Cadence or the Innoveda
> System-Level-Design-Tools :

No, I do not use these.

> Any Hints & Storys appreciated

> Best regards from Dresden

> Georg

Regards from Vienna
Roman

> --
> #  mail from: Georg Heinrich                #
> #  mailto:    Georg.Heinrich@eeaass.iiiiiss.ffhhgg.de #
> #  visit:     http://www.xgeorg.de          #
> #############################################




Article: 43616
Subject: Re: State machine synthesis
From: "Phil Connor" <philip_john_connor@hotmail.com>
Date: Mon, 27 May 2002 16:35:15 +0000 (UTC)
Links: << >>  << T >>  << A >>
"Robert O. Taniman" <bobchen74@yahoo.com> wrote in message
news:abjqkg$ck0$1@dinkel.civ.utwente.nl

Hi Robert,

Apologies, only just seen your post....

Timing on Xilinx is worst case ie. everything going against you.

So if your timing is only just marginal it may work fine on real
hardware until the temperature rises or the voltage drops etc.

Hope this helps

Regards

Phil






-- 
Posted via Mailgate.ORG Server - http://www.Mailgate.ORG

Article: 43617
Subject: Re: Why there is no clear signal in BRAM?
From: Muzaffer Kal <kal@dspia.com>
Date: Mon, 27 May 2002 16:36:48 GMT
Links: << >>  << T >>  << A >>
On 27 May 2002 06:05:42 -0700, muthu_nano@yahoo.co.in (Muthu) wrote:

>Hi,
>
>In virtex-II block RAMs, reset signal is there. that will reset the
>output bus value to all "zeros" after giving reset. But it is
>understood that, it will not affect the Memory cell contents.
>
>In most of the situations, during running time we need to clear the
>memory contents. But there is no provision, in BRAM to clear the
>memory contents of the BRAM. So, we have to waste the more memory
>write cycles, to make the memory cell contents to zeros.
>
>My question is: Why there is no clear bit in BRAM? Is that possible or
>not?

Virtex-II block rams are regular SRAM blocks which have a very high
density. Putting a reset pin into each cell would significantly cut
down on the density so it is undesirable.
If you do a careful design, you don't need to clear memories. Try to
communicate between the state machines which write to and read from
the brams so that no location is read from before it was written. If
your state machines are reset and synchronized, you should almost
never need cleared memory.

Muzaffer Kal

http://www.dspia.com
ASIC/FPGA design/verification consulting specializing in DSP algorithm implementations

Article: 43618
Subject: Re: static vs gate-level timing analysis
From: Utku Ozcan <utku.ozcan@netas.com.tr>
Date: Mon, 27 May 2002 19:49:05 +0300
Links: << >>  << T >>  << A >>
"Robert O. Taniman" wrote:

> Just a short question from a newbie (me): what is the difference between
> static timing analysis and gate-level timing analysis?
>
> Robert

I want to play with order of the words in your question:

Why does Xilinx put STA after MAP, in Flow Engine by default?

My answer: Before PAR, it is good that the tool warns you that some portion
of your chip consists of many logic levels. If there is too many logic level
that anyway cannot pass STA after MAP, then it is no use of running PAR.
PAR runs much longer than MAP does, so it saves your design cycle time
at the expense of additional tool run.

Utku

PS: STA = Static Timing Analysis



Article: 43619
Subject: Re: Synchronous Single Clock Designs
From: "gosensgo@goober_lumictech.com" <gosensgo@GOOBERlumictech.com>
Date: Mon, 27 May 2002 16:54:13 GMT
Links: << >>  << T >>  << A >>
I think he was referring to internal tristates. A bi-directional databus
at the pads can be realized from two unidirectional internal busses
(a read and write bus).

"Fabio G." <9+3@supereva.it> wrote in message
news:3cef83cb.5712756@powernews.inwind.it...
> Rick Filipkiewicz <rick@algor.co.uk> ha scritto:
>
> >that makes ASIC vendors dislike tristates
>
> So in ASIC data bus can not be realized?
>
> --
> Per rispondermi via email sostituisci il risultato
> dell'operazione (in lettere) dall'indirizzo.



Article: 43620
Subject: Re: Small FIFOs in Spartan
From: "Falk Brunner" <Falk.Brunner@gmx.de>
Date: Mon, 27 May 2002 19:32:26 +0200
Links: << >>  << T >>  << A >>
"BÝrge Strand" <borge.strand.remove.if.not.spamming@sintef.no> schrieb im
Newsbeitrag news:1022512364.16393@halvan.trd.sintef.no...

> actually minimal. The reason I wrote Spartan instead of SpartanII is that
> I'm a little afraid of BGA mounting. That's one thing I can't do with my
SMD
> iron and microscope.

Spartan-II is available up to 200k in PQ208. Spartan-IIE even 300k

--
MfG
Falk





Article: 43621
Subject: Re: Altera 10K30A240C-1
From: "Tuomo Auer" <tuomo.auer@removethis.hut.fi>
Date: Mon, 27 May 2002 20:40:52 +0300
Links: << >>  << T >>  << A >>
Have you looked form EBV Elektronik  www.ebv.com Price of EPF10K30AQC2403 is
72.31 euros.

--
Tuomo Auer

"Salman Sheikh" <sheikh@pop500.gsfc.nasa.gov> wrote in message
news:aciojs$70i$1@skates.gsfc.nasa.gov...
> Hello,
>
> Anyone know where I can get one of these chips for cheap?  Arrow.com looks
> like the only place to buy the -3 speed part.
>
> Thanks.
>
> Salman
>


Article: 43622
Subject: XC95288 Programming
From: hanksdejanews@hotmail.com (Hanks Lee)
Date: 27 May 2002 13:43:56 -0700
Links: << >>  << T >>  << A >>
Hi Experts,

I'm new to CPLD in-system-programming. We use the method metioned in
Xilinx App-note xapp058. We could successfully covert the svf code to
xsvf code, however we could not program the device with their
playxsvf.exe. An error was shown at the end of programming. We can Get
Device ID, Erase, Blank Check the device with playxsvf.exe. Does
anybody encounter this kind of problem before? Did we do something
wrong?

Thanks,

Hanks

Article: 43623
Subject: Re: How can I create an encrypted netlist for Altera?
From: Petter Gustad <newsmailcomp2@gustad.com>
Date: Mon, 27 May 2002 22:06:28 GMT
Links: << >>  << T >>  << A >>
Kevin Brace <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> writes:

> So, my question is, how can I convert an EDIF netlist generated by
> LeonardoSpectrum-Altera (I hate that tool, too, because the GUI is
> buggy, but it's free, and can generate an EDIF netlist.) to an encrypted
> Altera proprietary format like what I did with Xilinx's software?

Is the NGD file actually encrypted? I thought it was only an
undocumented binary format?

I've just used Synopsys FPGA Compiler II to create an EDIF netlist
which was read into Quartus II (I like the TCL support). An immediate
EQN file is created which is neither binary or encrypted, but I would
describe it as "obfuscated".

Would it be possible for you to distribute your core with the Altera
IP core program? There must already be a mechanism to protect your IP.
I know that you can download and simulate some of the IP's. Other's
like the Altera PCI core you can even upload to a device, but it will
only operate for two days or so. That's what I call try before you
buy.

Petter
-- 
________________________________________________________________________
Petter Gustad   8'h2B | (~8'h2B) - Hamlet in Verilog   http://gustad.com

Article: 43624
Subject: Re: footprint competabilty in virtex-II devices
From: mrand@my-deja.com (Marc Randolph)
Date: 27 May 2002 16:53:33 -0700
Links: << >>  << T >>  << A >>
nahum_barnea@yahoo.com (Nahum Barnea) wrote in message news:<fc23bdfc.0205262244.6de99161@posting.google.com>...
> Hi.
> I oredered virtex-II in FF1152 package and I see that the lead time are long,
> I fear it will delay the integration of my project.
> 
> I read in xilinx site that FF1152 and FF896 are footprint compatible.
> 
> Does it mean that I can use avaliable FF896 device or do I need to do
> special adjustments ??


If you didn't use the outer two rows of the FF1152 for I/O, you can
drop the FF896 onto the center pads of the FF1152.

Have fun,

   Marc



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