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"Brian Davis" <brimdavis@aol.com> wrote in message news:a528ffe0.0410191907.7dea9fd4@posting.google.com... > Symon wrote: > > < re. the missing leaded package SSO data > >> >>That's because the lead frame has buggered your SI before >>you've even started your PCB. >> > > Yes, and the poorer on-die power distribution of those > same leadframes makes adhering to those (missing) SSO > guidelines even more important than in the BGA parts. > V. good point. I wonder, do the IBIS models include the lead frame? >> >>The idea is that if the voltage mode drivers switch >>simultaneously in opposite directions, the current through >>the Vcco pins stays constant, so the lead/trace inductance >>doesn't screw things up. >> > > Xilinx has two flavors of differential driver: > > 1) the older style, voltage-mode, pseudo-differential, > switch-two-CMOS-outputs-with-an-external-resistive-attenuator > > which they say doesn't balance that well : > http://www.fpga-faq.com/archives/42700.html#42709 > > 2) the 'real' balanced current-mode drivers of the V2/V2P/S3, > which the Answer Records say is not a factor in SSO limits > > So, I'd expected to see much better SSO numbers for the 'real' > LVDS drivers than for the older 'pretend' ones, but DS099, table 23, > says both types have a four-pair SSO limit per VCCO-GND pair. > > > Brian I got the difference between the two types, but failed to realise that they didn't balance so well. Thanks for the link you posted to Bob and Austin's exchange, I'm thinking again. I guess I'm very cynical, I think the "25 ps to 125 ps" time from the pad to the pin is a red herring. The synchronicity of the IOBs outputs switching on the die is what's important. Maybe the 'gate' or drive capacitance of the output transistors added to the bounce? Maybe a tiny bit! I guess that leaves the crossover current, but how long does that last? I thought the output structure stopped that happening. CMOS, right? And how did they measure it? Hmmm! Cheers, Syms.Article: 74826
"Davis Moore":
> Jan Bruns wrote:
> > A more important example is the SRL16 and RAM16X1S primitives. Again,
> > it's "map" reporting, that SRL16 + RAM16X1S aren't supported on F-LUT
> > of a slice on SpartanII, although the SpartanII Data Sheet
> > unmistakeable states:
> > | In addition to operating as a function generator, each LUT can
> > | provide a 16 x 1-bit synchronous RAM. [...]
> > | The Spartan-II LUT can also provide a 16-bit shift register
> > | that is ideal for capturing high-speed or burst-mode data.
> A LUT RAM can be implemented in the F LUT of a SLICE
> as long as there is also a LUT RAM in the G LUT of the same
> SLICE. The F LUT RAM hardware is dependent on the G LUT
> RAM and can not independently support a LUT RAM. This
> is true for shift registers as well.
Ok, that's what "map" seems to be trying to tell us (I'll append it's words
below). But isn't that far away from what one could expect to be a hardwired
limitation? Say there is a Slice-internal routing resource, that connects
F1-4 with G1-4, just to safe global routing resources, when in RAM32X1-mode.
Let's further assume, these 4 connects are enabled by only one configuration bit.
What might be a practical reason to share this bit with "RAM-F used" (wich might
not even exist), instead of sharing it with "MUX5 used"?
After having read the xdl output (not parsed throughly, of course), it seems to
me, that there simply isn't even such a "safe global routing resources when using
ram32x1"-feature of that kind.
Gruss
Jan Bruns
________________________________________
ERROR:Pack:1118 - The symbol luf_1 was unable to be implemented in a Slice
containing no other symbols. RAM cannot be placed in F in RAM 16x1 or 1SHIFT
mode. Check that the constraints on this symbol make sense in isolation.
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset,
RLOC=R0C0.S0) which require the combination of the following symbols into a
single SLICE component:
RAM symbol "luf_1" (Output Signal = o1_OBUF)
LUT symbol "lug_1" (Output Signal = o2_OBUF)
RAM cannot be placed in F in RAM 16x1 or 1SHIFT mode. Please correct the
design constraints accordingly.
ERROR:Pack:679 - Unable to obey design constraints (MACRONAME=hset,
RLOC=R0C0.S0) which require the combination of the following symbols into a
single SLICE component:
RAM symbol "luf_1" (Output Signal = o1_OBUF)
RAM symbol "lug_1" (Output Signal = o2_OBUF)
The address signals must match exactly when using both F and G in RAM mode.
Please correct the design constraints accordingly.
Article: 74827Symon wrote: > "Johan Bernsp=E5ng" <xjohbex@xfoix.se> wrote in message > news:cl2g6r$fn7$1@mercur.foi.se... >=20 >=20 >>Well, it's a quite large design sampling the input at 200 MHz (from an >>ADC), CIC filters, LP FIRs, CORDIC, BP FIRs etc. I.e. lots of >>calculations for my poor ModelSim. >=20 >=20 > Of course, you simulated each of these blocks separately to verify they= > worked? ;-) > Cheers, Syms. >=20 >=20 >=20 Actually, no I didn't. I used ChipScope and a real input source to the=20 system. Since the filter blocks are from CoreGen, as well as the CORDIC, = I wouldn't get more information about the internal signals from a=20 simulation as I get from ChipScope. Cheers --=20 ----------------------------------------------- Johan Bernsp=E5ng, xjohbex@xfoix.se Research engineer, embedded systems Totalf=F6rsvarets forskningsinstitut Swedish Defence Research Agency Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 74828
The main thing is to make sure setup and hold times are kept in check. It will also work faster if all the signals are generated from the same chip or you use bidirectional handshaking. If your trying bi-directional coms... an LVDS seralizer would probably be better... differential and fewer signals. "Avin" <avin11@hotmail.com> wrote in message news:30b48c91.0410192023.42dd4d5@posting.google.com... > Hi, > > I am trying to enable commmunication between two FPGAs, both being the > Stratix 1S40 on the Nios Stratix Boards. One chip implements a > controller while the other implements a datapath. I am trying to > provide control signals to the datapath-chip from the controller-chip > and retrieve back the output from the datapath-chip back to the > controller-chip. For this, I have assigned the outputs and inputs to > the pins of the Proto connnectors on the board and used the LVTTL IO > standard. For some reason, the communication doesn't seem to take > place. Subsequently, the connection between the FPGAs is then done > through IDE cables connected to the 40 pin Proto FDCs. Any settings > that I should be aware of when attempting to enable communication > through Proto connector pins..? > > Thanks.Article: 74829
>That's because the lead frame has buggered your SI before you've even >started your PCB. Then why does Xilinx sell the chips? They must be good for something. Maybe there is a comment in some ap-note that says not to bother trying to implement PCI in a PQ-208 type package. (and explaining why) Or maybe it takes 8 layers, or ... I haven't seen anything like that, but I haven't looked carefully and nobody has mentioned anything like that yet in this discussion. "Don't do that" might be the right answer. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 74830
Thanks to all who replied to my post..Article: 74831
Nicolas Matringe <matringe.nicolas@numeri-cable.fr> wrote in message news:<41750735.2030301@numeri-cable.fr>... > Thomas Bartzick a écrit: > > Hello together, > > > > has anyone experience with tristates in SPARTAN3-fpgas? > > If we implement a schematic-oriented structure we won't get any > > error-messages but only warnings and the design will be compiled fine. > > But it seems that all our tristate outputs are driven permanently > > (which is very bad!). > > I have just finished a VHDL PCI design in a Spartan3 and so far it works > (tests are still in progress but tristate outputs are OK) Hello Nicolas, well I didn't mean, that tristates are basically a problem in SPARTAN3 but schematic-entry->to vhdl-transformation and also specialized cores make trouble! We are using a core which has been originally written vor VIRTEX2-devices but was now tested on a SPARTAN3 on which we detected the described phenomenons. A XILINX-engineer has told me that using library-primitives which carry tristates is a bad idea, because some primitives (and so the tristates of them) are no more supported by XILINX in SPARTAN3. Behavioural models should be used instead! Ok, well any hints are welcome! Bye, Thomas.Article: 74832
Quick message for those asking part numbers (if you didnt ask - IGNORE, thanks for answers): XILINX VirtexProII-based ML300 and ML310 boards (we have both), part# as follows: a) UW-V2P-ML310 - US version, embedded/development platform? It may be 'HW" in front of this part# and not "UW" and b) DO-V2P-ML300 - US version, evaluation/development kit (EDK 6.2I) *****Your original message******** It would help, if you would tell us, which board you got ...Article: 74833
Hello I need some practical info on has any body used Xilinx Vertex series of FPGAs for any project involving active partial reconfiguration I mean to say that if a part of FPGA is working then can we reconfigure another part of the FPGA and make it work Rgds KedarArticle: 74834
Hello, I'm playing with the spartan3 starter KIT. One of my goals was to implemenet a pipelined DES design for cracking a good old single des-challenge. The complete DES pipeline uses the following resources. Device utilization summary: --------------------------- Selected Device : 3s200ft256-5 Number of Slices: 1415 out of 1920 73% Number of Slice Flip Flops: 1081 out of 3840 28% Number of 4 input LUTs: 2342 out of 3840 60% Number of bonded IOBs: 65 out of 173 37% Number of GCLKs: 1 out of 8 12% ========================================== Now I need to step through a 48 bit key space (I know the other 8 bits) .The code for a simple 48 bit counter: >entity keygen is port >( > CLK: in STD_LOGIC; > RESET: in STD_LOGIC; > COUNT: inout STD_LOGIC_VECTOR(1 to 48) >); >end keygen; > >architecture Behavioral of keygen is > >begin > >process (CLK, RESET) >begin > if RESET='1' then > COUNT <= x"000000000000"; > elsif CLK='1' and CLK'event then > COUNT <= COUNT + 1; > end if; > >end process; > > >end Behavioral; Device utilization summary for this counter. --------------------------- Selected Device : 3s200ft256-5 Number of Slices: 28 out of 1920 1% Number of Slice Flip Flops: 48 out of 3840 1% Number of 4 input LUTs: 48 out of 3840 1% Number of bonded IOBs: 49 out of 173 28% Number of GCLKs: 1 out of 8 12% ========================================== All fine untill I place the counter in front of the pipline. The result of the synthesis process of the complete design is: Device utilization summary: --------------------------- Selected Device : 3s200ft256-5 Number of Slices: 1972 out of 1920 102% (*) Number of Slice Flip Flops: 1752 out of 3840 45% Number of 4 input LUTs: 3116 out of 3840 81% Number of bonded IOBs: 65 out of 173 37% Number of GCLKs: 1 out of 8 12% WARNING:Xst:1336 - (*) More than 100% of Device resources are used ========================================== Am I missing something here? This is a huge increase of used resources I can't explaine. Any help/explanation is welcome. regards AlwinArticle: 74835
Hi all, I am finishing my PCI core. I want to do from XST an .ngc file of my PCI core. The goal is to map IO buffers for all the PCI signal and to let other signals without IO buffer mapping. If I use the XST command line -iobuf , I can only enable or disable the use of IO Buffer on all the port of the entity. Any advice ? Thanks Laurent www.amontec.comArticle: 74836
Symon wrote: > >I wonder, do the IBIS models include the lead frame? > AFAIK, IBIS modeling ignores ground bounce & such. Earlier versions of the S3 IBIS files used the SAME package model for ALL packages, from BGA through PQFP; the IBIS file had tiny entries for package parasitics, and Xilinx suggested a user-added Tline model to model the pin: uncoupled 65 ohm transmission line, 25-100 ps delay from : http://direct.xilinx.com/bvdocs/appnotes/xapp475.pdf Now, if what you're modeling is a transmission line, or behaves like one at the edge rates of interest, a Tline model is more appropriate than a single element lumped approximation; but to model a conventional leadframe package with an UNCOUPLED** Tline model seems rather optimistic. Looking again today, the latest version (2.6) of the S3 IBIS files now has lumped parasitics for some of the leaded packages ( PQ208 and TQFP144, but not the VQ100 ). Note: XAPP475 has not yet been updated to address this modeling change. The other concern I have with the Xilinx IBIS models is that they're still using an ancient version of IBIS (2.1), which doesn't support some of the newer IBIS features such as differential input parasitics. ( Which explains the lack of IBIS models for the _DT terminators in the V2Pro ) ** I don't believe IBIS 2.1 supports modeling of pin-pin coupling BrianArticle: 74837
Laurent Gauch wrote on 20.10.2004 13:12: > Hi all, > > I am finishing my PCI core. > > I want to do from XST an .ngc file of my PCI core. > The goal is to map IO buffers for all the PCI signal and to let other > signals without IO buffer mapping. > > If I use the XST command line -iobuf , I can only enable or disable the > use of IO Buffer on all the port of the entity. > > Any advice ? The only way to do this I can think of is to disable automatic IOBUF insertion in XST and manually instantiate IO buffers for those signals you need them for in your VHDL-code. With a few for...generate-statements it shouldn't even be a whole lot of code. cu, SeanArticle: 74838
Altera's app note "Designing with FineLine BGA Packages" indicates that it is ok to route one (or even two!) signals between 1.0mm balls. My question is if anyone is actually doing this? What is the effect on yield? Does Altera or anyone else offer a proven board or set of gerbers demonstrating this routing technique? Thanks, KenArticle: 74839
Kenneth Land wrote: > Altera's app note "Designing with FineLine BGA Packages" indicates that it > is ok to route one (or even two!) signals between 1.0mm balls. > > My question is if anyone is actually doing this? What is the effect on > yield? > > Does Altera or anyone else offer a proven board or set of gerbers > demonstrating this routing technique? I think so. Xilinx recommanded escape pattern uses 1 line between balls. Sylvain MunautArticle: 74840
Just wondering, why's count an inout? and it could be that the tools are using a lot of resources for route-through, due to some mis-understood code. must admit that i'm not too keen on the mixture of hex and integer for your counter structure, but i don't know whether that effects the design. Ben "alwin" <alwindotpeters.@freeler.nl> wrote in message news:r7hcn0d6k9nok5co7qmuhs5qoi9pk5kgci@4ax.com... > Hello, > > I'm playing with the spartan3 starter KIT. > > One of my goals was to implemenet a pipelined DES design for cracking > a good old single des-challenge. The complete DES pipeline uses the > following resources. > > Device utilization summary: > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 1415 out of 1920 73% > Number of Slice Flip Flops: 1081 out of 3840 28% > Number of 4 input LUTs: 2342 out of 3840 60% > Number of bonded IOBs: 65 out of 173 37% > Number of GCLKs: 1 out of 8 12% > > > ========================================== > > Now I need to step through a 48 bit key space (I know the other 8 > bits) .The code for a simple 48 bit counter: > >entity keygen is port > >( > > CLK: in STD_LOGIC; > > RESET: in STD_LOGIC; > > COUNT: inout STD_LOGIC_VECTOR(1 to 48) > >); > >end keygen; > > > >architecture Behavioral of keygen is > > > >begin > > > >process (CLK, RESET) > >begin > > if RESET='1' then > > COUNT <= x"000000000000"; > > elsif CLK='1' and CLK'event then > > COUNT <= COUNT + 1; > > end if; > > > >end process; > > > > > >end Behavioral; > > > Device utilization summary for this counter. > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 28 out of 1920 1% > Number of Slice Flip Flops: 48 out of 3840 1% > Number of 4 input LUTs: 48 out of 3840 1% > Number of bonded IOBs: 49 out of 173 28% > Number of GCLKs: 1 out of 8 12% > > ========================================== > > All fine untill I place the counter in front of the pipline. > The result of the synthesis process of the complete design is: > > Device utilization summary: > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 1972 out of 1920 102% (*) > Number of Slice Flip Flops: 1752 out of 3840 45% > Number of 4 input LUTs: 3116 out of 3840 81% > Number of bonded IOBs: 65 out of 173 37% > Number of GCLKs: 1 out of 8 12% > > WARNING:Xst:1336 - (*) More than 100% of Device resources are used > > ========================================== > > Am I missing something here? > This is a huge increase of used resources I can't explaine. > > Any help/explanation is welcome. > > regards > Alwin > > > > > >Article: 74841
Hello all, first a little background .. I'm currently working on a fpga design (using VHDL) and using the Xilinx spartan IIE fpga (xc2s400e) chip. my design size is about 1300 slices (about third of the chip capacity). My problem is as follow : sometimes when I change my top design and then re-synthisizes it, some "parts" of my code is not working properly i.e. - some of my fpga blocks are working as usuall and some dont (e.g. FSMs). this appens not only for large code changes, sometimes it happens when I "just" change an output pin to be '0' instead of '1' (a very minor change). my static timing analisys looks o.k. (at least the paths that i've constrained). and I realy dont know where to start looking. I checked my design over and over for "bad code" parts but didnt found anything that might explain this. I would realy like to know if some of you have expeienesd something similar in the past and if not maybe someone can give me a tip to start with.. thanks in advance, Moti.Article: 74842
I had a rather silly question, but the documentation has been rather confusing. If my understanding is correct, i can send clock signals on normal IO pins (not gclk pins) and then define a bufgmux in my VHDL code and it will globally route it. Is my understanding correct? I don't have to route my two clocks to clk pins and THEN put a BUFGMUX do i? Just wanted to make sure. THanks KeithArticle: 74843
Gary, Can you post your professors phone number and email so if we have any questions while working your homework, we can ask them directly. :) Regards, Jim > I need to accomplish the following using the Spartan-3 Starter Kit. > This is a small part of my overall project and I don't have time to do > it. > > Inputs- > > 5V differential quadrature (A+ A- B+ B-) signal > Enable (active high) > Counter Reset (active high) > > Output- > > Trigger Pulse (active low) > > > Specifics- > > I need a trigger pulse that is n clocks wide (n should be changeable > in code- pulse length will need to range between 10us and 500us) > whenever the quadrature counter (24 bit) increments/decrements by x > counts (x should be changeable in code and will range from around 15 > to 200). Quadrature input max speed is 7.8mhz. The trigger pulse > should only be output when the enable signal is active (the counter > can run all the time). > > I am not asking for free help, I just need a complete solution and I > will pay for it ;) > > Thanks, > > GaryArticle: 74844
Keith, The tools will use local interconnect to find an entry to the BUFG tree (you will also geta warning). This means that you will have an unknown skew, and added possibility for jitter. Depends on what you are doing, but if you care about delay, or phase, don't do it. Austin Keith wrote: > I had a rather silly question, but the documentation has been rather confusing. If my understanding is correct, i can send clock signals on normal IO pins (not gclk pins) and then define a bufgmux in my VHDL code and it will globally route it. Is my understanding correct? I don't have to route my two clocks to clk pins and THEN put a BUFGMUX do i? > > Just wanted to make sure. > > THanks > > KeithArticle: 74845
"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:10nckd55pitso93@news.supernews.com... > > Altera's app note "Designing with FineLine BGA Packages" indicates that it > is ok to route one (or even two!) signals between 1.0mm balls. > > My question is if anyone is actually doing this? What is the effect on > yield? > > Does Altera or anyone else offer a proven board or set of gerbers > demonstrating this routing technique? > > Thanks, > Ken I think the real question is how on earth can you AVOID routing tracks between a BGA pads? I can't think of a single board that I've ever seen with BGA devices with no traks between the pads.Article: 74846
"Thomas Bartzick" <thomas.bartzick@atlanticzeiser.com> wrote in message news:47ce721b.0410190358.4d52344a@posting.google.com... > Hello together, > > has anyone experience with tristates in SPARTAN3-fpgas? > If we implement a schematic-oriented structure we won't get any > error-messages but only warnings and the design will be compiled fine. > But it seems that all our tristate outputs are driven permanently > (which is very bad!). > > Hints are very appreciated! > > Thanks, I rarely see any compiler generated warnings in a synthesizable design which does not translate to FATAL bugs and errors! It's better to show us your code for the tri-state drivers and I'm sure the answer will be easy.Article: 74847
"ALuPin" <ALuPin@web.de> wrote in message news:b8a9a7b0.0410180010.12f6e77c@posting.google.com... > Hi @ all, > > I am trying to use the Quartus SignalTap Analyzer. > > Maybe someone can help me with my problem: > > In the current state of my design test I have > programmed my device. The receiving logic does not > run yet because there is no incoming data traffic yet > so that no IDLE-->Low transition is recognized. (Start of > packet). > > And yet I would like to know whether the PLL does generate > the clocks correctly (PLL inclock:30MHz outclocks: c0 48MHz > c1 : 90MHz, e0: 90MHz (external use) > > Because of the fine package and the used board layers > it is almost impossible to measure the clocks externally with an > oszilloscope. > > So the question is how to make the clocks visible with > the SignalTap Analyzer. > As I read in the application note it is said that clocks > cannot be monitored. > > But I cannot imagine that such a basic condition for a synchronous > design cannot be captured. > > What possibilities do I have ? > > > Thank you for your help. > > Kind regards > > André Simple! If you just need to be sure that the clocks are working, put a simple module in your FPGA that divides the clock by say, 16, and monitor it using the SignalTap! You won't know the duty cycle, but for that you really need to use an osciloscope!Article: 74848
"alwin" <alwindotpeters.@freeler.nl> wrote in message news:r7hcn0d6k9nok5co7qmuhs5qoi9pk5kgci@4ax.com... > Hello, > > I'm playing with the spartan3 starter KIT. > > One of my goals was to implemenet a pipelined DES design for cracking > a good old single des-challenge. The complete DES pipeline uses the > following resources. > > Device utilization summary: > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 1415 out of 1920 73% > Number of Slice Flip Flops: 1081 out of 3840 28% > Number of 4 input LUTs: 2342 out of 3840 60% > Number of bonded IOBs: 65 out of 173 37% > Number of GCLKs: 1 out of 8 12% > > > ========================================== > > Now I need to step through a 48 bit key space (I know the other 8 > bits) .The code for a simple 48 bit counter: >>entity keygen is port >>( >> CLK: in STD_LOGIC; >> RESET: in STD_LOGIC; >> COUNT: inout STD_LOGIC_VECTOR(1 to 48) >>); >>end keygen; >> >>architecture Behavioral of keygen is >> >>begin >> >>process (CLK, RESET) >>begin >> if RESET='1' then >> COUNT <= x"000000000000"; >> elsif CLK='1' and CLK'event then >> COUNT <= COUNT + 1; >> end if; >> >>end process; >> >> >>end Behavioral; > > > Device utilization summary for this counter. > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 28 out of 1920 1% > Number of Slice Flip Flops: 48 out of 3840 1% > Number of 4 input LUTs: 48 out of 3840 1% > Number of bonded IOBs: 49 out of 173 28% > Number of GCLKs: 1 out of 8 12% > > ========================================== > > All fine untill I place the counter in front of the pipline. > The result of the synthesis process of the complete design is: > > Device utilization summary: > --------------------------- > > Selected Device : 3s200ft256-5 > > Number of Slices: 1972 out of 1920 102% (*) > Number of Slice Flip Flops: 1752 out of 3840 45% > Number of 4 input LUTs: 3116 out of 3840 81% > Number of bonded IOBs: 65 out of 173 37% > Number of GCLKs: 1 out of 8 12% > > WARNING:Xst:1336 - (*) More than 100% of Device resources are used > > ========================================== > > Am I missing something here? > This is a huge increase of used resources I can't explaine. > > Any help/explanation is welcome. > > regards > Alwin > > I also think that you should not use an "inout" bus here as it has no meaning. Instead, try using an internal signal as the counter, and just connect it to the output.Article: 74849
"Moti Cohen" <moti@terasync.net> wrote in message news:c04bfe33.0410200517.391ab8d9@posting.google.com... > Hello all, > > first a little background .. > I'm currently working on a fpga design (using VHDL) and using > the Xilinx spartan IIE fpga (xc2s400e) chip. > my design size is about 1300 slices (about third of the chip > capacity). > My problem is as follow : > sometimes when I change my top design and then re-synthisizes it, some > "parts" of my code is not working properly i.e. - some of my fpga > blocks are working as usuall and some dont (e.g. FSMs). > this appens not only for large code changes, sometimes it happens when > I "just" change an output pin to be '0' instead of '1' (a very minor > change). > my static timing analisys looks o.k. (at least the paths that i've > constrained). and I realy dont know where to start looking. > I checked my design over and over for "bad code" parts but didnt found > anything that might explain this. > > I would realy like to know if some of you have expeienesd something > similar in the past and if not maybe someone can give me a tip to > start with.. > > thanks in advance, Moti. Well, off my head I can't help you what specific problem you may face but in general, if you have access to more than one syntesize tool, try to compile to code with it too and see if you see a difference. If you code is OK, the both tools should give similar results (apart from timing) but if there is a small bug, sometimes usinge a second tool which may map the design differently, can help you to isolate the problem. I assume you use XST, so you can try Synplify just as an example. If you don't have access to it, you can ask for a 30 days evaluation version (which is full featured) and try your desing with it. Regards Arash
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