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Messages from 75350

Article: 75350
Subject: Re: FPGA & DDR-SDRAM
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Wed, 03 Nov 2004 17:13:25 +1100
Links: << >>  << T >>  << A >>
On Tue, 02 Nov 2004 17:06:48 GMT, "John_H" <johnhandwork@mail.com>
wrote:

>"Symon" <symon_brewer@hotmail.com> wrote in message
>news:2uprjlF2ectrlU1@uni-berlin.de...
>> Hi Allan,
>> Good points but, playing Devil's advocate, with just one address/control
>> bus, there's only half as many signals to worry about. Duplicating the
>> busses, you start eating up board area, lengthening the traces, making the
>> problem worse than if you just placed the two DIMMs right next to each
>other
>> on the same short bus.
>
>[snip]
>
>I'd agree with the single address/control bus as well if the two modules are
>placed next to each other as are typical dual-DIMM systems.  The only
>difference here is that the bank selects are common to both modules rather
>than separate and there are twice the number of byte lanes.  Otherwise, all
>dual-DIMM issues still apply.  Different clocks go to the different modules
>so there is 1 load per clock.  A preload of the address/control bus may be
>helpful.  Check out the Micron app notes for DDR DIMMs and you'll see the
>issues that need to be addressed for using two DIMMs.
>
>If the board is too crowded with 16 bytes lanes going through 2 DIMMs (which
>does sound agressive) then the separate address/control for the separate
>modules would be helpful for DIMMs that aren't parallel.

In addition, many (all?) of the address and control signals aren't DDR
(i.e. they only make one transition per clock), which allows for more
settling time.

C.F. the data signals, which can make two transitions per clock.

Regards,
Allan

Article: 75351
Subject: Re: FPGA/CPLD Basics
From: "Nitro" <nitro-57@no_spam_please_usa.net>
Date: Wed, 03 Nov 2004 06:48:01 GMT
Links: << >>  << T >>  << A >>
I am Not sure at what level you are looking but the Xilinx site
(http://www.xilinx.com) has a few on-line tutorials.  If you are near Texas I
noticed a free CPLD intor class with developer kit at one of the local
distributors.


On 2 Nov 2004 09:14:36 -0800, Jack// ani wrote:

>
>
>Hi all,
>
>Is there any tutorial on web, where I can learn about working and
>architecture of FPGA and CPLD?
>
>Google turned out to be useless. Someone out there maybe is having
>some helpful pointer.
>
>Any suggestion regarding reference/text books is also appreciated. 
>
>TIA

Article: 75352
Subject: FPGA for Game and Amusement
From: ".::[ IchiGeki ]::." <nomail@please.com>
Date: Wed, 03 Nov 2004 07:18:23 GMT
Links: << >>  << T >>  << A >>
Hi there,

I'm looking for an FPGA board for game and amusement with jamma and cctalk
connector, some ideas? ;)

Thanx




Article: 75353
Subject: hostid for Actel Designer
From: georgevarughese@indiatimes.com (geoerge)
Date: 2 Nov 2004 23:52:04 -0800
Links: << >>  << T >>  << A >>
I am trying to get a floating license for Actel Designer. When I enter
the hostid of my machine (running slackware linux 10.0 ), I get a response
from register.actel.com saying that it requires a 8/12 byte number where as
the 'hostid' command on my machine returns a 7 byte one. prepending a '0' to 
the number didn't help either. Is this a problem with slackware or with the
registration software ?

Article: 75354
Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
From: usenet_10@stanka-web.de (Thomas Stanka)
Date: 2 Nov 2004 23:57:01 -0800
Links: << >>  << T >>  << A >>
"Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote:
> I am interested in safety for embedded applications. So I read this articels 
> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996 
> with great interest.
> 
> People listed a lot of advantages of FPGAs, however the major problem 
> (related to safety) left was that the FPGA has to be reprogrammed at each 
> power up.
> 
> My question: isn't an CPLD a good solution for small safety critical 
> applications?

What principle advantage do you think to gain with an CPLD over an
FPGA?
If you think about a flash based CPLD, why not using a flash based
FPGA?

A lot of Hi-Rel applications use fuse-based fpgas which are (almost)
immune against functional changes after programming and are ready to
start after power-up. So you end nearly in a safety level you reach
with asics.

bye Thomas

Article: 75355
Subject: Re: hostid for Actel Designer
From: Stefan Frank <stefrank@gmx.net>
Date: Wed, 03 Nov 2004 09:16:23 +0100
Links: << >>  << T >>  << A >>
On 11/03/2004 08:52 AM, geoerge wrote:
> I am trying to get a floating license for Actel Designer. When I enter
> the hostid of my machine (running slackware linux 10.0 ), I get a response
> from register.actel.com saying that it requires a 8/12 byte number where as
> the 'hostid' command on my machine returns a 7 byte one. prepending a '0' to 
> the number didn't help either. Is this a problem with slackware or with the
> registration software ?

Hello Geoerge,

have you tried lmhostid from the flexlm utilities? If that does not 
work, try the MAC address of your ethernet card.

The hostid command doesn't seem to be appropriate in all cases.

HTH & HAND,
Steff

Article: 75356
Subject: Re: FPGA/CPLD Basics
From: "Vadim Vaynerman" <vadimv@ieee.org>
Date: Wed, 3 Nov 2004 00:24:55 -0800
Links: << >>  << T >>  << A >>
If you are lookiung for an intro to FPGAs/CPLDs, try these:

 <http://toolbox.xilinx.com/docsan/xilinx6/books/docs/qst/qst.pdf>

 <http://direct.xilinx.com/bvdocs/appnotes/xapp473.pdf>

The first tutorial will teach you how to use the free Webpack suite as well as ISE 6, and is very good. The second app note describes the diffrent software tools you use to create FPGA-based designs. -Vadim

Article: 75357
Subject: Re: FPGA & DDR-SDRAM
From: "Quinn" <quinn_the_esquimo@freenet.de>
Date: Wed, 3 Nov 2004 09:45:46 +0100
Links: << >>  << T >>  << A >>
> >"Symon" <symon_brewer@hotmail.com> wrote in message
> >I'd agree with the single address/control bus as well if the two modules
are
> >placed next to each other as are typical dual-DIMM systems.  The only
> >difference here is that the bank selects are common to both modules
rather
> >than separate and there are twice the number of byte lanes.  Otherwise,
all
> >dual-DIMM issues still apply.  Different clocks go to the different
modules
> >so there is 1 load per clock.  A preload of the address/control bus may
be
> >helpful.  Check out the Micron app notes for DDR DIMMs and you'll see the
> >issues that need to be addressed for using two DIMMs.

Hi, thanks. You already helped me alot, folks! I searched the Micron
homepage but unfortunately didn't get the information (about using two DDR
DIMMS at the same time) you mentioned. Would you please be so kind to send
me the link or pdf?

Regards,    Quinn




Article: 75358
Subject: Re: "frying" FPGAs
From: georgevarughese@indiatimes.com (geoerge)
Date: 3 Nov 2004 01:04:52 -0800
Links: << >>  << T >>  << A >>
> 
> Also using a weaker regulator mmight be another option...
> 
> Bye

If the design downloaded is doing the nasty thing:

May be adding a simple fuse on the power (vcc) supply to the board could
save the FPGA. I hope it is logical to assume that the power consumption
increases heavily when the FPGA is ready to give up.

Also trying a power supply with current limitting circuitry could prevent it 
from burning.

One has to be careful about the jtag programming side though. Connecting diode
protection to the supply line from the jtag may be necessary - if the
protection of the FPGA is insufficient.


Any thoughts ?

Article: 75359
Subject: Re: FPGA/CPLD Basics
From: ALuPin@web.de (ALuPin)
Date: 3 Nov 2004 03:14:30 -0800
Links: << >>  << T >>  << A >>
nospam4u_jack@yahoo.com (Jack// ani) wrote in message news:<86040da6.0411020914.75d6f51e@posting.google.com>...
> Hi all,
> 
> Is there any tutorial on web, where I can learn about working and
> architecture of FPGA and CPLD?
> 
> Google turned out to be useless. Someone out there maybe is having
> some helpful pointer.
> 
> Any suggestion regarding reference/text books is also appreciated. 
> 
> TIA

GOOGLE is YOUR friend:

FPGA + CPLD + architecture

Article: 75360
Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
From: "Falk Salewski" <salewski@informatik.rwth-aachen.de>
Date: Wed, 3 Nov 2004 12:29:12 +0100
Links: << >>  << T >>  << A >>
Didn't know about flash based FPGAs before. Maybe it's something to think 
about.
Thanks for your reply!

Falk

"Thomas Stanka" <usenet_10@stanka-web.de> schrieb im Newsbeitrag 
news:ef424d2c.0411022357.68e94613@posting.google.com...
> "Falk Salewski" <salewski@informatik.rwth-aachen.de> wrote:
>> I am interested in safety for embedded applications. So I read this 
>> articels
>> dealing with "ASICs Vs. FPGA in Safety Critical Apps." posted around 1996
>> with great interest.
>>
>> People listed a lot of advantages of FPGAs, however the major problem
>> (related to safety) left was that the FPGA has to be reprogrammed at each
>> power up.
>>
>> My question: isn't an CPLD a good solution for small safety critical
>> applications?
>
> What principle advantage do you think to gain with an CPLD over an
> FPGA?
> If you think about a flash based CPLD, why not using a flash based
> FPGA?
>
> A lot of Hi-Rel applications use fuse-based fpgas which are (almost)
> immune against functional changes after programming and are ready to
> start after power-up. So you end nearly in a safety level you reach
> with asics.
>
> bye Thomas 



Article: 75361
Subject: Physical Compiler Vs Design Complier
From: whizkid@gamebox.net (whizkid)
Date: 3 Nov 2004 04:02:59 -0800
Links: << >>  << T >>  << A >>
Can anyone pointout the practical differences? I am now synthesising a
design with TSMC 13u library with Design Compiler? What difference in
results can I expect if I use physical Compiler.

thanks
whizkid

Article: 75362
Subject: Re: XST - Memory Problems
From: swankoski@nrl.navy.mil (Eric)
Date: 3 Nov 2004 06:39:55 -0800
Links: << >>  << T >>  << A >>
"Antti Lukats" <antti@case2000.com> wrote in message news:<cm8bbg$iir$05$1@news.t-online.com>...
> "Eric" <swankoski@nrl.navy.mil> wrote in message
> news:84d8efa2.0411020557.78be0f2e@posting.google.com...
> > OK, so I'm trying to synthesize a huge design. Just for quick
> > reference, the inferred macros are below:
>  
> > "ERROR: Portability:3 - This Xilinx application has run out of memory
> > or has encountered a memory conflict..."
> 
> most Xilinx errors are in the "Portability" DLL :( usually such error means
> you need to wait for next Service pack. or the next one, etc..
> 
> 2.5Gb is not enough :(
> I guess you are targetting VP100
> not sure if more memory solves the problem, users with 3GB RAM have seen the
> same error even with VP70
> 
> Xilinx is "commited" to fix all fatal errors, such as yours, so just go
> start complaining! open webcase etc..
> 
> Antti

I hope so. I tried to contact them and get some help. I've tried
targeting the 2VP100 as well as the FX140 and LX200. I've since
changed my design substantially, making it smaller and more efficient.
The real problem, I think, is with the multipliers - once they can't
be used in the DSP48s or the embedded multipliers they take up a lot
of space.

All in all it ends up running out of memory regardless of what I do,
but sometimes at different places.

Article: 75363
Subject: Re: FPGA/CPLD Basics
From: nospam4u_jack@yahoo.com (Jack// ani)
Date: 3 Nov 2004 08:09:30 -0800
Links: << >>  << T >>  << A >>
"Nitro" <nitro-57@no_spam_please_usa.net> wrote in message news:<avgebabfcnzcyrnfrhfnarg.i6l7qq0.pminews@news.randori.com>...
> I am Not sure at what level you are looking but the Xilinx site
> (http://www.xilinx.com) has a few on-line tutorials.  If you are near Texas I
> noticed a free CPLD intor class with developer kit at one of the local
> distributors.

Yeah, there in fact a handbook on there site
http://www.xilinx.com/publications/products/cpld/logic_handbook.pdf,
which I already have. Book is all about FPGA implementation, which is
definitely not my purpose. I need to know how it actually works.

Article: 75364
Subject: Re: compactflash interface problem
From: cs_posting@hotmail.com (Chris Stratton)
Date: 3 Nov 2004 08:17:18 -0800
Links: << >>  << T >>  << A >>
"NoThisRAT" <nothisrat@yahoo.com> wrote in message news:<cm5eb8$89l$1@mail.cn99.com>...
> hello,
>   I design a compactflash interface between pci and a sandisk compactflash
> with true-ide mode, but I have some problem now. after reset, I try to read
> the status register of CF, I got 0x58. When I try any ATA commands like read
> sectors or set features ( set CF to PIO mode), I got 0x59 from status
> register. What is the matter? I think I make the read/write sequence right.
>   BTW, the timing parameters I used is PIO-0.
> 

Did you get the polarity of the chip selects right?  Have you reset
the card?  Do you have to do the whole drive select (probably with the
LBA bit on) in the head register like for an actual IDE disk?  Send
any other initialization commands?  Have you verified with a scope
that the CF card is actually driving the data lines and you aren't
just reading phantom values or resistors?  Are you waiting for the
busy bit to go away, and when apprpriate the data ready to come on,
before you try to do things?

One thing to do is slow it all down... I originally tried to hang an
IDE interface right off a bus, but switched it to registers for
software control of the actual signals in order to debug things more
simply; now that it works I'm going to work on switching it back and
think about a DMA mode.

Status of 0x59 means the error bit is on, try reading the error
register.  I usually got this when I read from an illegal location for
a disk's geometry... I was first playing with a little old drive that
seemed like it claimed to support LBA but in fact didn't.

Chris

Article: 75365
Subject: Re: FPGA & DDR-SDRAM
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 03 Nov 2004 16:33:25 GMT
Links: << >>  << T >>  << A >>
"Quinn" <quinn_the_esquimo@freenet.de> wrote in message
news:cma5vf$sjg$1@news.cs.tu-berlin.de...
> Hi, thanks. You already helped me alot, folks! I searched the Micron
> homepage but unfortunately didn't get the information (about using two DDR
> DIMMS at the same time) you mentioned. Would you please be so kind to send
> me the link or pdf?
>
> Regards,    Quinn

micron.com
-> Modules, DDR SDRAM
---> Technical Notes (tab)

Lots of good info.  The "compensation" that I read about a long while ago
was in TN-46-07, DDR333 Memory Design Guide for Two-DIMM Unbuffered Systems
at http://download.micron.com/pdf/technotes/TN4607.pdf but there is much
more information both at this Technical Notes tab and the Designer's Toolbox
tab.

Happy hunting!



Article: 75366
Subject: Re: unstable fpga design
From: billh40@aol.com (Bill Hanna)
Date: 3 Nov 2004 09:23:57 -0800
Links: << >>  << T >>  << A >>
ALuPin@web.de (ALuPin) wrote in message news:<b8a9a7b0.0410272244.2ee6e77@posting.google.com>...
> Hi,
> 
> > To get repeatable
> > performance I had to resort to 2-phase clocking for local clocks. 
> 
> 
> 
> What do you mean ?
> 
> Could you give more details on that?
> 
> Thank you.
> 
> Rgds
> André


        Two-phase clocking uses the clock rising edge to clock the FF
and uses the clock falling edge to capture the FF Q output in a 2nd FF
to avoid hold time violations when using local clocks.  The local
clocks can have a maximum skew of 9 nsec due to the poor router.
       The XC2V6000-4 FF gate delay is 0.57 nsec and the net delay for
a fan-out of 1 is 0.52 nsec.  The FF set-up time is 0.35 nsec.  So,
maximum skew on a local clock greater than 1.5 nsec will cause false
results.

       I have used a MAXSKEW constraint of 1 nsec for local clocks in
the UCF file and the router meets the constraint for 90% of the
signals.

       The global clock buffer maximum skew is 0.57 nsec across the
die.  However , there is a limited number of global clock buffers
(16).

Bill Hanna

Article: 75367
Subject: Re: Physical Compiler Vs Design Complier
From: "Tom Verbeure" <hombre@gmail.com>
Date: 3 Nov 2004 09:55:03 -0800
Links: << >>  << T >>  << A >>

If you provide a floorplan to Physical compiler, it will estimate the
loading of nets according to actual placement of cells instead of
statistical wireload models. This generally results in faster maximum
speeds of the final design.

Tom


Article: 75368
Subject: Need Virtex 2 Proto Board
From: in2chips2000@yahoo.com (Pete)
Date: 3 Nov 2004 10:30:20 -0800
Links: << >>  << T >>  << A >>
I am looking for a prototype board with a socket for Virtex 2 devices in the
1517 BGA package.

I have a number of XC2V6000-FF1517 devices that I need to test and would
like to use the board to do the testing.

I would be willing to trade some of the V6000 devices for a test board

Also if there is anyone out there that is looking for the above device
please let me know as I plan to sell these at a significant discount once I
can complete the testing of the devices and guarantee their operation

Article: 75369
Subject: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
From: "vax, 9000" <vax9000@gmail.com>
Date: Wed, 03 Nov 2004 13:43:54 -0500
Links: << >>  << T >>  << A >>
Hi group, 
  When I am developing code for a hobby project, I find that XILINX webpack
infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to
remove it to pack more function into the XC95144XL target. 
I am using the version 6.1.
  Here is the sample code (complete and compiles) and the synthesized
schematic is posted at
<http://geocities.com/mscpscsi/PHOTOS/CPLD_VHDL.jpg>. I think ADDR_NEXT can
be connected to D only and HOST_DATA can be connected to pre-set/clr only.
Any idea? Thanks.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 entity busmaster is
  Port (
    ADDR: out std_logic_vector(7 downto 0);
    ADDR_CLK_I: in std_logic;
    ADDR_NEXT: in std_logic_vector(7 downto 0);
    HOST_DATA: in std_logic_vector(7 downto 0);
    HOST_CSWR: in std_logic
    );
end busmaster;
 architecture Behavioral of busmaster is
begin
  ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I)
  begin  -- process
    if HOST_CSWR = '0' then
         ADDR <= HOST_DATA;
    elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then
      ADDR <= ADDR_NEXT;
    end if;
  end process;
end Behavioral;
   

--VAX, 9000


Article: 75370
Subject: comparator problem
From: yshashi@gmail.com (sk)
Date: 3 Nov 2004 11:03:57 -0800
Links: << >>  << T >>  << A >>
Hey 
I'm actually designing a comparator circuit 

                    
                      |--------feedback resistor------|
                      |                               | 
                      |      |---------------------|  | 
       RC CIRCUIT ----|------|+                    |  |
                             | COMPARATOR CIRCUIT  |  |
              INPUT----------|-                    |--|---------OUT
                             |---------------------|
The task is to design this cirucit in such a way  that when an input
pulse (0.5,-2.5) with a pulse width of 8micro seconds is given it
should produce me an output which remains high for atleast like
64micro seconds..i tried using R=2248.5k and C=8500pF and the feedback
resistor i used was 90k..i was able to get an o/p which remains high
for 64microseconds but when looked at it carefuly i was able to figure
out that the outout remained high just beacuse of the large difference
between the resistors(the storage capacitance is not much observed in
the o/p graph)...it should basically work like a monostable
multivibrator (without using ic 555 timer though)...it would be of
great help to me if u could give me some suggestions as how could i do
this..

thanks
sk

Article: 75371
Subject: Re: CPLDs and Safety? Re: ASICs Vs. FPGA in Safety Critical Apps.
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 03 Nov 2004 14:20:31 -0500
Links: << >>  << T >>  << A >>
Falk Salewski wrote:
> 
> Didn't know about flash based FPGAs before. Maybe it's something to think
> about.
> Thanks for your reply!

The ones I have seen are actually SRAM FPGAs with an automatic loader
from on-chip flash.  This loads much faster than an external flash
would, but otherwise the process is the same.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 75372
Subject: Re: comparator problem
From: "John_H" <johnhandwork@mail.com>
Date: Wed, 03 Nov 2004 19:25:15 GMT
Links: << >>  << T >>  << A >>
Since you're posting to the FPGA newsgroup....

STOP IT !!  Don't try to add analog components - however simple they may
seem in concept - when you have the FPGA resources to give you what you need
with very little overhead.  You need a clock resolute enough to discern 8ms
from undesired shorter values.  Use this clock to count when 8ms is valid
then generate your 64ms pulse with the same clock.  No fuss no muss.

If you're trying to use the differential inputs to an FPGA as a comparator,
keep in mind the voltage tolerances on the input to your circuit as well as
the voltage driving the feedback.  The tolerances on your resulting circuit
will be sloppy and not necessarily repeatable.


"sk" <yshashi@gmail.com> wrote in message
news:9b0842f2.0411031103.6c440e9c@posting.google.com...
> Hey
> I'm actually designing a comparator circuit
>
>
>                       |--------feedback resistor------|
>                       |                               |
>                       |      |---------------------|  |
>        RC CIRCUIT ----|------|+                    |  |
>                              | COMPARATOR CIRCUIT  |  |
>               INPUT----------|-                    |--|---------OUT
>                              |---------------------|
> The task is to design this cirucit in such a way  that when an input
> pulse (0.5,-2.5) with a pulse width of 8micro seconds is given it
> should produce me an output which remains high for atleast like
> 64micro seconds..i tried using R=2248.5k and C=8500pF and the feedback
> resistor i used was 90k..i was able to get an o/p which remains high
> for 64microseconds but when looked at it carefuly i was able to figure
> out that the outout remained high just beacuse of the large difference
> between the resistors(the storage capacitance is not much observed in
> the o/p graph)...it should basically work like a monostable
> multivibrator (without using ic 555 timer though)...it would be of
> great help to me if u could give me some suggestions as how could i do
> this..
>
> thanks
> sk



Article: 75373
Subject: Re: FPGA for Game and Amusement
From: "Marco" <l@r.it>
Date: Wed, 03 Nov 2004 19:35:48 GMT
Links: << >>  << T >>  << A >>

http://www.seventech.it

Merlino Board Gambling Machine Dev Kit (The Dev kit include all the software 
tools and C++ demo code, to develop a gambling machine)


Hardware Main Features

Power:

Single voltage of 12V also not stabilised (Jamma)



Video Section:

Optimised for the viewing of vide-graphic animation.

VGA CRT/LCD output configurable with resolutions up to 1024x768. - Standard 
connector out

Video output RGB 15/25 Khz with resolutions of 320x240 and 420x240 -  Jamma 
out

All supported resolutions handle 65000 colours.

Management of the Alpha Blending function (transparency of the viewed 
graphic objects).

In order to lighten the work load of the processor a function has been 
installed on the hardware which makes it possible to superimpose two images 
and calculate the result point by point according to the "alpha" colour 
which determines the transparency.



Web Server:

TCP/IP interface on board, operates as a web server.



Audio Section (Jamma and external connector):

16 bit stereo audio with 10+10W audio amplifier.



Input/Output (Jamma):

16 lines for digital input and 16 lines for output with a power driver.

All the I/O are protected from eventual radio-electrical disturbances.



Memory of User Data:



64 MB of Flash Memory (Intel Strata Flash) - Expandable.



Serial BUS:

1 port for 12C Bus to which it is possible to connect up to 255 peripherals

2 RS232 ports -

Output for CC_TALK Bus (Jamma and external connector)



Clock System

Real Time Clock with pad battery - Watch Dog Timer



Non Volatile Memory

256K FRAM (ferroelectric memory)



Safety

Implementation of an architecture which reasonably protects from eventual 
violation both of the software and hardware.



Optional Modules available:

Module for GSM-GPRS connections - GPS reception module

USB Interface module - Bluetooth interface module

Touch Screen module



".::[ IchiGeki ]::." <nomail@please.com> ha scritto nel messaggio 
news:3D%hd.251662$35.11845320@news4.tin.it...
> Hi there,
>
> I'm looking for an FPGA board for game and amusement with jamma and cctalk
> connector, some ideas? ;)
>
> Thanx
>
>
> 



Article: 75374
Subject: Re: XILINX Webpack VHDL synthesis question (unnecessary MUX infered)
From: rickman <spamgoeshere4@yahoo.com>
Date: Wed, 03 Nov 2004 14:51:48 -0500
Links: << >>  << T >>  << A >>
"vax, 9000" wrote:
> 
> Hi group,
>   When I am developing code for a hobby project, I find that XILINX webpack
> infers unnecessary MUX. I suspect that the MUX eats resource so I'd like to
> remove it to pack more function into the XC95144XL target.
> I am using the version 6.1.
>   Here is the sample code (complete and compiles) and the synthesized
> schematic is posted at
> <http://geocities.com/mscpscsi/PHOTOS/CPLD_VHDL.jpg>. I think ADDR_NEXT can
> be connected to D only and HOST_DATA can be connected to pre-set/clr only.
> Any idea? Thanks.
> 
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>  entity busmaster is
>   Port (
>     ADDR: out std_logic_vector(7 downto 0);
>     ADDR_CLK_I: in std_logic;
>     ADDR_NEXT: in std_logic_vector(7 downto 0);
>     HOST_DATA: in std_logic_vector(7 downto 0);
>     HOST_CSWR: in std_logic
>     );
> end busmaster;
>  architecture Behavioral of busmaster is
> begin
>   ADDR_UPDATE: process (HOST_DATA,HOST_CSWR,ADDR_CLK_I)
>   begin  -- process
>     if HOST_CSWR = '0' then
>          ADDR <= HOST_DATA;
>     elsif ADDR_CLK_I'event and ADDR_CLK_I = '1' then
>       ADDR <= ADDR_NEXT;
>     end if;
>   end process;
> end Behavioral;

I agree 100%.  The mux is pointless.  In essence the mux combines the
two sets of signals and the set/clear logic is demuxing them again.  You
DO need the and gates on the set/clear inputs since according to your
code, HOST_DATA is a signal and not a constant and is only used when
HOST_CSWR is '0'.  

However, in a CPLD, I am not sure that the mux uses additional
resources.  The set/clear and gates will use some of the terms in the
array, so I don't think any of the other terms will be available for
other functions.  Anyone know for sure?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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