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Messages from 75175

Article: 75175
Subject: Re: Question to TBUS-Placement in SPARTAN3 again!
From: "Antti Lukats" <antti@case2000.com>
Date: Thu, 28 Oct 2004 09:27:06 +0200
Links: << >>  << T >>  << A >>
"Thomas Bartzick" <thomas.bartzick@atlanticzeiser.com> wrote in message
news:47ce721b.0410272305.4b80b8e@posting.google.com...
> Good morning!
>
> For my own consideration, please:
>
> Is it correct that:
>
> 1.) TBUF-elements are not available in SPARTAN3 (physically)?
> 2.) I cannot make use of TBUF-library elements, also Webpack ISE 6.x
> is not producing an error?
> 3.) I can use behavioural descriptions with 'Z'-strengths? The
> synthesis tool is transforming them to logic regardless if I give the
> option "-tristate2logic yes/no"?
> 4.) I can use external (I/O)-TBUFS.
>
> Ok, well thank you for your good support at all!
>
> Thomas.

1 there are no TBUF inside the S3 FPGA fabric
3 you can use 'z' its converted to muxes, but better to avoid using 'z'
4 you can use tristate iobuf of course

Antti



Article: 75176
Subject: OPB versus PLB
From: "Frank van Eijkelenburg" <someone@work.com>
Date: Thu, 28 Oct 2004 09:55:12 +0200
Links: << >>  << T >>  << A >>
Could somebody explain me why the OPB bus is used for "slow" peripheral and 
the PLB bus for "fast" peripherals? I have a small design with both an OPB 
and PLB bus and both are running at 100 MHz. Of course there is a delay when 
access devices at the OPB bus from a PowerPC (OPB2PLB bridge). But is this 
the only delay or are there more (like burst supports etc.).

TIA,
Frank 



Article: 75177
Subject: synthesizeble Wait Statement in Procedure
From: Roman <roman.leitner@cern.ch>
Date: Thu, 28 Oct 2004 10:24:28 +0200
Links: << >>  << T >>  << A >>
Hy all,

I have a little problem to write a kind of WAIT-Procedure in VHDL. ( 
like in C, "loop until i = 0,...")
This is necessary to pass  some data to an external chip (Cypress SL811) 
to the right time.

In the end it should look like this:
send_data(xyz);
wait(t);
send_data(xyz);
wait(t);
send_data(xyz);
wait(t);
....


I know that I can do it in an process with a counter, but I would prefer 
  a procedure, which I will put into the package body, and then call it 
when I needed.
Has anyone of you gurus :-) an idea how to manage this?

Thank you very much,
Roman

Article: 75178
Subject: Re: OPB versus PLB
From: Sean Durkin <smd@despammed.com>
Date: Thu, 28 Oct 2004 11:28:03 +0200
Links: << >>  << T >>  << A >>
Frank van Eijkelenburg wrote on 28.10.2004 09:55:
> Could somebody explain me why the OPB bus is used for "slow" peripheral and 
> the PLB bus for "fast" peripherals? I have a small design with both an OPB 
> and PLB bus and both are running at 100 MHz. Of course there is a delay when 
> access devices at the OPB bus from a PowerPC (OPB2PLB bridge). But is this 
> the only delay or are there more (like burst supports etc.).
The PLB just has some features that make it better suited for high-speed 
accesses. You can do 64bit-transfers, simultaneous read and write, it's 
hooked up directly to the PPC (so there's no need for a bridge in 
between, which could add more delay), has less latency and so on. The 
PLB is specifically designed to connect your PPC to memories and other 
stuff that needs really high data rates.

The OPB on the other hand is designed to be as simple as possible (i.e. 
use little logic ressources) and interface as easily to your logic as 
possible. It just lacks some of the "advanced features" the PLB has. 
Doesn't necessarily mean it's a lot slower, just that the theoretical 
maximum throughput is a lot higher for the PLB.

cu,
Sean

Article: 75179
Subject: Re: Viewing/Controling C-Build Outputs
From: Mark McDougall <markm@vl.com.au>
Date: Thu, 28 Oct 2004 19:34:32 +1000
Links: << >>  << T >>  << A >>
George wrote:

> Now my real probelm is that I can't get at the output from the compile
> of main.c. It has flashed by in the C-Build window and that window
> keeps getting cleared several times in the build process.
> 
> Does anyone know how to get at build output messages??

I haven't used the NIOS for a *long* time, but I was building from the 
CLI with gcc under cygwin when in windoze. Can you do the same?

Regards,
Mark

Article: 75180
Subject: Re: Low-power FPGAs?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 28 Oct 2004 22:37:56 +1300
Links: << >>  << T >>  << A >>
Hal Murray wrote:

>> In a Sync system you may have 50- >100% margin by
>>the time you apply Voltage/Temp/Process corners : In an Async system,
>>that margin is available for extended battery life.
> 
> 
> Huh?  Why does one use more battery than the other?
> 
> Power depends upon the work you do, not how fast you do it.
<snip>

  Yes, but the Async allows you to vary the Vcc, and the
chip runs as fast as possible at that Vcc.Temp, then
your P = K.F.V^2 works in your favour.
  Devices such as FLASH where the Active I/F curve does not pass thru 
the origin, also benefit from less ON time.

  Armed with a full Speed/Vcc curve from a precise data sheet,
plus on chip temperature sense, and variable supply, and you can
get almost the same thing from a Sync design, and that's how
many MobileCPUs work. However, they are more the exception,
and most small uC, and FPGAs are not specified to that detail.

  One could design a FPGA system for min possible power, using
TempSense, Variable Vcc, and a small Async block whose task was to 
provide either the main clock, or a reality check of the scalable-clock.

-jg




Article: 75181
Subject: information about Nuhorizon Spartan-3 Development Board ?
From: jm_contact2002@yahoo.fr (jerome)
Date: 28 Oct 2004 02:52:09 -0700
Links: << >>  << T >>  << A >>
Hello,

Could someone give me information about the Nuhorizon Spartan-3
Development Board?
It seems to be a good one based upon the Spartan-3 400 thousand gate
FPGA (XC3S400-4PQ208C).
Could someone confirme me I can use it with the ISE Webpack 6?
A contact in NuHorizon told me I need full software, but I don't
understand.

Any other comment or suggestion?

Thanks,

Jerome.

Article: 75182
Subject: Re: information about Nuhorizon Spartan-3 Development Board ?
From: Sylvain Munaut <tnt_at_246tNt_dot_com@reducespam.com>
Date: Thu, 28 Oct 2004 12:20:11 +0200
Links: << >>  << T >>  << A >>
jerome wrote:
> Hello,
> 
> Could someone give me information about the Nuhorizon Spartan-3
> Development Board?
> It seems to be a good one based upon the Spartan-3 400 thousand gate
> FPGA (XC3S400-4PQ208C).
> Could someone confirme me I can use it with the ISE Webpack 6?
> A contact in NuHorizon told me I need full software, but I don't
> understand.

Yes you can.
The current webpack supports up to XC3S4000
However, the next one (7.x) will only support up to XC3S1500 but that's
still enough for the XC3S400 ...

Of course, it's possibkle that sample bitstream/sources provided with
the kit need the full version to be rebuilt. For e.g. if you have a 
microblaze demo, you need the EDK to rebuild it ...


Sylvain

Article: 75183
Subject: Re: information about Nuhorizon Spartan-3 Development Board ?
From: "John Adair" <removethisthenleavejea@replacewithcompanyname.co.uk>
Date: Thu, 28 Oct 2004 14:14:39 +0100
Links: << >>  << T >>  << A >>
Webpack 6.2 supports up XC3S400. I believe the Webpack 6.3 installed direct
from the web supports up to XC3S1500.

John Adair
Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development
Board.
http://www.enterpoint.co.uk

"jerome" <jm_contact2002@yahoo.fr> wrote in message
news:96a74216.0410280152.436c4fc3@posting.google.com...
> Hello,
>
> Could someone give me information about the Nuhorizon Spartan-3
> Development Board?
> It seems to be a good one based upon the Spartan-3 400 thousand gate
> FPGA (XC3S400-4PQ208C).
> Could someone confirme me I can use it with the ISE Webpack 6?
> A contact in NuHorizon told me I need full software, but I don't
> understand.
>
> Any other comment or suggestion?
>
> Thanks,
>
> Jerome.



Article: 75184
Subject: Re: unstable fpga design
From: moti@terasync.net (Moti Cohen)
Date: 28 Oct 2004 07:19:34 -0700
Links: << >>  << T >>  << A >>
Hi all,
firstlly, i would like to thank all of you for answering. your answers
were very helpfull and informative. I mannaged to stabilze my design
and now it is working very smoothly (Knock on wood..).
I made some changes both in my code and in my constarints in order to
acheive stability and repeatability.
I will describes some of the simple steps that i've taken in order to
get my design stable - for the use of fpga designers experiencing the
same unstability problems as i did.


1. Check that are no unconnected (floating) inputs - in my case i
forgot some floating inputs so I took care of it (internal pull-ups
res.)

2. Check that the design is !!!realy!!! synchronous with no FFs
driving the clock to other FFs - I found a hidden ripple clock in my
design and took care of it.

3. When high rate output is not needed set the "SLOW SLEW RATE" option
to LOW - it might help.

4. Synthesize the design in a different Synth. tool - I found some new
warnings that way and they were very informative.

5. Look for latches inferences - I had one and I believe that it gave
me some problems.

6. Ask the guys in this group - they can give you some pretty good
tips..


All of the above tips are tips that I received from the guys here and
I'm very gartefull for them - THANKS!!
Ragards, Moti.

Article: 75185
Subject: spartan-3 development board
From: "bassos" <bassos@bassos.it>
Date: Thu, 28 Oct 2004 15:21:46 GMT
Links: << >>  << T >>  << A >>
Hi guy,

i want buy the avnet spartan-3 development board

ADS-XLX-SP3-DEV1500

http://www.em.avnet.com/evk/home/0,1719,RID%253D0%2526CID%253D17468%2526CCD%253DUSA%2526SID%253D4746%2526DID%253DDF2%2526SRT%253D1%2526LID%253D0%2526PVW%253D%2526BID%253DDF2%2526CTP%253DEVK,00.html

i would like know by you what you think about it.
I would like load uclinux on this board.

thanks
regard
bassos



Article: 75186
Subject: Re: Newbie: Read from Compact Flash using System ACE
From: Eric Crabill <eric.crabill@xilinx.com>
Date: Thu, 28 Oct 2004 09:27:33 -0700
Links: << >>  << T >>  << A >>

Hi,

Most likely, you will need to interface to the SystemACE MPU
port (as a "memory mapped peripheral") and then implement a
FAT12 or FAT16 filesystem reader to access the file of interest...

If you are using EDK to build a PowerPC/MicroBlaze system,
you can make use of a peripheral in EDK, the OPB to SystemACE
bridge, for the hardware portion of the interface.  There is
also an XilFatFS library that helps with the FAT filesystem.

If you are building a custom design not using EDK, you'll need
to implement something similar.  Maybe you could do it with
PicoBlaze and a small program you write...  But you'll need
to know about FAT filesystem to get it right.

Another option to simplify things is to use some clever format
of the card to have a FAT partition followed by another unused
partition.  I think you could then put your data in specific
sectors in the unused partition and have a FSM or other simple
processor pull the data off the disk from known sectors using
the MPU interface.  This removes the need to implement a FAT
file system.  But now you have to write some utilities to get
your data into specific sectors of the disk...

There's also a design on opencores.org which is relevant but
I don't know how you'd directly use it with SystemACE CF.

Eric

Frank Wang wrote:
> 
> I want to be able to read files off the compact flash card through the
> xilinx system ace chip which is connected to a xilinx virtex 2e FPGA.
> The compact flash card is formated as FAT12.   Has anyone done this
> before, or at least could point me in the right direction in
> implementing this in verilog?
> 
> Thanks,
> 
> frank

Article: 75187
Subject: Re: Low-power FPGAs?
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Oct 2004 12:35:38 -0400
Links: << >>  << T >>  << A >>
Jim Granville wrote:
> 
>   There are some FPGA examples at
> http://www.ics.forth.gr/carv/async/demo/
> 
>   You are broadly correct tho, no system is truly 'clockless', and so
> at some stage you need to know that your Async core _did_ complete
> the branch or thread or interrupt, within some system limit.
> 
>   Where Async can help, is in being more generally spread spectrum,
> ( so improves EMI ), and in having an automatic IDLE mode: When the
> Sw completes, it can stop.

But most sw never completes.  The program typically runs in a loop
waiting for something to do.  The async CPU is no different.  You can
use a HALT or IDLE instruction, but that is what they do on sync logic
CPUs. 


>   Of course, a std uC can come close to the same with HW IDLE control,
> and there are now many Spread spectrum clock generators.

See, great minds think alike...  ;)


>   Downsides are: your core speed is now very elastic, and so cannot be
> used for software timing, plus faster clocked peripherals and
> interrupt type flags that can be dual port in nature (SW & HW access)
> must get very tricky to prove. On a system that had such a bug, it
> would be very enviroment sensitive.
> 
>   The biggest gain I can see from Async, is it (should?) self-track
> Vcc/Temperature/Process. Of these, Wide Vcc operation is likely to give
> the most user benefit.
>   In a Sync system you may have 50- >100% margin by
> the time you apply Voltage/Temp/Process corners : In an Async system,
> that margin is available for extended battery life.

Now that is something I can understand.  Right now the best you can do
is reduce clock speed, which many power sensitive systems use.  In the
async system you can also cut voltage saving power by the square of
voltage.  But couldn't you do that in a sync system as well?  A lot of
the low power CPUs, PICs for one (or is that millions?) spec the chip to
run at one range of speeds for a higher voltage and a lesser range of
speeds at a lesser voltage.  So these CPUs could also save power by
cutting their own voltage and running slower.

Oh, the margin is no more available in async parts.  They have to run a
handshake clock between circuits that is assured to be slower than the
logic path.  Don't you think they put a lot of margin into that
difference?  In fact, when running hot at low voltage, I bet the margin
is a lot less with sync parts.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 75188
Subject: Re: synthesizeble Wait Statement in Procedure
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Oct 2004 12:46:22 -0400
Links: << >>  << T >>  << A >>
Roman wrote:
> 
> Hy all,
> 
> I have a little problem to write a kind of WAIT-Procedure in VHDL. (
> like in C, "loop until i = 0,...")
> This is necessary to pass  some data to an external chip (Cypress SL811)
> to the right time.
> 
> In the end it should look like this:
> send_data(xyz);
> wait(t);
> send_data(xyz);
> wait(t);
> send_data(xyz);
> wait(t);
> ....
> 
> I know that I can do it in an process with a counter, but I would prefer
>   a procedure, which I will put into the package body, and then call it
> when I needed.
> Has anyone of you gurus :-) an idea how to manage this?

I am pretty sure this is not synthesizable.  If you want something that
can be synthesized, think about how you would build the circuit out of
hardware and then describe that circuit using logic and clocked
processes.  You can put the logic inside a procedure.  But you might do
better to use a module and pass it a trigger signal.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 75189
Subject: Re: Low-power FPGAs?
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 28 Oct 2004 13:07:24 -0400
Links: << >>  << T >>  << A >>
Simon Peacock wrote:
> 
>  I saw the same posting too..
> 
> Self timed IC's tend to reduce power in several ways... for starts the peak
> is lower.. as nothing switches at the same time :-)

Is the smily indicating a joke?  That doesn't save power, right? 


> second.. only the circuit active is running.. the next step is still idle
> the last step is now idle.  The tend is to then be either idle or running..
> not 'clocked and waiting'.

If you have separately clocked circuits, that is like pipelining.  Why
wouldn't you run them in parallel?  If you take out the pipeline
registers, you will not use any more power and you will make the circuit
smaller.  


> Third.. the ripple effect... as each stage runs as fast as it wants/needs,
> things which would gobble time doing nothing, now take next to no time to
> do, so simple instructions process faster, and overall, the 'speed' can
> decrease.. or at least .. spend more time doing nothing as speed assumes a
> clock ;-)

In a sync design the circuits are balanced since they all run together. 
Of course this is never perfect.  But this way things can run in
parallel and stay in step.  In an async circuit you would have to have
traffic cops directing results based on availability at a very low
level.  That would add a lot of logic.  


> That's suppose to be good for a 30 % power drop.  That's according to the
> thesis I read a few months back. The problem is, of course, the more you get
> the chip to do.. the less the power saving.  Look at a hyper threading P4
> for example.. all that silicon not doing anything until you hyper thread..
> and then consume another 10 watts
> 
> The classic example of this is a MOVE to register instruction in a
> processor...
> If a standard FPGA or processor, you would setup the address, read, write,
> allocate a bus, and on the next clock edge, execute a simultaneous read and
> write, now the whole chip sees this read and write.. and everything else
> decides its not for them.
> In an Async system, the MOVE sets up a async path between the register and
> the memory... everything else is still idle or doing something else (thru
> other async paths) and the memory and register do the data transfer between
> themselves nothing else knows / cares
> Sounds simple .. but they've been working on this for 10 years. I think
> because when things go wrong.. the system turns to custard, simulation
> requires specialist tools... you can't prototype in a FPGA either.

But logic that is not being used in a sync design may be clocked, but it
uses far less power than if it were actually working.  I still don't see
the power savings.  To some extent, this is comparing apples to oranges
since the two methods will use very different design techniques.  I
think if you were designing a CPU from scratch you would not even have
the same instruction sets for the two designs.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 75190
Subject: Re: Programmable I/O Card for the PC - does it exist ?
From: vbishtei@hotmail.com (vadim)
Date: 28 Oct 2004 10:22:47 -0700
Links: << >>  << T >>  << A >>
I have found a I/O card by Geotest called GC5050. There are several
small
companies that make similar stuff, but I wanted to know whether anyone
has experience (good/bad) using such cards to generate bit-streams.

I am limited on FPGAs and would prefer to have a Software driven
dedicated I/O card that can be reading a simple text file containing
the bit patterm ("1"s and "0"s) and outputting to its ports.
Frequencies of interest are 1Mbps up to 100Mbps...

Article: 75191
Subject: Re: Low-power FPGAs?
From: "Symon" <symon_brewer@hotmail.com>
Date: Thu, 28 Oct 2004 10:42:29 -0700
Links: << >>  << T >>  << A >>
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:4181274C.875E4850@yahoo.com...
> Simon Peacock wrote:
> > Self timed IC's tend to reduce power in several ways... for starts the
peak
> > is lower.. as nothing switches at the same time :-)
>
> Is the smily indicating a joke?  That doesn't save power, right?
>
Well, I think he's trying to say the instantaneous power peak is less for
async. In a sync circuit, most of the energy is consumed at the clock
switching edge. So, the power during the tiny moment of that switch is
enormous, compared to the average power. For async, the transitions are
spread out, as they're delayed in time from one another. This also relates
to the lower EMI thing mentioned in this thread.
Cheers, Syms.
p.s. Good points in the rest of your post, Rick.



Article: 75192
Subject: Re: Low-power FPGAs?
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 28 Oct 2004 10:42:58 -0700
Links: << >>  << T >>  << A >>

rickman wrote:

> Simon Peacock wrote:

>> I saw the same posting too..

>>Self timed IC's tend to reduce power in several ways... for starts the peak
>>is lower.. as nothing switches at the same time :-)

(snip)

>>Third.. the ripple effect... as each stage runs as fast as it wants/needs,
>>things which would gobble time doing nothing, now take next to no time to
>>do, so simple instructions process faster, and overall, the 'speed' can
>>decrease.. or at least .. spend more time doing nothing as speed assumes a
>>clock ;-)

> In a sync design the circuits are balanced since they all run together. 
> Of course this is never perfect.  But this way things can run in
> parallel and stay in step.  In an async circuit you would have to have
> traffic cops directing results based on availability at a very low
> level.  That would add a lot of logic.  

It takes different kinds of logic.  Ordinary FF's would be useless,
so standard FPGA's would not be such a good fit.  Synchronous design
can use a lot of logic keeping things synchronized.   Also, it means
that the whole system is clocked at the rate of the slowest subsystem.

Extra logic and extra design work is then needed to make up for
the speed lost to the synchronous requirement.

(snip)

>>In an Async system, the MOVE sets up a async path between the register and
>>the memory... everything else is still idle or doing something else (thru
>>other async paths) and the memory and register do the data transfer between
>>themselves nothing else knows / cares
>>Sounds simple .. but they've been working on this for 10 years. I think
>>because when things go wrong.. the system turns to custard, simulation
>>requires specialist tools... you can't prototype in a FPGA either.

I don't see why you couldn't prototype in an FPGA.  It might take
a larger FPGA than a synchronous design, and all those FF's would
be wasted.  Also, the design tools tend to assume synchronous logic
putting more work on the designer.

> But logic that is not being used in a sync design may be clocked, but it
> uses far less power than if it were actually working.  I still don't see
> the power savings.  To some extent, this is comparing apples to oranges
> since the two methods will use very different design techniques.  I
> think if you were designing a CPU from scratch you would not even have
> the same instruction sets for the two designs.  

For the PDP-10 line, the KA-10 was asynchronous (self timed) while the 
KI-10 and KL-10 were synchronous, pretty much the same instruction set.

-- glen


Article: 75193
Subject: Re: synthesizeble Wait Statement in Procedure
From: glen herrmannsfeldt <gah@ugcs.caltech.edu>
Date: Thu, 28 Oct 2004 10:44:36 -0700
Links: << >>  << T >>  << A >>


Roman wrote:

> I have a little problem to write a kind of WAIT-Procedure in VHDL. 
 > (  like in C, "loop until i = 0,...")

> This is necessary to pass  some data to an external chip (Cypress SL811) 
> to the right time.

This sounds like a use for a state machine.

-- glen


Article: 75194
Subject: clk warning
From: "Johanus Breeman" <>
Date: Thu, 28 Oct 2004 11:10:08 -0700
Links: << >>  << T >>  << A >>
Hi All,

Does anyone have any information regarding this error:

Warning:XdmHelpers:662 - Period specification "TS_ANY_clk" references the TNM group "ANY_clk", which contains pads and synchronous elements. The timing analyzer will ignore the pads for this specification. You might want to use a qualifier(e.g. "FFS") on the TNM property to remove the pads from this group.

I am curious what exactly this warning is saying and how to go about fixing it. If anyone has the knowledge on this matter it would be of great help.

Thanks,

Johanus Breeman

Article: 75195
Subject: Re: Looking for FPGA design services in India or similar
From: vrms22@yahoo.com (VRMS)
Date: 28 Oct 2004 11:30:27 -0700
Links: << >>  << T >>  << A >>
Hi,

I should be able to help you on this. I have over two decades of
experience in developing state-of-the-art technologies in DSP, FPGA,
Video, Embedded Systems etc and with 15 years of experience in India
on these technologies, though for last 8 years I have been in the
Silicon valley. I know very well the industries there. Send me details
via e-mail if you are interested (vrms22@yahoo.com)

VRMS


searchfordesignservices@hotmail.com (Anom) wrote in message news:<671a04d4.0410220739.8d21b45@posting.google.com>...
> Hi,
> 
> For a quite large project dealing with Virtex 4, DDR2, gigabit
> ethernet and digital signal processing, I'm looking for a top of the
> bill design house in a far east country like india.
> 
> All tips are welcome.
> 
> Best Regards,
> Anom

Article: 75196
Subject: Xilinx Platform Studio- I don't get C source code error messages.
From: narenvarmap@gmail.com (Naren)
Date: 28 Oct 2004 11:48:04 -0700
Links: << >>  << T >>  << A >>
Hai Everyone,
I'am working on Xilinx Photo Studio.
I made some changes to the Master Program C Source Code provided on
Xilinx Website for Microblaze on Spartan 3 Starter kit and I get the
following error:

make: *** [TestApp/executable.elf] Error 1
Done.

The GCC Compiler doesn't mention in which line the error is or what
the error is.

When I checked the same edited program on a different system, the
particular error is mentioned along with the line number.

Should I have to re-install XPS or some different C Compiler.

Please help,
Thank You in Advance,
Naren.

Article: 75197
Subject: xilinx edk 6.3
From: "E.S." <emu@ecubics.com>
Date: Thu, 28 Oct 2004 13:25:14 -0600
Links: << >>  << T >>  << A >>
Hi all,
is the edk 6.3 shipping in the meantime/already ?
Still waiting for mine, but just saw the first patch for it already ...

cheers & thanks



Article: 75198
Subject: Random number generation in testbench
From: fastgreen2000@yahoo.com (FGreen)
Date: 28 Oct 2004 13:39:37 -0700
Links: << >>  << T >>  << A >>
Back ground info : Using Modelsim in Windows environment, using
Verilog.

I'm trying to generate a random number that's different each time
$random is called.  Not knowing much about DOS/windows environment, I
need help passing in wallclock information from the command line (in a
does batch file).

Doing 

  dos prompt> vsim +SEED='time' ...

and using in the testbench

  if (!($value$plusargs("SEED=%d", rand_seed))
   ...

doesn't work because the wallclock time isn't passed in correctly.  I
don't want to use the same starting seed each time the simulation is
run, either.  I'll, of course, save the seed so that I can reproduce
the bugs.

How do I get around this problem?  
How do you use random data pattern in your test bench?

I don't have an option of using unix (or unix-like shell in
windows)...

Thanks in advance.

Article: 75199
Subject: Xilinx V-II BUFGMUX oddities..
From: Marc Kelly <marc@redbeard.demon.co.uk>
Date: Thu, 28 Oct 2004 23:04:34 +0100
Links: << >>  << T >>  << A >>
Hello, I was wondering if someone with a bit more experience in these 
things than me could maybe explain this..

I have a design that has to have two versions, with very minor 
functional differences and one of them works, the other hes very messed 
up clocks, with clocks missing or very badly screwed up... Both have the 
same pin constaints and timings. As far as i can see the only major 
difference between the two in the place and route  of them is as follows...

For X board (NON working..)

|         clk_ret_i       | BUFGMUX0S| No   | 2172 |  0.272     |  1.188 
      |
+-------------------------+----------+------+------+------------+-------------+
|       cclk_in_aux       | BUFGMUX4S| No   |   33 |  0.069     |  1.157 
      |
+-------------------------+----------+------+------+------------+-------------+
|         cclk_in_g       | BUFGMUX3S| No   |    3 |  0.000     |  1.136 
      |
+-------------------------+----------+------+------+------------+-------------+
|            dclk_g       | BUFGMUX6S| No   |   10 |  0.007     |  1.150 
      |

For Y board (working..)

|         clk_ret_i       | BUFGMUX2S| No   | 2171 |  0.272     |  1.188 
      |
+-------------------------+----------+------+------+------------+-------------+
|       cclk_in_aux       | BUFGMUX4S| No   |   33 |  0.029     |  1.167 
      |
+-------------------------+----------+------+------+------------+-------------+
|         cclk_in_g       | BUFGMUX7P| No   |    5 |  0.138     |  1.161 
      |
+-------------------------+----------+------+------+------------+-------------+
|            dclk_g       | BUFGMUX6S| No   |   10 |  0.005     |  1.111 
      |

These were where I let the xilinx tools (6.2 Patch 3 under linux) do the 
placing of the BUFGMUX's .. However it always seemed ot chose those 
positions..

I got round the issue by forcing them to be the Y board configuration, 
but i was wondering what could be the issue with the X board version 
above?? It wasnt a dodgy chip, as every single one of our 30 boards had 
the same issues..

Was just curious as to what could be causing this.. (and how to avoid it 
again...)

Cheers..

/\/\arc



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