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spacexxspace@yahoo.com wrote:
> Can anyone tell me the solution to solve the setup or Hold time
> violation when running the simulation?
Consider using a synchronous testbench.
-- Mike Treseler
Article: 78476Only using 2-stage ganged synchronizer flops to move a data bus from one clock domain to another is GUARANTEED to fail. A metastable event on any of the synchronizers will delay the transition on that bit causing a wrong value to appear on the bus in the receiving clock domain. Now if your data is an incrementing Gray code pattern, where only one bit changes per increment, you can use synchronizers over a bus, but this is a special case. (We use this in implementing asynchronous FIFOs where we need to pass read and write pointers across the clock domains - but that's another story...) In general you need to use either a handshake protocol or an asynchronous FIFO to move data across clock domains. Implementations of handshake protocol based clock domain crossers are cheap in terms of LEs but have a high latency penalty while FIFOs are more expensive while enabling streaming data transfers. -PaulArticle: 78477
Hi, > I don´t understand what is role of PCI LogiCore, when CoreGen > of older Foundations isn´t usable (... if I understand correctly). Core Generator is a "delivery vehicle". The PCI LogiCORE from Xilinx is a piece of IP, in the form of a netlist. Initially, Xilinx would deliver the netlist directly to customers on a CD or via download from a web page. If you have the PCI LogiCORE netlist, it does not matter if you have Core Generator or not. > But why aren´t downloadable pci.vhd-s for this purpose directly > (e.g. on xilinx´s ftp)?? Xilinx currently makes the PCI LogiCORE available through Core Generator, and also available on the web. Web download is only available if you own a license, you cannot download an eval from the web... Core Generator is capable of generating an eval copy. In any case, your issue is that the netlist for XC4000E devices has been discontinued a long time ago, and is no longer available or supported. What is currently available on the web and through Core Generator is a netlist that is suitable for derivatives of the Virtex family: * Virtex, Virtex-E, Spartan-II, Spartan-IIE * Virtex2, Virtex2Pro, Spartan3 * Virtex4 If you are just doing this for fun, you might consider using the PCI interface from OpenCores. You could target this to any device you wish. If you are doing "serious development work" you probably don't want to be using XC4000E but instead one of the devices above in which case you can use the current PCI LogiCORE. Hope that helps, EricArticle: 78478
Rick North wrote:
> I have several BRAMs in my design each needs its own set of constants.
I use an HDL constant array.
http://www.xilinx.com/xcell/xl37/xcell37_22.pdf
-- Mike Treseler
Article: 78479At some point gate count becomes irrelevant. Some of the things that really matter in terms of complexity are: - the device family, size and percentage utilization - number of clock domains and their frequencies - the function and complexity of the core processing logic - what kind of interfaces exist and the rates they run at e.g. DDR, bit skew compensation schemes etc. - programmability/reconfiguration features of the design e.g. microcoded control, CSRs etc. Hardware design is moving in the same direction as software design in terms of functional complexity. Nobody in the software world will these days use number of lines of asm code as a metric (unless they're low level firmware guys maybe). my 2 cents -PaulArticle: 78480
A little off topic, but does anyone know of any zero-delay clock buffers similar to the PI6C2404? Key requirements are external feedback, LVTTL/LVCMOS in and out, rated for at least 100MHz, and a smallish package (SO8 is ideal). I need four outputs (including the one used for feedback). Thanks! RobArticle: 78481
Hi to everyone, I have an Avnet XILINX Virtex-II Pro FPGA xc2vp7ff896 and I am trying to make simple designs work on this board. I'm using EDK 6.3 for designing purposes and Impact to generate the .ace file and copying it to the compact flash card. I have already tried 3 or 4 different designs and none of them seem to work on this board. I think i'm doing everthing correctly since on power up I choose the design to be executed with the dip switches on S1 and reset the board with the first dip switch on S2 like the manual says. Although everything seems to work correctly (no error lights on the board) there is no type of response from the application through serial port of the board on to the hyperterminal session on my PC. Nevertheless when I try booting the .ace files that come preconfigured from factory on the compact flash they all work correctly. ¿Is there something i'm missing making the design? When choosing files to add to the ace file, ¿do I choose only the download.bit file or do I also choose the .elf file? When I choose both I have error lights on the board. ¿Is there any way of debugging the application without the JTAG parallel cable? ¿Do I have to include SysACE component in EDK designs in order to be able to boot from the CF card? If I include SysACE component EDK no longer lets you choose SDRAM component, necessary for nearly all my designs. Thankyou.Article: 78482
Hi, Thanks to everyone who responded to my original "Asynchronous Inputs Question", the answers have been very informative. As you can tell, I'm new to FPGAs/VHDL but I should have known better than to connect asynchronous inputs to a state machine! Does anyone have a suggestion for a practical book (Horowitz & Hill style) or links, papers, etc. for VHDL, especially synthesis for FPGAs ? The books I've come across are a bit lacking in this respect. Lastly, I get "Unable to retrieve message ..." when clicking on the post follow-up button. Am I doing something wrong? Many thanks DaveArticle: 78483
Peter Alfke wrote: > Do not try to find an exotic and expensive oscillator. Go with standard > 40 or 50 MHz and use the DCM to give you the desired internal clock > rate. > Peter Alfke, Xilinx Application > Actually Digi-key lists some that are not "exotic" or "expensive" but unfortunately not stocked either. A 100+ MHz oscillator these days is built with a lower frequency crystal and a PLL. Since pretty much all packaged oscillators consist of a crystal and one chip and maybe some jellybean discretes, I don't see where a chip with a PLL to multiply the frequency is more exotic than the generic inverter pack found in the older designs. One reason to use the 100 MHz oscillator is if you need better jitter specs than you could get from the DCM or if you're going to multiply it up further (like 800 MHz). Finding a quartz crystal that actually runs at 100+ MHz would be exotic. > kcl wrote: > > Hi, > > > > Does someone know where I could find a quartz at 100MHz and 200MHz in > a > > socket DIP8 for the Digilent Spartan3 board? > > > > Thank You. > > > > AlexisArticle: 78484
"Adrian Mora" <adrian.mora@terra.es> wrote in message news:1KQLd.105095$A7.178990@telenews.teleline.es... > Hi to everyone, > > I have an Avnet XILINX Virtex-II Pro FPGA xc2vp7ff896 and I am trying to > make simple designs work on this board. > I'm using EDK 6.3 for designing purposes and Impact to generate the .ace > file and copying it to the compact flash card. > I have already tried 3 or 4 different designs and none of them seem to > work on this board. > I think i'm doing everthing correctly since on power up I choose the > design to be executed with the dip switches on S1 and reset the board with > the first dip switch on S2 like the manual says. > Although everything seems to work correctly (no error lights on the board) > there is no type of response from the application through serial port of > the board on to the hyperterminal session on my PC. > Nevertheless when I try booting the .ace files that come preconfigured > from factory on the compact flash they all work correctly. > ¿Is there something i'm missing making the design? > When choosing files to add to the ace file, ¿do I choose only the > download.bit file or do I also choose the .elf file? When I choose both I > have error lights on the board. I do not have the Avnet board, but I can get the FPGA to configure by only loading the bit file into the FPGA. I either load the program via JTAG into SRAM, or program an external flash for the program load. I have not got to the point of loading a program from Compact Flash. because I cannot get the RDYFORCFCMD to go active after I try to read a sector of data. In fact I only get one 16 bit word when I read a sector, the same vaule repeated 256 times :,(. I'm at EDK 6.2. > ¿Is there any way of debugging the application without the JTAG parallel > cable? You really ought to spring for a JTAG cable. You can load the FPGA, load the software, single step the software, and use ChipScope with it. > ¿Do I have to include SysACE component in EDK designs in order to be able > to boot from the CF card? I did not have it to configure the FPGA, but I believe it is commonly used to read data or elf files from CF. -Newman If I include SysACE component EDK no longer lets you > choose SDRAM component, necessary for nearly all my designs. > > Thankyou. >Article: 78485
"Gabor" <gabor@alacron.com> schrieb im Newsbeitrag news:1107291002.762500.222660@c13g2000cwb.googlegroups.com... > Finding a quartz crystal that actually runs at 100+ MHz would be > exotic. Not too much. Can be a) overtone (harmonic) crystal b) inverted MESA style (available up to 200 MHz fundamental AFAIK) Regards FalkArticle: 78486
Did anyone experience the same PITA non-existent service from Synplicity and Mentor graphics? Tried to get eval license for synthesis comparison since a year now...no feedback..nada... And even better...if you write to Mentor that your former employer might have used illegal licenses for their still sold products tjey answer with nothing as well... Seems to be okay for Mentor to go with cracked software (o; rickArticle: 78487
I found out the problem: The "local target memory" (specified by IP2IP_Addr) discussed on page 114 in the PLB IPIF PDF needs to have an unique address space. I was under the impression that the "local target memory" was some address space within the user_logic.vhd that could have any address range the user desires. However, since the Master PLB module has a slave attachment, the slave component has to have a unique address space, which is the address space of the "local target memory". Pretty confusing since the manual did not explicitly define what the "local target memory" is. In any case, the Master Read/Transaction complete successfully. NN On Mon, 31 Jan 2005, Nju Njoroge wrote: > Hello, > > Thanks to Andrea's help, I was able to confirm that I was properly > setting-up the master write/read requests signals . I was able to narrow > done the problem to the slave to master attachment interactions in the > plb_ipif. For instance, when the my user_logic module issues a master > read, the master attachment issues a read on the PLB bus and it seems to > be executing successfully (all the ACKS go high at the appropriate moment > on the PLB bus). After the master read, the slave attachment is supposed > to perform a write to the "local" memory in my user_logic module. The > Bus2IP signals (like Bus2IP_WrReq) from the slave attachment, which are > supposed to toggle during a slave attachment write, do not toggle. > Likewise, for a master write, the slave attachment should perform a local > memory read, which also fails (no activity on the slave Bus2IP_x signals), > so the master write is never completed since the slave read is not > performed. I looked at the internal plb_ipif signals in simulation > (ModelSim), which show that sa2ma_x and ma2sa_x have activity, but the > activity eventually leads to errors. > In summary, the Master to PLB bus interactions seem actually okay, but > there is some failure within the slave <-> master attachments interactions > (sa2ma_error signals is asserted during these failures), the whole > transaction does not complete properly. > > Has anyone encountered such issues? I haven't changed the inputs/outputs > of the plb_ipif instantiation that the "Create/Import IP" wizard > generated. Andrea said that she just instantiated the plb_ipif manually > (i.e. not with the Wizard). Has anyone else had to adopt this approach to > get a master plb module working? > > Thanks, > > NN > On Wed, 26 Jan 2005, Nju Njoroge wrote: > > > Hello Andrea, > > > > Thank for the response. I wrote a simple test pcore to get a feel for how > > the plb_ipif module should respond. Below is snippet of the main code. The > > summary of the code is that it issues a single beat write to an address, > > then issues a read to the same location. There is a little counter that > > waits after the reset signals have gone high before it starts the > > write/read requests. Note that the BE, Data, Addr, buses etc. are held > > constant well before the requests are made. Would you happen to have a > > simple example of PLB master you wrote that works? I would like to see the > > timing to get an idea why the M_Request and associated plb_ipif signals > > are not being triggered. Also, what version of plb_ipif are you using? We > > are using plb_ipif_v2_01_a (the one that has a master attachment). > > > > Thanks, > > > > Nju > > > > reg [6:0] counter; > > wire counter_done; > > > > > > // Logic for simple 7-bit coutnter > > always @(posedge Bus2IP_Clk) > > begin > > if(Bus2IP_Reset) counter[6:0] <= 7'd0; > > else if (counter < 7'd127) counter <= counter + 1'b1; > > else counter <= counter; > > end > > > > assign counter_done = (counter == 7'd127); > > > > assign IP2Bus_Data = 64'hfeeddeadbeefbead; > > assign IP2Bus_Retry = 1'b0; > > assign IP2Bus_Error = 1'b0; > > assign IP2Bus_ToutSup = 1'b0; > > assign IP2Bus_RdAck = Bus2IP_RdReq; > > assign IP2Bus_WrAck = Bus2IP_WrReq; > > > > > > assign IP2Bus_Addr = 32'h00000008; > > assign IP2Bus_MstBE = 8'hf0; > > assign IP2Bus_MstBurst = 1'b0; > > assign IP2Bus_MstBusLock = 1'b0; > > assign IP2Bus_MstNum = 5'h0; > > assign IP2IP_Addr = IP2Bus_Addr; > > > > // Logic for requests > > > > // State machine for simple write, followed by read > > reg [1:0] state, nxt_state; > > > > //State encoding > > parameter COUNTING = 2'b00; > > parameter WRITING = 2'b01; > > parameter READING = 2'b10; > > parameter DONE = 2'b11; > > > > always @(posedge Bus2IP_Clk) > > begin > > if(Bus2IP_Reset) state <= COUNTING; > > else state <= nxt_state; > > end > > > > always @(/*AUTOSENSE*/Bus2IP_MstError or Bus2IP_MstLastAck > > or Bus2IP_MstTimeOut or counter_done or state) > > begin > > case(state[1:0]) > > COUNTING: > > nxt_state <= (counter_done == 1'b0) ? COUNTING: WRITING; > > > > WRITING: > > nxt_state <= (Bus2IP_MstLastAck | Bus2IP_MstTimeOut | > > Bus2IP_MstError) ? READING: WRITING; > > READING: > > nxt_state <= (Bus2IP_MstLastAck | Bus2IP_MstTimeOut | > > Bus2IP_MstError) ? DONE: READING; > > > > DONE: > > nxt_state <= DONE; > > default: nxt_state <= COUNTING; > > endcase // case(state[1:0]) > > end // always @ (... > > > > assign IP2Bus_MstRdReq = (state == READING); > > assign IP2Bus_MstWrReq = (state == WRITING); > > > > On Wed, 26 Jan 2005, Andrea Sabatini wrote: > > > > > Nju, > > > > > > I've been designing master PLB master modules using the PLB IPIF for quite a > > > while now and, like in your case, the only think I could rely on were the > > > two diagrams you referreded to in your message and the simulation results. I > > > have to say that I did not follow the design flow suggested by Xilinx > > > because I just instatiated the PLB IPIF inside my code and I did not use the > > > Peripheral wizard. > > > > > > I think that the timing reported in those two diagrams is not correct > > > becasue the signls Bus2IP_Cs and Bus2IP_CE are always asserted at the same > > > point in time but the signals Bus2IP_RdCe, Bus2IP_WrCe, Bus2IP_RdReq and > > > Bus2IP_WrReq, althought are always asserted at the same time, are alwas at > > > least one clock cycles delayed respect to the previous two. > > > > > > To be honest, I do not think that that module is bug-free but so far it seem > > > to behave correctly in our application. > > > > > > If you can be more specific about your problem maybe I can help you a little > > > more. > > > > > > Regarding the documentation, I do not know if something more detaild exist. > > > > > > Regards, > > > > > > Andrea Sabatini > > > > > > > > > > > > > > > > > > > > >Article: 78488
It all depend on your perspective. I can get a 50 MHz complete oscillator foe $1.50 (or less). Some people, especially in the Spartan world, think that $5.- is a lot of money... I recently paid $20 for a 10 MHz oscillator from Maxim because it offers 1 ppm accuracy and stability. Peter AlfkeArticle: 78489
>> You could not allow your engineers to go home or use >> the phone or use the internat "Symon" wrote: > Perhaps that's why one of them ripped him off in the past... ;-) The only shackles and chains I had around were already chaining me to my desk, so that couldn't be it! :-) I gather from the responses that design work security either isn't a significant issue (BTW, it has NOT been for me) or that no sensible approach exists. By "sensible" I mean anything that does not adversely affect work and creativity. -MartinArticle: 78490
RobJ wrote: > A little off topic, but does anyone know of any zero-delay clock buffers > similar to the PI6C2404? Key requirements are external feedback, > LVTTL/LVCMOS in and out, rated for at least 100MHz, and a smallish package > (SO8 is ideal). I need four outputs (including the one used for feedback). > > Thanks! Howdy Rob, Check out ICS, Cypress, IDT, Alliance Semiconductor, and Motorola - among others (like Lattice's ispClock stuff). Of course, since this is the FPGA group, I assume you have an FPGA on board - in which case, why not use that? Out of pins? Or is its phase alignment not tight enough for you? Have fun, MarcArticle: 78491
Kolja wrote: > > I am pretty sure that I can disregard transmission line effects > at these very short signal lengths. > What's your planned routing scheme for the short differential nets? ( i.e. track width/separation/height/etc per pair and between pairs, # layer changes, # vias per net ) Also, if the A/D is only 4 mm distant from the FPGA, I'd start worrying about power/gnd plane noise & bypass problems, and then start considering moving it farther away :) Or, are you splitting A/D and FPGA ground & power to provide supply isolation, and then running coupled pairs across the plane cuts to the FPGA? > > What I am concerned about is the current mode driver > characteristic as described by Gabor. > As for the unloaded behavior, I believe the driver output impedance requirements (IIRC about 40-140 ohm single ended ) of the LVDS specs should bound the unloaded output swing. ( I'd add a third vote for the recommendation of verifying that with your actual driver on an eval board ) I'd also vote for the suggestion of at least leaving room for terminations where you can fit them near the driver; or, if the pairs are crossing a plane cut, perhaps a fancier differential/common mode attenuator scheme located right at the plane cut would be in order. If you have output driver strength control, you can tweak that to reduce the output swing, whether unloaded or into a higher-than-normal DCI termination value. BrianArticle: 78492
Peter, You were superb! Those built-in async fifo controllers, in Virtex-4, are amazing. I wasn't aware that they were in there. It's a good thing that Xilinx had the foresight to hire that FIFO expert (whoever he might be). ;-> Bob "Peter Alfke" <peter@xilinx.com> wrote in message news:1106877046.479990.51180@z14g2000cwz.googlegroups.com... > > > If you click on > > http://seminar2.techonline.com/s/xilinx_feb0105 > > and register for the Feb.1 Xilinx TechOnLine, then you can witness my > presentation about Virtex-4 performance. It's a daring high-wire act > between engineering and marketing. Wish me luck! > > The time is Tuesday, Feb 1, noon to 1 pm Pacific time. > It would be nice to feel that I can count on some friends in the > invisible audience. > > Peter Alfke, Xilinx Applications >Article: 78493
The best solution is to ask your Synplicity FAE for the designware compatibility library. Andy Luotto wrote: > I want to map an RTL which synthesize on Synopsys Design compiler on > FPGA (Synplify is the tool and Xlinx is the FPGA I want to use for > mapping) > > The issue is that this unit uses Synopsys Designware components (FIFO > controller, counters and 8b10b enc / dec) > > What is tyhe safest and fastest path to migrate this design on > Sinplify? > > Thanks in advance >Article: 78494
Does coreConultant really support FPGA Compiler2?
After I config the FPGA family/device/speed grade in the "Library set-up for
fc2_shell" and goto step "Specify Clock",
there is a error message says:
Error:Running a 'after_OK' activity hook for activity 'TechSetup'(ACT-6)
Error:Command 'sAct::postApplyCurrentActivity {set_current_compoent
"" -quiet}'
failed with the following reason:
can't read "fc2VerifyDWDCommand": no such variable
While processing after_OK activity hooks for TechSetup.
The error_info stack is suppressed. (TCLSH-16)
Error:Command 'sAct::DlgActivateBoundActivity _sel12221'
failed with the following reason:
Error occurred for item techDlg doing send_event -apply.
The error_info stack is suppressed. (TCLSH-16)
How can I do?
Software Platform:
DesignWare AMBA Connect
FPGA Compiler 2 3.8.2 T-2003.09.SP1
Article: 78495I am thinking of building a fully functional mp3 player with an FPGA. I will appreciate any help if your guys can give me any suggestion. I want the design to be as original as possible. For example: I prefer to implement mp3 decoding mechanism inside an FPGA by myself, rather than purchasing an off the shelf mp3 decoder. My preliminary spec is a simple mp3 player with an FPGA, USB memory stick, an LCD display, a keypad and whatever other external components necessary to build a complete system. 1. If I use USB memory stick, is it significantly more difficult than using IDE harddrive? 2. Where can I download the mp3 specification and algorithm? Is it in public domain, or is it a copyright secret? 3. What kind of other external components needed to implement this project? 4. Do I need an advanced knowledge in DSP for this project? I have basic background in DSP, but not at advanced level. Thanks in advance! HendraArticle: 78496
Kolja Sulimma wrote: > Austin Lesea wrote at 2003-10-02 08:03:57 PST > "Also look at what happens when you do not have a 100 ohm termination. > For some signals, and lengths of pcb, it may not be required." and > "If I may suggest, use LVDCI_25_DCI only for clock inputs, or a few > signals." > > I need to get 16 LVDS pairs into one edge of a Spartan-3. This is really > simple to layout without termination resistors and really complicated > (with our board technology) if I add termination resistors. > > Without termination the maximum signal length is 4mm. The chip driving > the LVDS signals uses current mode output drivers. > > My question now is what will happen if I try to use LVDS without > termination? Will the current mode drivers produce a very large output > signal swing? dangerous overshoot? (They are 3.3V powered) > We want to run data at 480 Mbps over each pair so surely reflections > with less than 30ps roundtrip time are not that much of a problem? > > If the current mode drivers require the 100R at their output, could I > add them at the source? To get many resistors much closer than 4mm on a > bga is difficult anyway. > > Thank you in advance for your suggestions. On a short run, just where the termination is, is not as critical as having the temination itself. Fish-hooks in no termination at all, are likely to be : a) Common mode range of the LVDS receivers - I do not believe this is Rail-rail comparitor stuff - outside the common mode range two things might happen - slower recovery and/or logic inversion. Someone at xilinx should know ? b) Simple dV/dT effects, will mean more intersymbol distortion effects [assuming a) does not bite you first :) ] you can get 4 resistors in a single package, and mount them routing-practical distances from the receiver ? -jgArticle: 78497
HI, seems I had to be more specific :). Thomas Stanka wrote: >> Well, I just couldn't discover how to instantiate the FF by hand in the >> Actel platform... > > In designer, you could choose to place by hand. I guess that you have to > modify the edif netlist before reading in, to get cells, that could be set > by hand on a c-cell place. Remember that a FF could be build from complete > combinatorial gates. If your synthesis tool didn't use the FF_cc you have to replace them in the netlist. Actel uses Dxx_CC for the C-Cell variant of Dxx. The DF1 could be replaced by DF1_CC. I don't know if you could replace a FF with set and preset by a Dxx_CC for the A54SX technologie, check this with your local Actel representant. bye Thomas -- Emailantworten bitte an thomas[at]obige_domain. Usenet_10 ist für Viren und Spam reserviertArticle: 78498
Hi, Why is it that you cant put a FDRE and an SRL16E on the same slice? I looked at a V2 slice within FPGA Editor (woohoo, got the full version of ISE at last!) and it shows me there's a WE signal going to the SRL16, driven by the slice's SR input. Now why would you want to drive it with the SR input when there's already a CE input available??? I wanted to construct a delay line (SRL16 + FF), whose output FF can be reset but then this is not allowed. Any workarounds? Thanks. -JimArticle: 78499
Thanks, "Bob". There was some confusion about the apparent or virtual delay between slides, and I should perhaps have talked more slowly. But totally I am happy. No responses yet (except yours), but perhaps later. The emotional words about benchmarks were no play-acting. I still have scars from Altera's reckless destruction of the old PREP cooperation, more than a dozen years ago. And they are still up to their same old trickery. Their newest game is giving leakage current values at 25 degrees. Nice numbers, but totally meaningless and utterly misleading. How does one expose this? Legally, it's not exactly a lie, but it has the same effect as if it were. Some engineers and managers may even be inexperienced enough to fall for this kind of nonsense. The question is just: How fast will it backfire? The earlier, the better ! No wonder smart engineers have developed a deep suspicion of marketing... Peter
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