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Ben Twijnstra wrote: > > Ah yeah..when is Altera striking with a free Linux version? (o; > > I'm pushing for this as well. Would you be OK with a GUI-less version? > (anyone interested raise their hands!). Altera pays royalties on the GUI > under Linux and Solaris, so if you can get by without a GUI, Altera can > truly ship something free. I second that. I guess marketing puts today a lot of pressure about user appealing IDEs, but if it were up to me I would put all my effort in getting out efficient, heavily tested and well documented shell tools before shipping monolithic, un-intuitive, visually bloated software. It would be nice to have Altera tools for Linux that way, or with a very light but well-thought interface (Synplify comes to my mind). If licensing is an issue, there are very good cross-platform free GUI tools. I think Lattice is using wxWidgets for their new IDE. Altera and Xilinx already use Eclipse for their CPU SDKs, maybe they should unify all with it (perhaps that is what they are planning to do?). C'mon, people went to the moon using slide rules, and the first ICs were layout with scissor-cut mylar over kitchen tables. It can't be *that* hard! My 2 cents. -- PabloBleyerKocik / pablo /"Reliable software must kill people reliably." @bleyer.org / -- Andy MickelArticle: 81451
> > The oscillator locking fits with what I am seeing, not being able to > > reprogram the devices. > > I would expect (generally speaking) a Config Ring osc to gate itself > off, after config is completed. > What does a normally operating device show - does this osc appear > to gate in normal usage ? From what I see with the spectrum analyzer, all of the devices except the failed part will keep their clocks running at all times. > It may pay to get a closer number on that - < 5 seconds and > 1ms is > quite wide... Yes I agree, except I am not sure what value this information is. Next time I reproduce the problem, I will measure it. > You could ask Xilinx explicitly if newer devices have any buried POR > cells, that are not also replicated by a RESET ? > > I would expect this type of oops to be eliminated :) > I agree. But I am also a bit surprised with as much work was being done with the DOD back then that a known problem like this would not have been documented. I did receive a third email from the hotline after posting that last message basically stating that they have been in contact with Austin and Peter. So at least it sounds like you should have all of information I provided to them. I had a direct mail about this subject, so I assume that the person wanted to remain anonymous so I will respect that. The person wrote: " It seems possible that from the outside an 8MHz oscillator would look like 16. That is, you see both transitions as a pulse. Note, for example, that the "60Hz" sound that we are used to hearing from things like transformers is actually 120Hz. " It is an interesting point. I know nothing of the internal design. We do not know the symmetry or if there are possible resonance that occur that could fake out the measurements. However, if this were the case I would not expect a 1Mhz signal to have it's majority of power at 16MHz. I agree that 8MHz is possible, but I took note that there was nothing at 8MHz, or if there was it was buried in the noise floor of the analyzer. I spent some time trying to locate some older parts to test. I can not find any documents that state how the data code was marked, so I am supplying all of the markings as they are shown on each device. Note that these parts are in different packaging, different sizes, etc. So I am not even sure how valid any of this data is. Also, the amplitude is a relative number. I have nothing to gauge it on than it's being relative from one device to the next. Also the probe was moved to detect the peak reading. XC3190A PQ160AKJ9901 A2025068A Assumed date: 99 Fundimental frequency: 16MHz @ -60dB XC3164A PC84CKG9649 A71686A 4C Assumed date: 96 Fundimental frequency: 20MHz @ -40dB XC3164A-5 PC84C X24961M AIG9406 Assumed date: 94 Fundimental frequency: 20MHz @ -40dB XC3120-5 PC84C XG2936M AJG9537 Assumed date: 95 Fundimental frequency: 20MHz @ -50dB * * It was very difficult to lay the probe flat onto this device with the PCB it was located on. Suspect that the reading would have been much higher. From this I would agree that the basic frequency was the same from at least as far back as 94. It is interesting that there seems to have been a shift and that the amplitude changed so much, but I don't know if this is any kind of an indicator. After all it is a different package.Article: 81452
Andr=E9s wrote:
> Hi,
>
> I am trying to implement a debug template in an EC-FPGA (LFEC20E)
with
> the Lattice ispTRACY IP Manager.
>
> I am facing some problems. Maybe someone of you has experienced the
same
> and can lead me into the right direction.
>
> Here are the steps I perform:
>
> 1. In the ispLEVER Project Navigator I open under TOOLS the ispTRACY
IP
> Manager
> 2. In the ispTRACY IP Manager I define the RAM depth etc. under
> CUSTOMIZE, then I click GENERATE to generate the file.
> 3. In the CORE LINKER I can connect the signals I want to look at
with
> the generated I/Os of the generated template.
> When clicking OK a new top level file is generated
> ("eval_ddr_top_test_debug.vhd")
>
> When importing this new top level file in the Project Navigator I see
> that in the new top level file there is instantiated a component
> "test_debug.vhd". But this file is missing. Instead there is just a
file
> "test_debug_tmpl.vhd" which can only be imported as a package.
> So the component is missing.
>
> Can someone tell me what went wrong or where to find the missing
file?
>
> Rgds
> Andr=E9s
Andres,
What you have done are the correct steps and you can keep going. The
"test_deubg.vhd" is a component generated by the linker to interconnect
the signals that you want to debug. There is no need to access to this
component (you can look at the respective .edi file generated).
Therefore, once you import the top level file to your project, this
component will be imported as well (ignore the red question mark) and
you will be able to generate the respective bitstream to start the
debug session (ispTRACY Logic Analyzer).=20
rgds,
cristian
Article: 81453"JJ" <johnjakson@yahoo.com> wrote in message news:1111591429.642074.52420@o13g2000cwo.googlegroups.com... John, > RISC ISAs are always characterized by the target technology on which > they are 1st implemented, hence poor FPGA efficiency unless thats where > you/we start. So true. For example, for PPC, the early implementations (1 um 3LM) were multiple dice -- the ICU (instruction cache and branch processing unit) was separate from the FXU (fixed point execution unit). That is why the PPC calling convention is peculiar -- the call (bl (branch-and-link)) instruction saves the return address in a link register LR (resident in the ICU) instead of a GPR (resident in the FXU), and which cannot be directly load/store'd, and so you have to first move it to a GPR to store it to the frame -- and the reverse nonsense in the function epilog. [Reference: Brian Case, IBM RS/6000's Complex Implementation Extracts Peak Performance, in Understanding RISC Microprocessors, 1993 (MPR rollup)] > If IBM were starting today on a fresh ISA with the memory wall in mind > (100s of dead cycles per cache miss), I would think/hope they would > come up with something entirely different. In our memory wall world, the on-chip ISA doesn't matter as much, performance-wise. You can sometimes model the performance of big applications by considering only the memory transactions that appear at the pins, and the particulars of the attached memory subsystem. What happens on chip is (mostly) irrelevant. Certainly during a garbage collection of a huge heap, or the like, all you're doing for tens of seconds is waiting on millions of non-resident cache line fills. And I have seen application code, over a large data structure, that spends several seconds (many billions of cycles) on one data load instruction that consistently misses the cache. There are well known latency tolerance techniques... > I would suggest that RISC ness could well be defined by how easy it is > to build an ISA simulator... For FPGA RISCs, I like to count the multiplexers in the datapath, because FPGA mux implementations are painfully expensive (*). <5 muxes is a good number. PowerPC is painful compared to MIPS, Alpha, MB, xr16, gr00x0. Even some cool new ISAs require more muxes than I care for. I haven't looked at Nios-II yet. I understand it has compact implementation variants, so I like to think it doesn't incur too many muxes. [http://www.fpgacpu.org/log/sep00.html#000919] (*) It would be nice to have a dual 4-1 mux (with common S0,S1) in a slice -- or the like -- please Xilinx, your CLB interconnect is up to the task. And the MULT_AND trick is essential. [http://www.fpga-faq.org/archives/74325.html#74331] [http://www.fpgacpu.org/log/nov00.html#001112] > PearPC only achieves better > performance closer to 50x slower IIRC through use of a JIT but the 68K > JITs are still far better. I think that is more attributable to a difference in the maturity or sophistication of the emulator. It should be possible to translate PPC to x86 in way less than 500-1 growth. > Perhaps really fast emulation of new ISA should be at > top of todo list of architects to help propagate new cpus, certainly to > get something running ASAP. If this meme subtly or overtly causes new ISAs to carry forward legacy ISA mistakes, let us hope it does not catch on. :-) Jan GrayArticle: 81454
lecroy7200 wrote: <snip> >> It may pay to get a closer number on that - < 5 seconds and > 1ms is >>quite wide... > > > Yes I agree, except I am not sure what value this information is. Next time > I reproduce the problem, I will measure it. You may have to document this, for those units in the field, plus if you decide to retro-fit a power removal WDOG, this will be an important number for that design. -jgArticle: 81455
Is xilkernel configurable to use 2 PPCs in a Virtex II? It seems that all the Xilinx literature I have found has xilkernel running only one PPC. I know the xilkernel source is available, but would like to stay away from it if possible. Anyone gotten a dual-core running with xilkernel? Thanks.Article: 81456
Yes, I had done everything. the ucf was created Ok. Usually the pinouts I had written all started with a P, now the digilent reference talks about pins not starting with a P. Those are the ones not working. If I write the lines directly to the UCF file then they do not map. " - LOC constraint G13 on SEV_SEG<1> is invalid: No such site on the device. To bypass this error set the environment variable" And that's for each one taht doesn't start with a P.Article: 81457
I found the error, although I had the correct device, I didn't had teh correct package. Sorry Jorge ---- al912912Article: 81458
> I have found the case, and the CAE assigned, and I am working with > Peter to resolve this. > > So, your support for this issue is now Peter Alfke and Austin Lesea. > All I can say is that if we can't help you, then no one can, so you can > not complain about not getting the best resources assigned to the job! Thanks!! You should now have my contact information. Feel free to use this. > > Basically, as an officially usupported part (end of life, last time buy > status, etc. ...), we will do what we can. I am hopeful it will get resolved one way or another. > I suggest we move this off of this forum. I look forward to working with you and Peter on this.Article: 81459
nickel wrote: > Hi, > > Anybody can tell me if Lattic ECP/EC FPGA devices support partial > run-time reconfiguration? If yes, is there any related application note > I can refer. > > Thanks a lot > > Nickel Nickel, As far as I know EC/ECP does not support partial reconfiguration. However, there is something that it might be helpful depending on the application. EC/ECP has an embedded SPI Flash Memory interface. Using the normal JTAG pins, you can reprogram the SPI Memory through the FPGA in a background mode (that is while the logic is running from the SRAM cells). So, the new configuration file can hold the part of the logic that you want to change. Hence, after toggling the PRGRM pin for a short time, the SRAM will be configured with the new configuration file. In case that configruation time is critical for your application, I suggest take a look at the new LatticeXP device. (http://www.latticesemi.com/products/fpga/xp/index.cfm) The configruation time for a 10K LUT is less than 1ms, and even more you can hold the value of the I/Os during that time (leave alone I/O). rgds, cristianArticle: 81460
We've been using Altium's P-CAD for a few years (started as TangoEDA). Currently running 2002 and very unlikely to upgrade as, in my opinion, it is not a very good product and the company just loves to collect their $1,500 a year by releasing bogus "service packs". Still lots of very fundamental issues that remain without attention. Anyhow, the question is, what do we move up to? Not looking for the $100K+ packages. What are people using that performs well for designing (schematic) and laying out high-speed, high-complexity PCB's? I've heard that PADS may have the largest installed base out there. I remember getting a demo of Mentor's Expedition at a tradeshow. It seemed like a pretty serious tool, although I'd suspect it comes at a hefty price. Any recommendations? The need will be here in another six months or so. I want to do my research well ahead of that. Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 81461
vlog-mode is a powerful major mode for editing verilog sources in GNU Emacs. visit http://vlog-mode.sourceforge.net for more infomation.Article: 81462
Martin wrote: > We've been using Altium's P-CAD for a few years (started as TangoEDA). > Currently running 2002 and very unlikely to upgrade as, in my opinion, it is > not a very good product and the company just loves to collect their $1,500 a > year by releasing bogus "service packs". Still lots of very fundamental > issues that remain without attention. > > Anyhow, the question is, what do we move up to? Not looking for the $100K+ > packages. What are people using that performs well for designing > (schematic) and laying out high-speed, high-complexity PCB's? I've heard > that PADS may have the largest installed base out there. I remember getting > a demo of Mentor's Expedition at a tradeshow. It seemed like a pretty > serious tool, although I'd suspect it comes at a hefty price. > > Any recommendations? The need will be here in another six months or so. I > want to do my research well ahead of that. Download the new PADS 2005 demo, from the Mentor website. This is fully functional, but has a low ceiling (rather than time-bombed), so you can try all features on simple designs, and take as long as you want to evaluate. If you load in a large design, all saves are disabled. You may also be able to get an early copy of the PCAD-PADS translator, and trial migrating your databases.... -jgArticle: 81463
Hi Ben > I'm pushing for this as well. Would you be OK with a GUI-less version? > (anyone interested raise their hands!). Altera pays royalties on the GUI > under Linux and Solaris, so if you can get by without a GUI, Altera can > truly ship something free. Oh yes. I can't be the only one here who would much rather run everything from a Makefile. Many moons ago I went through the agony of reverse engineering how to run XST, map, par, etc. from the commandline (under Wine), but that was ISE and I didn't keep it up. Cheers, TommyArticle: 81464
In article <1143s0i5u138ve3@corp.supernews.com>, bradsmallridge@dslextreme.com says... > Well that begs another question. I am a post DOS Xilinx user. I understand > that DOS is still being supported and I am a bit of a DOS dinosaur myself. > So does it behove me to start making batch files and processing stuff > using DOS batch files? > > I would recommend installing Cygwin and using a full featured make. I'm using this since years on Windows NT/XP and it works perfectly. KlausArticle: 81465
Checkout the voltage waveform as power is applied. You may find that a current surge (in the fpga) that takes place as the voltage ramps up makes this non-monotonic. This may upset various components on the board, if not the fpga itself. Regards Jon "Alessandro Strazzero" <alessandro.strazzero@virgilio.it> wrote in message news:391fed46.0503220724.4486035f@posting.google.com... > Dear everybody, > > I have a problem on some production boards based on the Altera Cyclone FPGA. > The boards have installed NIOS II CPU. The problem regards the power-on > sequence because some boards are not able to power-up correctly (seems NIOS II > CPU doesn't execute first operative code). > > The development was made on a C7 speed grade FPGA and I didn't experience such > problem. The boards where the problems were detected have installed the C8 > speed grade Cyclone. > > The power-on and reset circuitry comes from Altera's Cyclone development board. > I think the problem is around the FPGA speed grade, but I was not able to find > the reason. My system works at 64 MHz which is a well supported frequency by > the C8 speed grade device. > > Did you experience my same problem ? Any tips to workaround the problem will > be appreciated > > Best Regards > > /AlessandroArticle: 81466
>Yep - until you start feeding PRBS test streams into the scrambler, >which can make your equipment look less reliable than it would be >against a real-world stream. I'm missing something. Why is a PRBS test stream going to make errors? To make a long string of 0s, you have to send something that matches the pattern in the scrambler register. That pattern is supposed to be random - hard to guess and hard to hit by sending malicious data. Is there a trick or quirk I don't know about? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 81467
On 2005-03-23, Ben Twijnstra <btwijnstra@gmail.com> wrote: > I'm pushing for this as well. Would you be OK with a GUI-less version? If I'd have Altera FPGA, definitely yes. I probably would have considered purchasing Altera, if there would have been decent Linux software out to try. Now it's a bit late, though. There needs to be an easy tutorial on using the CLI tools, but I trust Altera can do it, or they already have.Article: 81468
Hi, does anyone know the difference between a Motorola S-record and the Motorola EXORmacs format, if there is any? Thanks ToniArticle: 81469
Hi there, We developed DesignF/X to help prevent/solve these kinds of issues amongst many others by helping create highly accurate pin assignment (.UCF output) for Xilinx devices. Explicit device/package matching is included as is clock/data pin correlation, etc. (Sorry, no Altera support for a while). S3, VII and VII-P are well supported. You can download a free trial from http://www.prodacc.com - system requirements and additional information listed there. Download should take a few minutes at the most. With best wishes, ManuArticle: 81470
Hi, I'm doing my final uni project in VHDL using the xilinx spartan 2 pegasus FPGA board but have hit a small snag. When I synthesize my VHDL code i get an error in the timing report that tells me that 3 signals are seen as clock signals when in actula fact only one of them is. TIMING REPORT Clock Information: ------------------ -----------------------------------+------------------------+-------+ Clock Signal | Clock buffer(FF name) | Load | -----------------------------------+------------------------+-------+ _n0070(_n00701:O) | NONE(*)(PISO_load_output_17)| 54 | ADC_EOC | BUFGP | 37 | sync_pulse | BUFGP | 2 | _n0149(_n01491:O) | NONE(*)(line_count_1) | 9 | _n0153(_n01531:O) | NONE(*)(SRAM_addr_4) | 19 | -----------------------------------+------------------------+-------+ (*) These 3 clock signal(s) are generated by combinatorial logic, and XST is not able to identify which are the primary clock signals. Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic. This problem prevents me specifying pins for the 2 non-clock signals. I have tried using the clock signal constraint as follows but this doesn't work. attribute clock_signal: string; attribute clock_signal of GCLK: signal is "yes"; attribute clock_signal of sync_pulse: signal is "no"; attribute clock_signal of ADC_EOC: signal is "no"; Can anyone pls pls help me. Today is the final day of practical work for my project and I want to have it working! any help is much appreciated! Regards AlistairArticle: 81471
Hal Murray wrote: > >> Much lower than that would be a serious problem. Much > >> higher would be hard to measure. > >Yep - until you start feeding PRBS test streams into the scrambler, > >which can make your equipment look less reliable than it would be > >against a real-world stream. > > I'm missing something. Why is a PRBS test stream going to make errors? > > To make a long string of 0s, you have to send something that > matches the pattern in the scrambler register. That pattern > is supposed to be random - hard to guess and hard to hit by > sending malicious data. > > Is there a trick or quirk I don't know about? Howdy Hal, I did a poor job of editing your original response, and an even poorer job of explaining mine - sorry! I was actually trying to provide an example in response to your "much lower would be a serious problem" statement. We've chased phantom bugs in our equipment before where a weekend long test would take a data hit. It was eventually tracked down to a device that effectively had a very short run-length tolerance. It wasn't a CDR, but the result was the same. We've also had a (different) vendor tell us that we had to order the STS's within our scrambled data stream in a certain way, or downstream devices may lose CDR lock. BTW, the 75 bit CID number for the V2Pro CDR can be found here: http://xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=15035 http://xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=15049 http://xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=15055 MarcArticle: 81472
Tuukka Toivonen wrote:
> Use Google to find the programs.
Thank you all for your advices, I'll try to find a suitable tool.
Best regards
Piotr Wyderski
Article: 81473Hi folks, I'm trying to get a DDR-SDRAM controller work as an AHB slave. According to the transfer timings in the AMBA Spec. Rev. 2, the next transfer can't go on until the slave involved in the previous transfer sets the HREADY signal. That means each time a read transfer associated with the DDR is initiated, AHB masters have to wait until the DDR finishes the read burst and puts the read data on the bus, and even another read command involved with the same row as in the current read transfer is not allowed. I think that's really a waste in timing, and will lead to a low efficiency of the DDR bandwidth. Any solutions? regards, Kevin ----- Posted via NewsOne.Net: Free (anonymous) Usenet News via the Web ----- http://newsone.net/ -- Free reading and anonymous posting to 60,000+ groups NewsOne.Net prohibits users from posting spam. If this or other posts made through NewsOne.Net violate posting guidelines, email abuse@newsone.netArticle: 81474
Hi .. why cant i synthesize a module where i have a for-loop which runs thourgh a signal std_logic_vector data_in .... for I in 0 to 31 loop if data_in(I)='1' then // do stuff end loop xilinx just runs forever .. never finishing ... but if i declare the std_logic_vector to be a constant instead of a signal then i works :/ What could be the reason
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Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z