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Messages from 79775

Article: 79775
Subject: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
From: mk<kal*@dspia.*comdelete>
Date: Thu, 24 Feb 2005 09:49:57 GMT
Links: << >>  << T >>  << A >>
On Wed, 23 Feb 2005 23:27:08 -0800, Rob Barris <rbarris@mac.com>
wrote:

>
>I have a simple binary FSK demodulator circuit based on the old 74HC297 
>DPLL, a divide-by-4 counter, and a flip flop. I'm interested in seeing 
>how many such circuits I could pack into a cheap FPGA like one of these:
>
>http://www.fpga4fun.com/board_pluto.html
> (uses Altera EP1K10TC100)
>
>http://www.altera.com/products/devices/acex/acx-index.html
>
>but I'm not sure where to start.  I'm just trying to figure out a 
>ballpark number, i.e. "one copy will just barely fit" or "seems like you 
>should be able to get five copies in there with room to spare".
>
>Is this a common kind of problem - translating old-school discrete chip 
>designs into FPGA?  I did a lot of googling for resources along this 
>vein but didn't come up with much.
>
>At the low price of the fpga4fun board, it's almost an impulse buy, but 
>I wanted to ask the newsgroup first and mull it over.
>
>Rob

297 contains approximately 50 flops and associated logic. As a very
rough approximation, you should be able to implement one 297 and your
divide by 4 counter in 100-150  LEs. A 10K100 has ~5K LEs so you're
looking at ~ 30 of your blocks. But of course it's late and it's been
a while since I got any coffee in my system...


Article: 79776
Subject: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
From: Allan Herriman <allan.herriman.hates.spam@ctam.com.au.invalid>
Date: Thu, 24 Feb 2005 21:07:14 +1100
Links: << >>  << T >>  << A >>
On Wed, 23 Feb 2005 23:27:08 -0800, Rob Barris <rbarris@mac.com>
wrote:

>
>I have a simple binary FSK demodulator circuit based on the old 74HC297 
>DPLL, a divide-by-4 counter, and a flip flop. I'm interested in seeing 
>how many such circuits I could pack into a cheap FPGA like one of these:
>
>http://www.fpga4fun.com/board_pluto.html
> (uses Altera EP1K10TC100)
>
>http://www.altera.com/products/devices/acex/acx-index.html
>
>but I'm not sure where to start.  I'm just trying to figure out a 
>ballpark number, i.e. "one copy will just barely fit" or "seems like you 
>should be able to get five copies in there with room to spare".
>
>Is this a common kind of problem - translating old-school discrete chip 
>designs into FPGA?  I did a lot of googling for resources along this 
>vein but didn't come up with much.
>
>At the low price of the fpga4fun board, it's almost an impulse buy, but 
>I wanted to ask the newsgroup first and mull it over.


Beware of performing a naive (i.e. literal) translation of your SSI
design into a programmable part.  Often designs using individual chips
do things which don't work very well in programmable logic.  Some of
these are:

1.  Gated clocks (to implement clock enables).
2.  Using async resets on flip flops and counters to implement logic
functions.
3.  Hazard coverage.  (Usually the tools will optimise out the
"unnecessary" logic.)

It's usually a trivial matter to turn these into a more FPGA or CPLD
friendly design.
This shouldn't affect the gate count / logic cell count much though.

Regards,
Allan

Article: 79777
Subject: Re: Looking for some rules of thumb - migrating a discrete 74HCxxx design into an FPGA
From: hmurray@suespammers.org (Hal Murray)
Date: Thu, 24 Feb 2005 04:48:06 -0600
Links: << >>  << T >>  << A >>
>I have a simple binary FSK demodulator circuit based on the old 74HC297 
>DPLL, a divide-by-4 counter, and a flip flop. I'm interested in seeing 
>how many such circuits I could pack into a cheap FPGA like one of these:

>but I'm not sure where to start.  I'm just trying to figure out a 
>ballpark number, i.e. "one copy will just barely fit" or "seems like you 
>should be able to get five copies in there with room to spare".
>
>Is this a common kind of problem - translating old-school discrete chip 
>designs into FPGA?  I did a lot of googling for resources along this 
>vein but didn't come up with much.

For a rough cut, count FFs.  THen divide that into the number
from the data sheet.

Most modern FPGAs have a basic unit that is a clump of logic
and a FF.  The "clump of logic" is typically a 4 input LUT
(Look Up Table).  It can implement any function of 4 inputs.

If your design/problem doesn't have a lot of logic between
the FFs, there is a good chance that all or most of it will
fit in that 4 input LUT.  So counting FFs works out to be
a good rough estimate.

-- 
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.


Article: 79778
Subject: Multiple additions
From: "blackduck" <rg66@le.ac.uk>
Date: 24 Feb 2005 03:30:50 -0800
Links: << >>  << T >>  << A >>
Hello friends

I am implementing a design which has about 250 32-bits unsigned numbers
which have to be added to give the final outcome, since it is a very
large number of elelments I think implementing this operation on FPGA
would be very slow (250 cascade adders), I am thinking in using
Carry-Save adders scheme to avoid the long propagation times due to the
carry, but I am not sure now if it would really help. I need to carry
out this additions in the shortest possible time, Carry-Save arithmetic
would be helpful? is there any other scheme I can use to speed up the
addition? (at some point I will need to increase the number of
quantities to be added far above 250).

Many Thanks


Article: 79779
Subject: Multiple addition(2)
From: "blackduck" <rg66@le.ac.uk>
Date: 24 Feb 2005 03:42:46 -0800
Links: << >>  << T >>  << A >>
About the original message multiple additions, I forgot to add that I'm
currentily using a Virtex II Pro 2vp100 device.

Thanks


Article: 79780
Subject: Re: Multiple additions
From: mk<kal*@dspia.*comdelete>
Date: Thu, 24 Feb 2005 12:01:17 GMT
Links: << >>  << T >>  << A >>
On 24 Feb 2005 03:30:50 -0800, "blackduck" <rg66@le.ac.uk> wrote:

>Hello friends
>
>I am implementing a design which has about 250 32-bits unsigned numbers
>which have to be added to give the final outcome, since it is a very
>large number of elelments I think implementing this operation on FPGA
>would be very slow (250 cascade adders), I am thinking in using
>Carry-Save adders scheme to avoid the long propagation times due to the
>carry, but I am not sure now if it would really help. I need to carry
>out this additions in the shortest possible time, Carry-Save arithmetic
>would be helpful? is there any other scheme I can use to speed up the
>addition? (at some point I will need to increase the number of
>quantities to be added far above 250).
>
>Many Thanks

How fast do you need the result and how fast are these numbers coming
in ? You're presenting your problem as if someone is giving you all
these 250 numbers in cycle n and wants the sum in cycle n+1. If the
numbers are coming one at a time and you need the sum after number
250, the problem is quite different. Please tell us little bit more on
your data (speed, format etc).


Article: 79781
Subject: Re: Multiple addition(2)
From: "Jochen" <JFrensch@HarmanBecker.com>
Date: 24 Feb 2005 04:10:36 -0800
Links: << >>  << T >>  << A >>
blackduck wrote:
> About the original message multiple additions, I forgot to add that
I'm
> currentily using a Virtex II Pro 2vp100 device.
>
> Thanks

[...]

> I need to carry out this additions in the shortest possible time,

Hi BlackDuck,

 Is pipelining an option ?

 always adding 2  32..38 bit numbers
 (depending of the stage within your pipeline)
 leads to 7 Pipeline-Stages to add 256 numbers !!!

  - 100 MHz
  - one Result on every clock
  - with an inital latency of 7 clocks

 should be possible in a Virtex2Pro...

Cheers
Jochen


Article: 79782
Subject: Adjustment for FPGA-FAQ 0044
From: Andrew Greensted <ajg112@ohm.york.ac.uk>
Date: Thu, 24 Feb 2005 12:25:24 +0000
Links: << >>  << T >>  << A >>
Hi All,

Not sure who can do this, but I think this extra info for FPGA-FAQ entry 
0044 will help.

For the SuSE distro, adding the two include directories to CFLAGS works 
if you place them at the start. So, it might be clearer to have this in 
the FAQ:


* on Debian, just run make. On SuSE: edit makefile
   -change KERNEL_DIR:  KERNEL_DIR = /usr/src/linux/
   -modify CFLAGS:
      i) delete all -I flags
     ii) add to start of CFLAGS  -I/usr/src/linux/include
    iii) add next in CFAGS  -I/usr/src/linux/include/asm-i386/mach-default/


I originally placed them elsewhere and compilation failed.

Hope this helps someone
Andy

Article: 79783
Subject: Re: Hardcopy Vs ASIC
From: digari@dacafe.com
Date: 24 Feb 2005 04:32:51 -0800
Links: << >>  << T >>  << A >>
john,
Thanks a lot of unbiased information. It really is helpful to me.


Article: 79784
Subject: Re: Multiple additions
From: "blackduck" <rg66@le.ac.uk>
Date: 24 Feb 2005 04:33:48 -0800
Links: << >>  << T >>  << A >>
Many thanks for your response,

Actually the problem is as you said, 250 filters are giving me at time
n 250 different values, then i need to get the addition of those 250
values at time n+1, and this new value conforms an input for a
comparator. Each data is a 32 bits unsigned integer, which is generated
by a lowpass filter at 300MHz, is in fact the impulse response of such
a filter.


Article: 79785
Subject: Re: Multiple addition(2)
From: "blackduck" <rg66@le.ac.uk>
Date: 24 Feb 2005 04:48:21 -0800
Links: << >>  << T >>  << A >>
Thanks Jochen,

Well, I can use the arrangement you propose to speed up the process,
which solves part of the problem, about the pipeline, I am not sure if
it will work since the design uses 250 filters which gives the 250
different values which have to be added to generate a single value. As
you said, each two of them can be added  in 7 stages to generate the
final addition, but as I know a very little about pipeline I cannot
imagine how to implement it. Can you explain me a little how the
implementation would look like please?


Article: 79786
Subject: Re: Multiple addition(2)
From: "KCL" <kclo4_NO_SPAM_@free.fr>
Date: Thu, 24 Feb 2005 14:04:13 +0100
Links: << >>  << T >>  << A >>
well you make a additionner that add 2 number
 you put 125 additionner in parrallel to add your 250 number
next level you use 63 additionner to add the 125 result of the first level
and you do that till you have only 1 result
so in final you will have 125 + 63+ 32+16+8+4+2+1=251 adders
and don't forget that ouput of each level is 1 bit more than input

but another thing is that your input don't arrived all at the same cycle 
clock (or does virtex 2P have 8000 input pin??) so you could make an 
accumulator
imagine one data arrive at each cycle clock, you add your new data to 
accumulator untill you have added your 250 data( = 250clock cycle)




"blackduck" <rg66@le.ac.uk> a écrit dans le message de news: 
1109249301.040661.131480@l41g2000cwc.googlegroups.com...
> Thanks Jochen,
>
> Well, I can use the arrangement you propose to speed up the process,
> which solves part of the problem, about the pipeline, I am not sure if
> it will work since the design uses 250 filters which gives the 250
> different values which have to be added to generate a single value. As
> you said, each two of them can be added  in 7 stages to generate the
> final addition, but as I know a very little about pipeline I cannot
> imagine how to implement it. Can you explain me a little how the
> implementation would look like please?
> 



Article: 79787
Subject: Re: Multiple additions
From: "KCL" <kclo4_NO_SPAM_@free.fr>
Date: Thu, 24 Feb 2005 14:13:57 +0100
Links: << >>  << T >>  << A >>
So your sample frequency is what?? 300MHz??

"blackduck" <rg66@le.ac.uk> a écrit dans le message de news: 
1109248428.297754.45730@g14g2000cwa.googlegroups.com...
> Many thanks for your response,
>
> Actually the problem is as you said, 250 filters are giving me at time
> n 250 different values, then i need to get the addition of those 250
> values at time n+1, and this new value conforms an input for a
> comparator. Each data is a 32 bits unsigned integer, which is generated
> by a lowpass filter at 300MHz, is in fact the impulse response of such
> a filter.
> 



Article: 79788
Subject: Re: How to synthesize the xilinx ip core?
From: "Jim Wu" <nospam@nospam.com>
Date: Thu, 24 Feb 2005 08:20:57 -0500
Links: << >>  << T >>  << A >>

"willie CHEN" <changewhere@126.com> wrote in message
news:cvjr1m$1tb$1@mail.cn99.com...
> Hi,
>     In my project,there's a xilinx IP core. I want to use the synplify7.7
to
> synthesize it, but there's a warning when synthesize .
>     The warning is :
> @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound
> component counter_11 mapped to black box
> @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound
> component counter_4 mapped to black box
>

These warnings can be ignored. The netlist (edf, ngo, etc) for the core will
be picked up when you run ngdbuild. "-sd" option of ngdbuild may be helpful.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips



Article: 79789
Subject: Re: Hardcopy Vs ASIC
From: Kim Enkovaara <kim.enkovaara@tellabs.com>
Date: Thu, 24 Feb 2005 15:33:09 +0200
Links: << >>  << T >>  << A >>
statepenn99 wrote:

> LSI:  Reasonable NRE and pretty low minimum volumes.   Logic density is
> adequate, but it has very little embedded memory.  I would be taking a
> hard look at LSI, if I didn't need so much RAM.

Was that the new LSI RapidChip Integrator2? It has max. 5.6Mgates and 8-9Mbits of
SRAM. That SRAM amount is comparable to EP2S180 (9.3Mbit).

--Kim

Article: 79790
Subject: Re: Hardcopy Vs ASIC
From: Petter Gustad <newsmailcomp6@gustad.com>
Date: Thu, 24 Feb 2005 14:47:12 +0100
Links: << >>  << T >>  << A >>
"statepenn99" <statepenn99@yahoo.com> writes:

> EasyPath:
> Hardcopy II:
> LSI:

Does anybody have any experience with the NEC ISSP? How it compares to
RapidChip?

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

Article: 79791
Subject: Re: Spartan-3 partial reconfiguration trouble
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 24 Feb 2005 05:51:50 -0800
Links: << >>  << T >>  << A >>
rickman wrote:
> >  I have a known-good initial bitstream in a configuration Flash
(the
> > 'boot' image). After that I disable it and I read data from a
memory
> > card, including the other bitstreams.
>
> Do you require the FPGA to be running when you load the other
bitstreams.

 It is the only way I will be able to load bitstreams from the memory
card and do a couple of other things at the same time.

> APP290 does not apply to S3 yet.  What docs talk about PR in S3s?

 At least the datasheet mentions it (regarding the SelectMAP
interface). Also XAPP462 refers to it in the bitgen generation section.
An there is the #18416 Answer Record...

 Cheers.

--
PabloBleyerKocik /"But what... is it good for?"
 pbleyer        / -- 1968 Engineer at IBM's Advanced Computing
  @embedded.cl / Systems Division, commenting on the microchip


Article: 79792
Subject: Re: The real performance leader: V4
From: "Pablo Bleyer Kocik" <pablobleyer@hotmail.com>
Date: 24 Feb 2005 06:15:23 -0800
Links: << >>  << T >>  << A >>
 Hello Peter.

Peter Alfke wrote:
> Do I get a ticket for the Love Boat also?
> Outside cabin, next to the swimming pool, good food, babes, sunshine,
> booze...
> Man, I might not even miss this newsgroup after a while...
> Peter Alfke

 I was going to suggest this also, but I couldn't remember any alter
ego of you in Altera. But if you don't mind a m=E9nage =E0 trois... sure,
I can add you to the list :D

 Thanks for your good humor. Regards.

 PS: Perhaps you can help me with my Spartan-3 partial reconfiguration
issue above... ;)


--               /"It would appear that we have reached the limits of
PabloBleyerKocik/ what it is possible to achieve with computer
technology,
pbleyer        / although one should be careful with such statements,
as
@embedded.cl  / they tend to sound pretty silly in 5 years."-J.von
Neumann


Article: 79793
Subject: Re: Spartan-3 Starter Kit supplier in the UK?
From: "Newman" <newman5382@yahoo.com>
Date: 24 Feb 2005 06:17:15 -0800
Links: << >>  << T >>  << A >>

newman5382 wrote:
> "nospam" <nospam@nospam.invalid> wrote in message
> news:dq2n015ge9pgefno5jl0rlod7d7aao9m74@4ax.com...
> > Alex <uksb@greenbank.org> wrote:
> >
> >>Alex <uksb@greenbank.org> wrote:
> >>[ SNIP original request ]
> >>
> >>Thank you for all of the replies. I've ordered directly
> >>from Xilinx and I'm looking forward to my new toy
> >>arriving.
> >
> > Did you or anyone else get the now bundled EDK evaluation (and 6.3i
ISE
> > evaluation I presume because the 6.3i EDK appears to need it)?
> >
>
> I have not got my EDK either. The Spartan III starter kit came with
the ISE
> eval CD's  I emailed the online store on Feb 07, 2005 and got the
same
> answer as Carsten did on Jan 30, 2005 :
>
> "quote"
> The EDK eval is being sent to all who have purchased the Spartan 3
> Starter kit and will begin shipping within the next couple of weeks.
>
> "unquote"
>
> I replied :
>
> On or before Jan 30, 2005, you gave the same exact answer to another
> customer.My question is, has your schedule slipped.
>
>
> The answer on Feb 08, 2005 was :
> The only information I have at this time is what was provided to us
by our
> Marketing group. If possible, please send me your ship to address and
ship
> to address of the other customer.I will then forward that information

> directly to the department responsible for the eval.
>
> I replied back on Feb 08, 2005 with the information requested.  I
have yet
> to receive an answer back as of Feb 10, 2005.
>
> - Newman


I heard the EDK 6_3 Eval CD's have started to ship.

- Newman


Article: 79794
Subject: Re: Multiple addition(2)
From: "Stephen Maudsley" <news2@sjmaudsley.fsnet.co.uk>
Date: Thu, 24 Feb 2005 14:30:21 GMT
Links: << >>  << T >>  << A >>

"KCL" <kclo4_NO_SPAM_@free.fr> wrote in message
news:421dd0cd$0$846$8fcfb975@news.wanadoo.fr...
> well you make a additionner that add 2 number
>  you put 125 additionner in parrallel to add your 250 number
> next level you use 63 additionner to add the 125 result of the first level
> and you do that till you have only 1 result
> so in final you will have 125 + 63+ 32+16+8+4+2+1=251 adders
> and don't forget that ouput of each level is 1 bit more than input
>
> but another thing is that your input don't arrived all at the same cycle
> clock (or does virtex 2P have 8000 input pin??) so you could make an
> accumulator
> imagine one data arrive at each cycle clock, you add your new data to
> accumulator untill you have added your 250 data( = 250clock cycle)

Might be worth looking at the filters as well - what are they? If they're an
FIR filter array then is it possible to do some of the additions in the MAC
array?

Like you I suspect that there is some data folding somewhere - at the moment
this device has an 80 Giga samples/second input - should be able to make the
coffee as well...



Article: 79795
Subject: Re: Multiple addition(2)
From: "blackduck" <rg66@le.ac.uk>
Date: 24 Feb 2005 06:37:37 -0800
Links: << >>  << T >>  << A >>
Hi KCL,

The design only receives 250 bits as inputs which are the incoming
impulses to lowpass filters (250), these filters produce an output
which has to be added to get the total response, then this total
response in sent to a comparator, indication if the total response is
greater to some value. Then in the first clock cycle, the comparator
has zero as input from the filters, the second clock cycle, the
comparator receives the total response from the filters and compares
this against a value, and this process should be repeated each clock
cycle. The device is able to run at 300 MHz, but the time required to
get the total response is of course slower than this (plus internal
delays), therefore I am trying to carry this process as fast as
possible. The design has 250 bits as inputs and 1 bit output.

Sorry if initially sounded as a 8000 input design.

Thanks


Article: 79796
Subject: Prescalable counter
From: Preben Holm <64bitNOnoSPAMno@mailme.dk>
Date: Thu, 24 Feb 2005 15:56:11 +0100
Links: << >>  << T >>  << A >>
Hi everyone..

I wonder how to build a prescaled counter! That is a counter that can be 
prescaled by fx. a factor 1.000.000 or less!

Any nice ideas how to do this?


Thanks
Preben

Article: 79797
Subject: Synchronous design
From: "morpheus" <saurster@gmail.com>
Date: 24 Feb 2005 07:03:13 -0800
Links: << >>  << T >>  << A >>
Hi All,
I'm kinda new in the business so this question may be very rookie.
Anyways, I was wondering if all synchronous designs need to be state
machine based designed or the synchronous behaviour can be modelled
using multiple clocked processes like always (in Verilog) blocks
activated by clock to do the same thing.
Thanks
morpheus


Article: 79798
Subject: Re: Prescalable counter
From: =?ISO-8859-1?Q?G=F6ran_Bilski?= <goran.bilski@xilinx.com>
Date: Thu, 24 Feb 2005 16:06:26 +0100
Links: << >>  << T >>  << A >>
Hi,

When using Xilinx, the SRL16 is a very good candidate for prescaler implementation.

Göran

Preben Holm wrote:
> Hi everyone..
> 
> I wonder how to build a prescaled counter! That is a counter that can be 
> prescaled by fx. a factor 1.000.000 or less!
> 
> Any nice ideas how to do this?
> 
> 
> Thanks
> Preben


Article: 79799
Subject: Implementing Multi-Processor Systems
From: Paul Hartke <phartke@Stanford.EDU>
Date: Thu, 24 Feb 2005 07:33:12 -0800
Links: << >>  << T >>  << A >>
I finally got around to watching the "Implementing Multi-Processor Systems
in FPGAs" TechOnLine Webcast:
http://seminar2.techonline.com/s/altera_feb1005
http://seminar2.techonline.com/~additionalresources/altera_feb1005/altera_Feb10_slides_edited.pdf

Based on this seminar and my own imagination, I can envision quite a lot of
potential usage models.  However, I was wondering to what level folks are
_actually_ using multiple soft-core processors in an FPGA for their
commercial, academic, and/or personal projects right now.

What is the overall architecture--how many processors are used?  How do the
processors coordinate their activities?  How is data processing distributed
across them?  Is the code/data stored in on-chip memory or externally?

Thanks.
Paul



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2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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