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Hello, I have a spartan 3 starter board with 50MHz oscillator. I need to generate a 1.44MHz clock to drive an external port and some internal logic block such as counters, comparators, etc. I have tried with a series of 2 DCM, but I have obtained a very different period. What I could do? Thanks Marco ToschiArticle: 84576
Hi Gary,
Quartus II 4.1 and newer versions have a graphical tool called the RTL
viewer. This tool will be great for you if you want to see how the
VHDL/Verilog/Schematic you write translates into logic. Our customers and
our own developers and support folks use it extensively to debug their
circuits if they run into a problem, or to understand how logic gets
implemented. There is also a state machine viewer built into the RTL viewer
which will show you the bubble diagram for your state machines written in
HDL.
The RTL viewer can be used to see the output after the synthesis step is
complete, but prior to Technology mapping into LUT's. There is another tool
called the Technology Map viewer which shows you the result after Technology
Mapping. Both Tools are available under the Tools menu and you can bring
them up after compiling your design. As you are already using Quartus they
are already on your desktop and one button click away.
Hope this helps,
Subroto Datta
Altera Corp.
Article: 84577Subroto Datta wrote: > Hi Gary, > Quartus II 4.1 and newer versions have a graphical tool called the RTL > viewer. This tool will be great for you if you want to see how the > VHDL/Verilog/Schematic you write translates into logic. Our customers and > our own developers and support folks use it extensively to debug their > circuits if they run into a problem, or to understand how logic gets > implemented. There is also a state machine viewer built into the RTL viewer > which will show you the bubble diagram for your state machines written in > HDL. > > The RTL viewer can be used to see the output after the synthesis step is > complete, but prior to Technology mapping into LUT's. There is another tool > called the Technology Map viewer which shows you the result after Technology > Mapping. Both Tools are available under the Tools menu and you can bring > them up after compiling your design. As you are already using Quartus they > are already on your desktop and one button click away. > > Hope this helps, > Subroto Datta > Altera Corp. > You guys working weekends as well now? Will Quartus be available in a Linux release soon or has this occured already. If yes, where, when and how much....... Nme. God Bless.Article: 84578
Hi Dave,
Quartus has been available on Linux for the past two years. Red Hat
Version 7.3, 8.0 and Red Hat Enterprise 3.0 are supported with Quartus II
5.0. We will be dropping 7.3 in the next release. These have been tested
with both Opteron and Xeon CPU's. Based on comments from some of the power
Linux users they have had it working on other Linux distributions. This
product will require the purchase of a Linux subscription. You will need to
contact your distributor or the Altera Telsesales group depending on your
location. Check http://www.shopaltera.com/design_software.asp for contact
information.
Hope this helps,
- Subroto Datta
Altera Corp.
"dave" <dave@dave.dave> wrote in message
news:d6ndja$jpi$1@news6.svr.pol.co.uk...
> You guys working weekends as well now?
>
> Will Quartus be available in a Linux release soon or has this occured
> already. If yes, where, when and how much.......
>
> Nme. God Bless.
Article: 84579Do you have the original design entries. ie Schematics of logic equations (HDL). OR are you trying to reverse engineer the original desing? gmArticle: 84580
If you can tolerate some jitter in your clock you can use a NCO for the generation of your required frequency. If you are not familiar with this term (NCO) search for it in this forum. I hope it helps.. Moti Cohen.Article: 84581
Marco wrote: > Hello, > I have a spartan 3 starter board with 50MHz oscillator. > > I need to generate a 1.44MHz clock to drive an external port and some > internal logic block such as counters, comparators, etc. > > I have tried with a series of 2 DCM, but I have obtained a very different > period. > > What I could do? > > > Thanks > Marco Toschi Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use that for your internal clock WITH a clock-enable for the whole thing once every 25 cycles. Also use that clock enable to drive an IOB register high which you then deassert 12 or 13 36 MHz clocks later for 48%/52% duty cycle. Clean, workable.Article: 84582
ivan wrote: > Hi All, > > Have anybody tried downloading uClinux on Virtex4 board.We have got > the bsp sources from > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html#bsp_package > > and the hardware from > http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html#ml401_uclinux_66mhz > > We have generated the bit stream using EDK6.3.02.But don't know how to > compile the kernel(uclinux) and download it.It would be very helpful if > anyone could explain the steps to be followed to bring up the shell of > uClinux. > > Thanks & Regards, > Ivan Get the ucLinux source from CVS. See http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Documentation/obtaining_sources.html Than apply the patches from Johns web site: http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/_files/uClibc.patch read through the Read me file in the distro you just obtained, or look through Johns site for instructions how to build the kernel. It takes a few tries to get it right ... PS: don't use "-jN" option to the makefile to built ucLinux - thats broken ... Good Luck, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84583
I created some IP with the EDK wizard. It is only a 64-bit register--trying to understand how BFM simulation works before I simulate my real design. The IP wizard generated files to do the simulation. After following the readme provided (and fixing a bug or two in the make file) I was able to get ModelSim to display the waveform based on all the default files. I am assuming now to do my own testing, I should modify the 'sample.bfl' file? Am I correct? If so, I can't find any decent documentation on how to do so or that describes this bus-functional language. If the sample.bfl is not the right place to tweak things, where do I need to look? Anyone who has done this before have any advice? I can provide more info on what I have tried if it helps you to help me! Thanks, JoeyArticle: 84584
you will require few steps before you start compile kernel 1) downlaod and install microblaze gcc tool chain from http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Toolchain/linux_binaries.html 2) and get the kernel like Rudolf Usselmann 3) you modify "PARAMETER target_dir" pointing to the ~dir_to_your_uclinux_/linux-2.4.x /arch/microblaze/platform/uclinux-auto in the system.mss 4) build the hardware http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/documentation/building_hardware.html 5)build kernel http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/documentation/building_kernel.html For a first build, it is advised to use only the generic uClinux MTD mapping. In the kernel config menu, under "Memory Technology Devices Settings" -> "Mapping drivers for chip access", select only the "Generic uClinux RAM/ROM filesystem support".Article: 84585
hello,jeffsen and everyone, i have compared the ucf file of ppc project with MICROBLAZE.I don't find the omitted pin, so i think i should modify the parameter of opb_sdram_controller in MICROBLAZE project(IN PPC project is PLB_SDRAM_CONTROLLER),i will try it,thanks your help!!!Article: 84586
"John_H" <johnhandwork@mail.com> wrote in message
news:FuIje.3028$6d.1773@trnddc02...
> Marco wrote:
> > Hello,
> > I have a spartan 3 starter board with 50MHz oscillator.
> >
> > I need to generate a 1.44MHz clock to drive an external port and some
> > internal logic block such as counters, comparators, etc.
> >
> > I have tried with a series of 2 DCM, but I have obtained a very
different
> > period.
> >
> > What I could do?
> >
> >
> > Thanks
> > Marco Toschi
>
> Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use that
> for your internal clock WITH a clock-enable for the whole thing once
> every 25 cycles. Also use that clock enable to drive an IOB register
> high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> duty cycle.
>
> Clean, workable.
To enable clock every 25 cycles I have used a counter with a threshold
signal that goes high at cycle 25.
The threshold signal will be the Clock enable for other logic blocks.
But in this way I obtain a gated clock on this counter.
What could I do?
I thought to the following circuit:
___________________________________
|
|
--------| | |
| MUX |-------------|D FF Q|------------- Clock
Enable
Counter ------| | | |
| |
| |
------------------------
|
oscillator
Is it correct?
Thanks
Marco Toschi
Article: 84587
"John_H" <johnhandwork@mail.com> wrote in message
news:FuIje.3028$6d.1773@trnddc02...
> Marco wrote:
> > Hello,
> > I have a spartan 3 starter board with 50MHz oscillator.
> >
> > I need to generate a 1.44MHz clock to drive an external port and some
> > internal logic block such as counters, comparators, etc.
> >
> > I have tried with a series of 2 DCM, but I have obtained a very
different
> > period.
> >
> > What I could do?
> >
> >
> > Thanks
> > Marco Toschi
>
> Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use that
> for your internal clock WITH a clock-enable for the whole thing once
> every 25 cycles. Also use that clock enable to drive an IOB register
> high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> duty cycle.
>
> Clean, workable.
Bad design...
I hope this is better...
________________________________
| |
--------| | |
| MUX |--------|D FF Q|--------Clock_En
Counter ------| | | |
| |
| |
---------------------
|
oscillator
Article: 84588Hi, Thanks for all the inputs.I could compile the kernal successfully.But when I download the same into the ML401 board with harware downloaded from the site,XMD reports the error regarding address mapping.The kernal comiled is supposed to load at location 0x8000_0000 and in the hardware does not exist.How can I over-come this issue.Do anyone have a compiled image for ML401 board.Both the .bit and .elf file. Any inputs at the earliest will be highly appreciated. Thanks & Regards, IvanArticle: 84589
Marco, all you have to do is build a 5-bit synchronous counter, clocked
at 36 MHz, that divides by 25, and decode one period of the 25. Pick
the period that is easiest to decode.
Use that decoded signal (active High) as the CE input to all your 1.44
MHz flip-flops.
Xilinx does the rest for you. CE controls a mux in front of the D input
that makes the D equal to Q whenever the flip-flop should not change
("clock disable").
This mux is invisible to you, and it means that the clock never is
gated.
Easy!
Peter Alfke, Xilinx Applictions
Article: 84590Hi, Symon schrieb: > "Thomas Stanka" <usenet_10@stanka-web.de> wrote: > > > > But is also written what to do if timing constraint meets power > > constraints? > > > > I like to have each design synchronous. And actually doing a > > _synchronous_ ASIC using several different clocks runing on various > > frequencies, but this is nearly impossible if it comes to do a > > prototype with an fpga and would be complete impossible if the design > > would need to hit the edge of technology, as often seen when doing > > high speed data processing. [..] > Ah, but this isn't comp.arch.asic. Those heretics have their own book! They > need to as they don't get FFs with CE for (kind of) free like we do in > FPGAs. > But, point taken! Well, some designs are pure Fpga designs never intended to target an ASIC and some ASICs never have to be implemented on a FPGA. An Asic has IMHO better possibilities for clock gating than an Fpga, so the point with different clock frequencys for power purpose will mostly imply asynchronous clock domains and there a violation of your synchronity rule :). I don't know which technology provides FF with CE, but there are more than Virtex-4 devices out there in the world *g*. bye ThomasArticle: 84591
Peter Alfke wrote: > Marco, all you have to do is build a 5-bit synchronous counter, clocked > at 36 MHz, that divides by 25, and decode one period of the 25. Pick > the period that is easiest to decode. Use that decoded signal (active High) > as the CE input to all your 1.44 MHz flip-flops. He also needs to drive an external 1.44 MHz clock signal... ArletArticle: 84592
BFM Simulation in Platform Studio http://www.xilinx.com/ise/embedded/bfm_simulation.pdf: "More information about the Bus Functional Language for each bus may be found in the OpbToolkit.pdf, PlbToolkit.pdf and DcrToolkit.pdf documents in the $XILINX_EDK/third_party/doc directory." Joseph wrote: > > I created some IP with the EDK wizard. It is only a 64-bit > register--trying to understand how BFM simulation works before I > simulate my real design. The IP wizard generated files to do the > simulation. After following the readme provided (and fixing a bug or > two in the make file) I was able to get ModelSim to display the > waveform based on all the default files. I am assuming now to do my > own testing, I should modify the 'sample.bfl' file? Am I correct? If > so, I can't find any decent documentation on how to do so or that > describes this bus-functional language. If the sample.bfl is not the > right place to tweak things, where do I need to look? Anyone who has > done this before have any advice? I can provide more info on what I > have tried if it helps you to help me! > > Thanks, > JoeyArticle: 84593
Hi , I'm looking for a core in VHDL that does a vector product. Basically the following calculation: Out = Coeff(1) * In(1) + Coeff(2) * In(2) + ... +Coeff(n) * In(n) for n=15 or more. Note that input signal "In(i)" is not a time delayed signal, but rather a "present" time vector of data. Hence using a FIR core or similar would not do this. The input and coefficients are 12-bit minimum. I'm looking for a readily available core that is optimized for latency and space, preferrably a Xilinx core or other that allows for variable coefficient sizes and vector lengths. Anything would be helpful. Thanks, AndrewArticle: 84594
As John_H explained, he can derive the 1.44 MHz clock from the divide-by-25 counter, either synchronously or by decoding. But he may have to pay attention to the phase relationship between the internal 1.44 MHz operation (which is synchronous to the 36-MHz clock, and the 1.44 MHz clock being sent out. Considering the low freqiencies involved, there is enormous leeway... Peter AlfkeArticle: 84595
Hi Andrew, > I'm looking for a core in VHDL that does a vector product. Basically the > following calculation: > > Out = Coeff(1) * In(1) + Coeff(2) * In(2) + ... +Coeff(n) * In(n) > > for n=15 or more. > > Note that input signal "In(i)" is not a time delayed signal, but rather a > "present" time vector of data. Hence using a FIR core or similar would not > do this. The input and coefficients are 12-bit minimum. I'm looking for a > readily available core that is optimized for latency and space, > preferrably a Xilinx core or other that allows for variable coefficient > sizes and vector lengths. That's going to cost a lot of internal signals. However, this is easy to write yourself. Just use two arrays, Coeff and Input, and use a for loop to go through the array saying Result := Result + (Coeff(index) * Input(index)) Good luck! BenArticle: 84596
In article <afmdnXOed9voXA3fRVn-gA@rogers.com>, Andrew Lohbihler <andrewl@rogers.com> writes >Hi , > >I'm looking for a core in VHDL that does a vector product. Basically the >following calculation: > >Out = Coeff(1) * In(1) + Coeff(2) * In(2) + ... +Coeff(n) * In(n) > >for n=15 or more. > >Note that input signal "In(i)" is not a time delayed signal, but rather a >"present" time vector of data. Hence using a FIR core or similar would not >do this. The input and coefficients are 12-bit minimum. I'm looking for a >readily available core that is optimized for latency and space, preferrably >a Xilinx core or other that allows for variable coefficient sizes and vector >lengths. > >Anything would be helpful. Thanks, Core?, isn't this a multiplier, an accumulator, coef table, data table & a sequencer or am I missing something? Sounds like it could be run off in the time it takes to read the core documentation. -- fredArticle: 84597
Hi, Has anyone had success with running GHDL under an x86_64 distro? I use Suse 9.3 and I dont have the option of compiling from source. The binary version seems to generate regular (x86) instructions but the assembler is parsing them in "x86_64 mode", so it chokes on certain instructions which are invalid in that mode. I did find an option in GHDL's online docs for a switch to pass options to the assembler (-Wa,OPTION), and I tried to use the --32 option, but it didn't work. Any ideas? Thanks -JimArticle: 84598
Hi Hendra,
my clock is working at 50Mhz (20ns). I need a delay of
1micro second. Does this involve a counter that increments up to 50
(1*10us / 20*10ns = 50). Is this how you figure out the delay???
Thanks !!!!!!
Hendra wrote:
> The #sign delay is not synthesizable to the FPGA. But you still can
> implement a delay in different way. You can use a shift register or
use
> a simple logic and a big counter that will send the input to the
output
> once the counter reach a certain number. Note that in both cases, you
> must know in advance the speed of the clock before you can write the
> code to implement an accurate delay.
>
> Hendra
>
>
> Amir Intisar wrote:
> > Hi,
> > i am a newbee to FPGA design and i wanted to know how to add
> simple
> > delay in my Spartan 3 XC3S200 FPGA. I have a 16 bit digital signal
> > which comes from an imaging device(CCD) which may, for example
> > represent the data on pixel 1. What i want to do is first send the
> > pixel number to the computer, and then send the 16 bit data for
that
> > pixel to the computer.
> > The output on the computer may look like something below,
> >
> > 1 - pixel no. 1
> > 1345 - data for pixel 1
> >
> > 2 - pixel no. 2
> > 2431 - data for pixel 2
> >
> > 3
> > 1325
> >
> > So do i have to send out the pixel number , then have a delay and
> send
> > out the data for that pixel. Something like this??
> >
> > out = pixel;
> > #100 out = data_in;
> >
> > Thanks !!!!!!!!
Article: 84599Hiya, Ive lurked here for a while and have read the many arguments for and against designing a board or purchasing a dev board, well usually i would agree that a dev board is allot less hassle, however i recently got given a couple of spartan 3's and ive got everything else in my junk box i need to design my own board, so there is no cost issue involved, except my own which i am not concerned about. As FPGA design is new to me (its something i really want to get into) I was woundering whether you could prehaps clear me up some questions i have? 1) do i need to supply a clock to the spartan 3, or is there an on chip one? I have read the data sheets, prehaps not fully, but i couldnt see any special pins to supply a clock to on there pinout. 2)can i places all the chips for driving the jtag on the board permentantly with the fpga, or is it good practice to keep this off board? if so why? I think ive got all the important elements sorted, it was just these issues i was interested in, If anyone else can point me to a website with a basic schematic so that I can verify my design, I would be very grateful :-) thanks David
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