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Gary Pace wrote: >Hi Y'all : > >I have many years of experience with hardware design, software design & >implementation etc (i.e. I'm comfortable with C++, soldering or anything in >between) > >What am I missing ? What would be some examples of something better done in >VHDL ? Are there examples of stuff that cannot be done in schematic ? > > I also like schematics for "random" logic, such as a bus controller/decoder. But, there's some stuff that is just so much more concise in VHDL. One example is a Gray-binary or binary-Gray code converter. In schematic, it is a string of FFs and XORs. In VHDL, it is a parameterizable one-line statement, with the parameter being the # of bits. (I may be exaggerating the concise-ness just a little, but both of these functions were completely coded in 4-6 lines.) These were 48-bit converters for time codes. I also did an experiment just to stretch my VHDL writing skills and coded up a do-nothing box that (pseudo)randomly changed bits in a 10 x 10 array, and simultaneously refreshed a 10 x 10 grid of LEDs, like a raster scan. Each of those bits was a VHDL function, and each raster line looped through 10 bits, then the line looped through 10 iterations. I compared (mentally) what this would look like in the most concise hierarchical schematic, and the superiority of the HDL was pretty convincing. JonArticle: 84626
My Outlook Express or appears to have the code snippet excerpted as a
(non-readable) attachment.
Trying again:
An example in Verilog:
always @(posedge Clk_36MHz)
begin // counting 0-24, inclusive
count <= count + (enable ? -5'd24 : +5'd1);
enable <= (count==5'd24);
out_clk <= enable | (count<5'd12);
if( enable )
begin
// do everything here at
// 1.44 MHz, no gated clock
end
end
A gated clock would be:
wire ClkGated = Clk36MHz | ~enable;
always @(posedge ClkGated)
begin
// do everything at 1.44 MHz with severe clock skew
end
Which - it appears you know - isn't a great way to go.
> "Marco" <marcotoschi_no_spam@email.it> wrote in message
> news:d6plfi$o79$1@news.ngi.it...
> <snip>
> > > > What I could do?
>
> <snip>
>
> > > Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM
in
> > > frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use
that
> > > for your internal clock WITH a clock-enable for the whole thing once
> > > every 25 cycles. Also use that clock enable to drive an IOB register
> > > high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> > > duty cycle.
> > >
> > > Clean, workable.
>
> <snip>
>
>
Article: 84627On Mon, 23 May 2005 18:29:56 +0200, "Antti Lukats" <antti@openchip.org> wrote: >Hi all, > >FPGA are fun to work with ... when the tools work. >New versions of the tools come out, then serice packs, but there is no light >that the tools would actually work better. This is towards Xilinx tools. I >used lately also Quartus 4.2 for several desings and dont recall having any >tool related issues at all. > >http://wiki.openchip.org/index.php/ISE > >there are some my current identified problems with ISE 7.1, unfortunatly >backing up to 6.3 doesnt also work for me as the most needed feature has a >problem on 6.3 - chipscope core inserter makes the working design a non >working design. > >I can not belive that everything do try todo with Xilinx tools is so weird >that nobody else (e.g. xilinx internal testing team) has ever tried that. >But with almost anything I touch I see the tools either crash or not >properly working. > >Some issues are minor, and I can figure out some workarounds, that takes >time, but if the problem can be circumvented its ok. Some issues are more >fatal. At the moment the current state (of xilinx tools) really doesnt look >like the next service pack would resolve the major issues (those I am aware >of, there are mort likely many more of them). > >At the very present moment I am really in not good mood as I need to verify >some designs VERY URGENTLY and the tools just fail there where I need them. > >Antti Have you reported the issues to Xilinx ? I was at a seminar last week & a Xilinx guy said they are always keen to get hold of designs (under NDA if necessary) that break their tools so they can improve them.Article: 84628
"Mike Harrison" <mike@whitewing.co.uk> schrieb im Newsbeitrag news:436491941l4r0s9cvt5pkp6u1526fute26@4ax.com... > On Mon, 23 May 2005 18:29:56 +0200, "Antti Lukats" <antti@openchip.org> wrote: > > >Hi all, > > > >FPGA are fun to work with ... when the tools work. > >New versions of the tools come out, then serice packs, but there is no light > >that the tools would actually work better. This is towards Xilinx tools. I > >used lately also Quartus 4.2 for several desings and dont recall having any > >tool related issues at all. > >Antti > > Have you reported the issues to Xilinx ? > I was at a seminar last week & a Xilinx guy said they are always keen to get hold of designs (under > NDA if necessary) that break their tools so they can improve them. > have reported some, but have not opened any webcases lately, just hasnt enought time for that. the current major problem I have, seems only to be an issue of core inserter in 6.3 so using core generator and hand wiring what is more time consuming, well if it works and doesnt brake the desing I am happy with that for the moment. As of most other issues those are not so urgent burning so I can wait and see if the issues get fixed in next service packs. some issues are on my side too, namly I am refusing to have 3rd PC for xilinx design having only 2 seems to be insufficient AnttiArticle: 84629
You wrote: "But, there's some stuff that is just so much more concise in VHDL. One example is a Gray-binary or binary-Gray code converter. In schematic, it is a string of FFs and XORs. In VHDL, it is a parameterizable one-line statement, with the parameter being the # of bits." This is correct, but: I have seen people converting a binary counter output to Gray code, believing that this would allow glitchless decoding. Of course it does not: The delay differences on the binary side go straight through to the Gray side. If you are a Schemtosaurus, you easily see a solution: Re-synchronize the Gray output. And if you are clever, you drive the conversion not from the binary counter's Q outputs but from its D inputs. That keeps the two counters in step. I doubt that you would get this "picosecond" insight from VHDL code. Peter AlfkeArticle: 84630
"Marco" <marcotoschi_no_spam@email.it> writes: > Even if I use a 32 bit ISE version, may I download fedora 64 bit version? Webpack doesn't include a 64-bit verion. The full ISE release does. However, my license for ISE is only for BaseX, and that isn't supported for 64-bit. Before I realized that I tried to get it working, but I ran into many problems and switched to the 32-bit version, which mostly just needed some older libraries from FC2. EricArticle: 84631
Many Thanks to everyone. Following your instructions I have solved my trouble! Marco ToschiArticle: 84632
The ML401, ML402, ML403 boards were designed with the new ribbon connector style used with the PC-4 and USB cables. The older PC-3 cables can not directly plug in to this connector and I'm sorry, but we don't sell a conversion cable either. Ed kurapati wrote: > Hi > > I have parallel III cable and I tried to connect to JTAG interface > port on ML403 board but I found it difficult to connect because of > insufficient spacing between pins. > > any help please.. > > bye >Article: 84633
"Antti Lukats" <antti@openchip.org> wrote in message news:d6t5jr$dga$04$1@news.t-online.com... > > have reported some, but have not opened any webcases lately, just hasnt > enought time for that. > ..but you do have time to post on CAF about it? ;-) Cheers, Syms.Article: 84634
gralsto wrote: > Hi all, > I've been working on a project that has uses a FSM and have run out of > ideas about why it's not working. There are four states, an input > from off chip triggers the change between most states, except the > "00" state which automatically changes to the "01" state on the > rising edge of the clock. However, after running the design for a > while the state stops changing and is stuck in the "00" state, where > it should automatically change regardless of the input. Any ideas as > to why this is happening would be much appreciated. Included below is > my code. > > Thanks! > Jesse > Although your code is written as a binary-encoded state machine, if you use Xilinx XST you'll find that the tools will convert it into one-hot. If you're using Xilinx ISE, look for a line like: Optimizing FSM <FSM_3> on signal <state> with one-hot encoding. in your synthesis report. If this is the case, then I would agree that most likely you're running into a synchronizing issue causing the state machine to go "zero-hot". The logic that indicates your current state is encoded from the one-hot outputs and probably defaults to zero if no states are hot. One thing that can tell if this is really the case is to change your state "00" to something nonzero (be sure to initialize the machine to this state at config time). Then if the machine goes "zero-hot" your encoded output will still indicate state "00" which is obviously wrong. There are ways to force the synthesis tools to keep your state encoding if you prefer. In XST you need to be careful because the tools will er-encode to one-hot even if your preference for synthesis is "user defined." You need to check the constraints guide on how to work around this. Good luck, GaborArticle: 84635
"Symon" <symon_brewer@hotmail.com> schrieb im Newsbeitrag news:42922978$0$79459$14726298@news.sunsite.dk... > "Antti Lukats" <antti@openchip.org> wrote in message > news:d6t5jr$dga$04$1@news.t-online.com... > > > > have reported some, but have not opened any webcases lately, just hasnt > > enought time for that. > > > ..but you do have time to post on CAF about it? ;-) > > Cheers, Syms. > > sometimes, yes :) honeslty I was about to submit a web case a few week ago, but wasnt succesful at first attempt and later have not tried. as of the transition time from 6 to 7 its not so clear if it makes sense to submit bugs to version 6, after upgrading one PC to 7.1 I have not been able to recheck if the bugs with 6.3 I did see are fixed or not. So that one reason why I havent submittted the webcases. AnttiArticle: 84636
Thanks for the valuable hints. I registered the second MUX on the falling edge and everything is fine. Quick'n'dirty. ;-) Regards FalkArticle: 84637
Hi I have a problem with using "IBUFG" and "RAMB16_S9" in Project Navigator (ISE 6,3), when implementing. In VHDL, BRAM and IBUFG were just instantiated. When VHDL-simulating in modelsim, it was okay using UNISIM. When synthesizing with XST, no errors are found but following warning messages are seen. ------------------------------------------- WARNING:Xst:766 - c:/xilinx/work/TOP.vhd line 79: Generating a Black Box for component <IBUFG>. . . WARNING:Xst:790 - c:/xilinx/work/MODULE.vhd line 127: Index value(s) does not match array range, simulation mismatch. . .WARNING:Xst:766 - c:/xilinx/work/BLOCK.vhd line 81: Generating a Black Box for component <RAM16X1D>. . . WARNING:Xst:753 - c:/xilinx/work/RAM.vhd line 176: Unconnected output port 'DOP' of component 'RAMB16_S9' . . ------------------------------------------- Finally MAPPING errors are found as follows ------------------------------------------- ERROR:Pack:1234 - F5 mux symbol "AA_Mmux_data_inst_mux_f5_26111" drives more than one F6 mux symbol, including symbol "BB_Mmux__n0024_inst_mux_f6_10". An F5 mux may drive at most one F6. Please correct the design. ----- INFO:LIT:95 - All of the external outputs in this design are using slew rate limited output drivers. The delay on speed critical outputs can be dramatically reduced by designating them as fast outputs in the schematic. INFO:MapLib:562 - No environment variables are currently set. INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0: BUFG symbol "CLK_bufg" (output signal=clk_int2) ------------------------------------------- Can someone help me with this troubleshooting? Thankyou in advanceArticle: 84638
Howdy Gang ! It seems we have some sort of a problem with system reset in one of our SoC. It appears that after the board power up we have to press the external rest button to get the system 100% operational. Before hitting the rest button, it seems as most of the system is working but some parts are working "strangely". I have not traced the problem yet, as it is rather a complex SoC ... So I have a generic question to the group: My understanding was that all flops will be cleared automatically after the FPGA has been configured. How does the FPGA know which FLOPS have to be initialized to a '1' vs. a '0' ? How should I implement the rest such that it would specifically be asserted after FPGA configuration is done. Do I have to connect the GSR signal to my reset signal ? There seems to be very little inconclusive guidelines for this problem. Any pointers/information highly appreciated ! Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 84639
Simon Peacock wrote: > shame its so far away from Wellington Indeed - It's a bit of a challenge moving half-way around the world to get work :P JeremyArticle: 84640
"Jeremy Stringer" <jeremy@_NO_MORE_SPAM_endace.com> schrieb im Newsbeitrag news:42923b2e$1@clear.net.nz... > Simon Peacock wrote: > > shame its so far away from Wellington > > Indeed - It's a bit of a challenge moving half-way around the world to > get work :P > > Jeremy isnt it full-way (99.99%) around the world to get from Wellington to Hamilton? ;) a complete half-way (the opposite on the globe) from Wellington is my birth town Tallinn. AnttiArticle: 84641
First, the registers are not always cleared on power up. When asynchronous set/reset logic isn't used, synthesizers often bundle other logic into the synchronous set/reset pins of the flops beyond system set/reset. The FDS and FDSE primitives (anything with a set but not reset) power up to logic 1 unless the user overrides the value with an INIT=R attribute. The FD, FDR, FDRE, FDRS, FDRSE primitives (anything with a reset) power up to logic 0 unless the user overrides the value with an INIT=S attribute. I haven't included the register primitives with async set/reset in the lists but the idea carries through. Some synthesizers also support register initialization in the code, producing the INIT=S and INIT=R attributes from the initializations. To get a synchronous reset into the design without pressing a reset *I* would just use a countdown that starts at power up and keeps the system in reset (except for the counter) until the count expires. I don't want to get in the business of async resets without additional controls to guarantee the deassertion of reset is synchronous where needed. "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:d6tc1s$ol4$1@nobel.pacific.net.sg... > > Howdy Gang ! > > It seems we have some sort of a problem with system reset in > one of our SoC. > > It appears that after the board power up we have to press the > external rest button to get the system 100% operational. Before > hitting the rest button, it seems as most of the system is > working but some parts are working "strangely". > > I have not traced the problem yet, as it is rather a complex > SoC ... > > So I have a generic question to the group: > > My understanding was that all flops will be cleared automatically > after the FPGA has been configured. How does the FPGA know > which FLOPS have to be initialized to a '1' vs. a '0' ? > > How should I implement the rest such that it would specifically > be asserted after FPGA configuration is done. Do I have to > connect the GSR signal to my reset signal ? There seems to be > very little inconclusive guidelines for this problem. > > Any pointers/information highly appreciated ! > > Best Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis >Article: 84642
Just to confirm and expand on John_H's posting: At the end of configuration, Xilinx applies an asynchronous (p)reset to all flip-flops. That's the good news. The bad news is that the trailing edge of this initialization signal, even when it has been synchronized to the clock, has such a long propagation delay, that it often straddles several incoming clock periods. As a result, state machines can get half initiated and half running. The user is advised to augment the "free" initialization with deliberate synchronous initialization of critical flip-flops. Peter Alfke, Xilinx Applications.Article: 84643
Hi.. I am currently working with Xilinx ISE 6.3i ..The design is in VHDL..I tried adding some extra inputs and outputs to the top level entity and hence made the corresponding changes to the UCF file. But when I try implementing the design, it shows errors in the Map process as follows: 1) The extra inputs I added in the UCF file are shown as invalid I have just used the format for example: NET "my_input_name" LOC = "P34" ; 2)Should I also add INST? If so how should I do that and is it for all the component instantiations? 3)When should I use | IOSTANDARD = LVTTL | PULLDOWN ? I then removed the unused inputs and outputs but it still shows the same error... Any suggestions are welcome.. Thanks in advance, MethiArticle: 84644
"Gary Pace" <xxx@yyy.com> wrote in message news:5Kvje.113165$AE6.112367@tornado.texas.rr.com... > What am I missing ? What would be some examples of something better done > in VHDL ? Are there examples of stuff that cannot be done in schematic ? Hello, I have never used a HDL, but I have an opinion anyway, this is usenet. I have a hardware and firmware (C and asm) background and recently picked up an existing schematic based fpga design for modification. My first fpga. What I miss most is the ability to compare the file I am looking at to last weeks version, or the version that Joe modified. I have not found a way to do that with schematics. I have gotten very used to this for firmware. If there are any software types looking for a project, I would pay for a tool to do this. BenArticle: 84645
I'm using a Nallatech development board that allows access through PCI to the chip. I'm outputting the value of the state machine to a register that is read by a C program running on the host computer. This is how I know it is stuck in the "00" state. I originally had a reset state in the process, but took it out when I hit the "lets try some random stuff" phase of trying to find out what was happening with the design. I'll try removing the clocking from the second process, but I know the clock is still running as other parts of the design that are clocked are still firing away. My other thought today is to try to do it a bit bassackwards by removing it from a "process" and try doing each part explicitly, shouldn't matter but maybe the synthesis tool is doing somthing odd and I can get it to do it another way? Thanks for the comments to far! -JesseArticle: 84646
Welp, I ended up implementing a process that uses explicit if/elsif statements to cover all cases and it appears to be working. Only thing I could think of is that Xilinx's synthesis tool was doing something odd that made it go into a random state, even though all states should have been covered. Not sure if I really like the solution, but if it works I guess I'll take it. Thanks for the ideas everyone. -JesseArticle: 84647
Hello: does anyone have a positive experience with Quartus /Linux using a JTAG interface ? Does it work well? What is the price of the hardware? Thanks.Article: 84648
which is your primary FPGA supplier? I cant go back to Xilinx again. Jeremy Stringer wrote: > For anyone that's interested, my company (Endace Technology Ltd) is > looking for VHDL engineers (And embedded software people and linux > driver/kernel developers). > > We're a small (but rapidly growing) company based in Hamilton, New > Zealand developing network measurement and acceleration products. > Overseas people are welcome (but have to have an appropriate degree and > three years of experience for immigration). > > If you're interested, the company website is http://www.endace.com, and > I may be able to answer a few questions - I'm an engineer, not an HR > person though, so for more specific information you would need to email > our HR people (vacancies@endace.com). > > Let me know if you're interested - we've all been asked to keep an ear > out for people :) > > JeremyArticle: 84649
Thanks! "Matthieu MICHON" <matthieu.michonRemove@laposte.net> schrieb im Newsbeitrag news:42927bcd$0$4866$626a14ce@news.free.fr... > Antti Lukats wrote: > (...) > > the current major problem I have, seems only to be an issue of core inserter > > in 6.3 > (...) > > Antti > > Hi Antti > > > I experienced the same issue. It seems that the RPM implementation in > ISE 6.3 is kind of broken, and since the "Use RPMs" attribute is active > by default in the CSP Core Inserter, the design implementation is very > likely to fail with default settings. > > A simple turn-around is to un-check the "Use RPMs" attribute (located in > the Device panel of the CSP Core Interter). > > Hope this help ;) > > > Matthieu (who also would be pleased to see native Mac OS X support for > EDA tools) Thanks! Antti, is hopefully not attacted for saying thanks in both top and bottom posting style :)
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