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Okay, we're looking for something that will work at ~1-10ua of power consumption at 1.5v, which makes us much lower power than cell-phones (I'm guessing several orders of magnitude). And we're looking for something that is pennies to produce in large volumes. That's why I'm guessing we rule out CPLDs and FPGAs. Thanks, Dave.Article: 88251
Oh, forgot to mention. That's peak power. We need to be in the tens of nanoamps during sleep mode which is the bulk of the time. Dave.Article: 88252
"Antti Lukats" <antti@openchip.org> wrote in message news:ddg1jp$7rh$01$1@news.t-online.com... > Hi > > I wonder if Xilinx does any testing of their releases at all - Unfortunately, I gotta agree with this one. Been using their software since ~1990 and everytime we update we go through the same thing.... the search for the newly broken function. -- Ed > creating Hard > Macros seems to be impossible in 7.1 as the FPGAeditor self terminates > itself on any attemp to add extpin. Well it seems to be that 6.3 made hard > macros are compatible and useable in 7.1 but its very awkward to keep a > copy > of 6.3 only for that purpose. > > Antti > PS to Xilinx, yes I did open a WebCase. I have plenty of webcases open. So > far NO HELP. > > >Article: 88253
<bret.wade@gmail.com> schrieb im Newsbeitrag news:1123876948.678140.112150@g49g2000cwa.googlegroups.com... > This issue is covered by Answer Record 21615. A patch is available. It > will also be fixed in SP4. > > http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=21615 > > Bret Wade > Xilinx Product Applications > Thank you Bret, yes that tactical patch fixed the issue. I did not expect patches to be available for SP3 so did not even search for those. suggestion - please please maintain a list of 'patches' for all SP's at some single location that would help finding them. AnttiArticle: 88254
"dave94024" <david.pariseau@sbcglobal.net> schrieb im Newsbeitrag news:1123887528.001958.38830@z14g2000cwz.googlegroups.com... > Oh, forgot to mention. That's peak power. We need to be in the tens > of nanoamps during sleep mode which is the bulk of the time. > > Dave. > try contacting http://www.emmicroelectronic.com I bet they will do the job for you at your quantities you can also try melexis, but I bet EM is better choice Antti BTW, thank you for your posting, thanks to it I found that EM is now also offering SO-8 packaged MCU's that new and I did not know that before.Article: 88255
>suggestion - please please maintain a list of 'patches' for all SP's at some >single location that would help finding them. Xilinx is generally pretty good at setting up their site so google can find things. Can you find the patch from google? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 88256
"Hal Murray" <hmurray@suespammers.org> schrieb im Newsbeitrag news:d8OdnS-OspG9GGDfRVn-uA@megapath.net... > >suggestion - please please maintain a list of 'patches' for all SP's at some > >single location that would help finding them. > > Xilinx is generally pretty good at setting up their site so google > can find things. Can you find the patch from google? > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam. > I guess it may show up, but when trying normal queries fpgaeditor crash extpin then it the patch does not show up in xilinx google search I only found it after searching by AR number given by Bret, otherwise I would not have found it all. Antti PS Xilinx WebCase on this issue did not even contact my til now - so the c.a.f. response was WAY faster, thanks again Bret! Yes I did close the webcase as it was actually addressed by AR what I did not find until givent the correct number of the AR.Article: 88257
I am simulating a IPIF + user core using the BFM simulation model and in my test I can succesfully write to the WFIFO (write fifo) and write to the RFIFO (read fifo) but for some reason the data from the read fifo doesn't get dumped to the IP2BUS_DATA (Data Bus) is there any signal that I should assert from the IPIF interface to dumped the data from the RFIFO to the bus? Thanks, NoelArticle: 88258
After dealing with ISE7.1 for a couple of days trying to install it under Fedora, Whitebox and some other distro I forgot, I gave in and installed CentOS3 (3.4 I believe); it installed on the first try and runs nicely. It's a RHEL3 clon, so all the libraries should match. HTH, -P@Article: 88259
Hallo,
I have developed an opb spi 16 bit peripheral with regiter support to
interface it to bus.
Here c code:
unsigned int (*control_reg) = (unsigned
int(*))XPAR_OPB_SPI_16_BIT_0_BASEADDR + OPB_SPI_16_BIT_SLAVE_REG2_OFFSET;
int main (void) {
(*control_reg) = 10;
xil_printf("%X %X\n", &(*control_reg), XPAR_OPB_SPI_16_BIT_0_BASEADDR +
OPB_SPI_16_BIT_SLAVE_REG2_OFFSET);
Using "unsigned int" the two address to be printed don't match. If I use
"unsigned char" they match, but in this way I truncate some datas because
they are 16 bit registers.
What could I do?
Many Thanks
Marco
Article: 88260Hi, Thanks for giving me the basic concept of what Rapid Prototyping is. Can u please mention me some websites that deal with the Rapid Prototyping technology. Thanks, Greetings, SarathArticle: 88261
I solved a part of my trouble.
Here the c code:
#define OPB_SPI_16_BIT_SLAVE_REG0 (XPAR_OPB_SPI_16_BIT_0_BASEADDR +
OPB_SPI_16_BIT_SLAVE_REG0_OFFSET)
#define OPB_SPI_16_BIT_SLAVE_REG1 (XPAR_OPB_SPI_16_BIT_0_BASEADDR +
OPB_SPI_16_BIT_SLAVE_REG1_OFFSET)
#define OPB_SPI_16_BIT_SLAVE_REG2 (XPAR_OPB_SPI_16_BIT_0_BASEADDR +
OPB_SPI_16_BIT_SLAVE_REG2_OFFSET)
unsigned int (*buffer_rx) = (unsigned int(*))OPB_SPI_16_BIT_SLAVE_REG0;
unsigned int (*buffer_tx) = (unsigned int(*))OPB_SPI_16_BIT_SLAVE_REG1;
unsigned int (*control_reg) = (unsigned int(*))OPB_SPI_16_BIT_SLAVE_REG2;
int main (void) {
(*control_reg) = 125;
xil_printf("%d\n", (*control_reg));
xil_printf("%d\n",
OPB_SPI_16_BIT_mReadSlaveReg2(XPAR_OPB_SPI_16_BIT_0_BASEADDR));
Now I should see:
125
125
Instead, even if now the address of (*control_reg) seems to be correct, I
see:
125
0
What could I do?
Many Thanks
Marco
Article: 88262Hello Peter, I have a small code snippet: U_IBUF_Key1: IBUF port map(I => InKey1, O => Key1); U_OBUF_Key1: OBUF_S_2 port map(I => Key1, O => InKey1); Key1Out <= Key1; U_IBUF_Key2: IBUF port map(I => InKey2, O => Key2); U_OBUF_Key2: OBUF_S_2 port map(I => Key2, O => InKey2); Key2Out <= Key2; I think, it describes the schematic proposed by you in your article "Six Easy Pieces (Non-Synchronous Circuit Tricks)" from 04/02/2003. I have a copy of ISE 7.1.03 and I have a copy of Synpicity Synplify 8.1. I tried to synthesize and implement the proposed code snippet. Both synthesis tools generate warning about combinatorial loops existence, but still generate output files. In time it comes to implementation the ISE during map phase prints the following error message and fails the implementation: MapLib:661 - LUT2 symbol "N_14_i" (output signal=N_14_i) has input signal "U_IBUF_Key2" which will be trimmed. See the trim report for details about why the input signal will become undriven. Trim report states the following: The signal "InKey1" is unused and has been removed. The signal "InKey2" is unused and has been removed. The signal "U_IBUF_Key2" is unused and has been removed. The signal "U_IBUF_Key1" is unused and has been removed. We invented the following hack, effectively adding register between IBUF and OBUF. U_IBUF_Key1: IBUF port map(I => InKey1, O => Key1); process (Clk) begin if rising_edge(Clk) then Key1Reg <= Key1; end if; end process; U_OBUF_Key1: OBUF_S_2 port map(I => Key1Reg, O => InKey1); Key1Out <= Key1; U_IBUF_Key2: IBUF port map(I => InKey2, O => Key2); process (Clk) begin if rising_edge(Clk) then Key2Reg <= Key2; end if; end process; U_OBUF_Key2: OBUF_S_2 port map(I => Key2Reg, O => InKey2); Key2Out <= Key2; Now the project can be synthesized and implemented, but the circuit is not asynchronous any more. What is the trick in the starting idea? Are we missing some secret word in VHDL source or some mysterious command line switch during synthesis and implementation? Is there any way to avoid message about combinatorial loops, since it kind irritating? With best regards, Vladimir S. MirgorodskyArticle: 88263
<v_mirgorodsky@yahoo.com> wrote in message news:1123934096.377073.5060@z14g2000cwz.googlegroups.com... > Hello Peter, > > I have a small code snippet: > > U_IBUF_Key1: IBUF port map(I => InKey1, O => Key1); > U_OBUF_Key1: OBUF_S_2 port map(I => Key1, O => InKey1); > Key1Out <= Key1; > > U_IBUF_Key2: IBUF port map(I => InKey2, O => Key2); > U_OBUF_Key2: OBUF_S_2 port map(I => Key2, O => InKey2); > Key2Out <= Key2; > > I think, it describes the schematic proposed by you in your article > "Six Easy Pieces (Non-Synchronous Circuit Tricks)" from 04/02/2003. I > have a copy of ISE 7.1.03 and I have a copy of Synpicity Synplify 8.1. > I tried to synthesize and implement the proposed code snippet. Both > synthesis tools generate warning about combinatorial loops existence, > but still generate output files. In time it comes to implementation the > ISE during map phase prints the following error message and fails the > implementation: > > MapLib:661 - LUT2 symbol "N_14_i" (output signal=N_14_i) has input > signal "U_IBUF_Key2" which will be trimmed. See the trim report for > details about why the input signal will become undriven. > > Trim report states the following: > > The signal "InKey1" is unused and has been removed. > The signal "InKey2" is unused and has been removed. > The signal "U_IBUF_Key2" is unused and has been removed. > The signal "U_IBUF_Key1" is unused and has been removed. > > We invented the following hack, effectively adding register between > IBUF and OBUF. > U_IBUF_Key1: IBUF port map(I => InKey1, O => Key1); > process (Clk) begin > if rising_edge(Clk) then > Key1Reg <= Key1; > end if; > end process; > U_OBUF_Key1: OBUF_S_2 port map(I => Key1Reg, O => InKey1); > Key1Out <= Key1; > > U_IBUF_Key2: IBUF port map(I => InKey2, O => Key2); > process (Clk) begin > if rising_edge(Clk) then > Key2Reg <= Key2; > end if; > end process; > U_OBUF_Key2: OBUF_S_2 port map(I => Key2Reg, O => InKey2); > Key2Out <= Key2; > > Now the project can be synthesized and implemented, but the circuit is > not asynchronous any more. > > What is the trick in the starting idea? Are we missing some secret word > in VHDL source or some mysterious command line switch during synthesis > and implementation? Is there any way to avoid message about > combinatorial loops, since it kind irritating? > > With best regards, > Vladimir S. Mirgorodsky > Jeez... I do wonder about this high level language stuff sometimes - with schematic capture draw two 2 i/p nand gates. connect the output of each one to an input of the other. Connect the pole of the switch to earth. connect each of the other outputs to the free input of each nand gate. Also pull up that input to Vcc via a 10k resistor. Take the output from the appropriate nand gate. Sorted. In hardware terms it is a set-reset flipflop. SlurpArticle: 88264
Hello Slurp, I am not looking for solution for this issue, since we get the problem solved in different way, but still solved. I am trying to learn synthesis tools and the ways how to work with tools in effective way. Since Peter Alfke published his article he managed to synthesize and implement this part of design and I am wondering about the way he did it. With best regards, Vladimir S. MirgorodskyArticle: 88265
Excellent! I just downloaded it and will try it out. Thanks! Dave "Andy Peters" <Bassman59a@yahoo.com> wrote in message news:1123878486.446093.174910@z14g2000cwz.googlegroups.com... > Dave wrote: >> Is there a freeware (or reasonable cost... i.e no annual renewal fee >> involved and a cost a hobbiest could afford) C compiler for the PicoBlaze >> available? >> >> I'd like to experiment with an embedded processor on a Spartan 3 (with >> the >> Xilinx development board) but prefer not to spend an arm-and-a-leg to get >> there :) > > http://www.poderico.co.uk/PCCOMP.htm >Article: 88266
Hi Antti, You would have had your solution a day earlier if you'd put a little more effort into the Answers search. Something like "7.1i add external pin" works for this case. You can't always depend on your posting being read by the person who wrote the Answer Record. There is another FPGA Editor issue that you may run into: http://www.xilinx.com/xlnx/xil _ans_display.jsp?getPagePath=21667 Regards, BretArticle: 88267
On 13 Aug 2005 06:40:21 -0700, v_mirgorodsky@yahoo.com wrote: >Hello Slurp, > >I am not looking for solution for this issue, since we get the problem >solved in different way, but still solved. I am trying to learn >synthesis tools and the ways how to work with tools in effective way. >Since Peter Alfke published his article he managed to synthesize and >implement this part of design and I am wondering about the way he did >it. > >With best regards, >Vladimir S. Mirgorodsky The schematic you saw in the article was almost definitely not the result of synthesis. It was drawn in a schematic tool and exported to edif to be input to the mapper directly. Your problem is most probably not inferring the right IO. I doubt if there are any LUTs generated by the schematic you're looking at. You should investigate the output of synthesis tool to see what components it generated and see if they look anything like the schematic. Synthesis tools are not very good at generating non-trivial IO functionality. You'll probably have to learn have to set some properties on your components.Article: 88268
> Here c code:
>
> unsigned int (*control_reg) = (unsigned int(*))XPAR_OPB_SPI_16_BIT_0_BASEADDR + OPB_SPI_16_BIT_SLAVE_REG2_OFFSET;
>
> int main (void) {
> (*control_reg) = 10;
> xil_printf("%X %X\n", &(*control_reg), XPAR_OPB_SPI_16_BIT_0_BASEADDR + OPB_SPI_16_BIT_SLAVE_REG2_OFFSET);
>
> Using "unsigned int" the two address to be printed don't match. If I use
> "unsigned char" they match, but in this way I truncate some datas because
> they are 16 bit registers.
Hi Marco,
You're doing pointer arithmatic here, which is not the same as just adding
addresses. If you add a number to a pointer of a specific type, the pointer
will be increased by the number times the size of the type.
for example, on a 32 bit system, the following snippet of code
int *p = 100;
p = p + 5;
wil result in p being 120, not 105 as you might expect, since sizeof(int) equals 4, and
100 + (5*4) = 120.
If you want to add a specific number of bytes to a pointer, typecase the
pointer to char before adding :
int *p = 100;
p = (char *)p + 5;
will result in p = 105.
_Ico
--
:wq
^X^Cy^K^X^C^C^C
Article: 88269Hey! SUpposing im using Xilinx ISE 4.2, how do I go about creating an EDIF file to load into this as thats the only thing I seem to be able to import into the 4.2v So what do I need to do? somehow find a compiler? or a simulator? will these output and EDIF from my VHDL? I did a google filetype:edif search to see whether this helps me explain it further to myself, but it seems like a net list or something that you create after placing the cells (or what ever its called) and I havent done that, Ive typed my VHDL and made a UCF file, so what now? Can anybody give me an overview (ASSII flow chart?? heh) of what I need to do from VHDL to sythesising with ISE 4.2? its the steps in the middle I can't figure out! sorry everybody! SvenArticle: 88270
That is really my concern. I checked the resulting EDIF and I found there input and output buffers, connected exctly the same fashion, like in schematic. The problem actually caused by the mapper throwing out the IBUF from the netlist and rendering InKey1 and InKey2 pins as unused.Article: 88271
I thought of this circuit, drew it with a pencil on a piece of paper, and analyzed it in my head. And I bredboarded it many years ago, without using any synthesis tool. I know it works, but I have not tried to sneak it past the security guards in the newer tools. Who claims that progress is always moving forward ? Peter AlfkeArticle: 88272
EM looks perfect for our application. Thanks! Dave.Article: 88273
thank you for all the advices and information. I see, it is complicated. But one thing i forgot to mention is that the image will be having CIS resolution, maximum will be about 500H * 200 V pixels and that im OK with monochrome images. One other question. what is the typical lifetime of CMOS image sensor, provided it will be used in continuous aqusition of images ( 24 x 7 - whole day, whole week ) at its maximum allowable speed. can some one give me some sites doing FPGA dev boards with PCI interface? Thank you. CMOSArticle: 88274
>One other question. >what is the typical lifetime of CMOS image sensor, provided it will be >used in continuous aqusition of images ( 24 x 7 - whole day, whole week >) at its maximum allowable speed. I can't think of any reason it would wear out. So I'd expect it to last as long as a CPU or memory chip as long as you are following the rules in the data sheet. >can some one give me some sites doing FPGA dev boards with PCI >interface? First link on: http://www.fpga-faq.org/ -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z