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Messages from 89175

Article: 89175
Subject: Re: spartan 3 starter kit auto configuration at power up
From: "Marco" <marcotoschi@nospam.it>
Date: Wed, 7 Sep 2005 13:36:33 +0200
Links: << >>  << T >>  << A >>

"CMOS" <manusha@millenniumit.com> wrote in message 
news:1126033955.739719.77870@g47g2000cwa.googlegroups.com...
> hi
> how do we program the spartan 3 starter kit to load the configuration
> from PROM automatically at start up.
> Thank you.
> CMOS
>

At Xilinx site: XAPP482.pdf

Marco 



Article: 89176
Subject: Re: Spartan 3 Ram Instantiation
From: amir.intisar@gmail.com
Date: 7 Sep 2005 06:23:27 -0700
Links: << >>  << T >>  << A >>
Hey John, thanks for all the information and i will try that piece of
code you have given me, but how do i assign the FPGA pins to reg [15:0]
ADCvals [12287:0]; . Its basically  -  [data_in]ADCvals[inAddr]. DO i
just have to assign the "inAddr" to the SRAM address pins and not worry
about the data pins?. Also, can "inAddr" and "rdAddr" be incrementing
numbers?. I want to start at memory address 0 and store the incoming
data up to 12,000. Once completed, i want to start at 0 again and send
out the data until i reach memory address 12,000. I was hoping to just
have an number that increments, something like this,

[15:0] ADCvals [i] <= ADCinVal;
i <= i + 1;
//wait for next value

Thanks Mate !!!


Article: 89177
Subject: Re: Cyclone conf flash - 25p10 !
From: "jai.dhar@gmail.com" <jai.dhar@gmail.com>
Date: 7 Sep 2005 06:28:29 -0700
Links: << >>  << T >>  << A >>
ST Micro's flash devices can be used instead since they are drop in
replacements, correct? They are much cheaper.


Article: 89178
Subject: Re: bare die (non packaged) FPGA, CPLD, controllers ?
From: "Dix" <mystery@gmail.com>
Date: 7 Sep 2005 06:29:12 -0700
Links: << >>  << T >>  << A >>
Thanks, Jon.
That's a good hint.
Also found: http://www.dieproduct.com/ , if someone else is in that.

Cheers, Dix.


Article: 89179
Subject: Re: Cyclone conf flash - 25p10 !
From: "Luis Cupido" <cupidoREMOVE@REMOVEua.pt>
Date: Wed, 7 Sep 2005 14:54:47 +0100
Links: << >>  << T >>  << A >>
The ones I use are the 25P10A from ST. (25P10AV-ST)

lc.


"Al Clark" <dsp@danvillesignal.com> wrote in message 
news:Xns96C9E2219E5EEaclarkdanvillesignal@66.133.129.71...
> "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote in
> news:newscache$0vhemi$3um$1@newsfront4.netvisao.pt:
>
>> Hi,
>>
>> I've been using the 25P10 flash to configure cyclone devices,
>> as far as I can see they are exactly equal to the  EPCS1
>> (even silicon ID is the same, I suspect it is the same chip inside)
>>
>> All altera devices (in AS) I tested can read it and configure fine,
>> however the Quartus II fail to load data into the 25P10...
>> (I must use another software to load the 25p10 and that is less
>> convenient)
>>
>> Does anybody knows why... what is the trick used ?
>>
>> Luis C.
>>
>>
>>
>>
>
> This is very interesting since the configuration roms are expensive
> compared to typical SPI flash. I noticed that Lattice is pushing the fact
> that they can configure using cheap standard SPI flash.
>
> Do you use the 25p10 A version. Have you tried SST parts?
>
>
> -- 
> Al Clark
> Danville Signal Processing, Inc.
> --------------------------------------------------------------------
> Purveyors of Fine DSP Hardware and other Cool Stuff
> Available at http://www.danvillesignal.com 



Article: 89180
Subject: Re: Defining Environment variables inside EDK
From: Sylvain Munaut <com.246tNt@tnt>
Date: Wed, 07 Sep 2005 15:59:43 +0200
Links: << >>  << T >>  << A >>
Amit Kasat wrote:
> Sylvain Munaut wrote:
> 
>> Hi,
>>
>> I need to define some environment variable to
>> change the behavior of the synthesis tool in order
>> for my design to compile (XIL_PLACE_ALLOW_LOCAL_BUFG_ROUTING).
>>
>> I'd like to define that inside the EDK project, without having to modify
>> my system or user wide environment. I've tried adding that to the
>> system_incl.make but that file is overwritten at each build ...
>>
>> What's the proper way to do that ? The search I've done so far didn't
>> get many relevant results ...
>>
>>
>>     Sylvain
>>  
>>
> Sylvain,
>    Create a copy of system.make (call it mysystem.make) and in XPS
> Project Options dialog box, point XPS to this makefile. In this
> makefile, you can set the environment variable. Note that
> system_incl.make and system.make are always overwritten, but you can
> point XPS to use your own makefile (which is to replace system.make) and
> thus change environment.
> 
> Thanks,
> Amit

Yes great thanks !


	Sylvain

Article: 89181
Subject: Re: Cyclone conf flash - 25p10 !
From: "Luis Cupido" <cupidoREMOVE@REMOVEua.pt>
Date: Wed, 7 Sep 2005 15:07:35 +0100
Links: << >>  << T >>  << A >>
Hi,

> Then SOMETHING must be different ?

Right :)
... but only Quartus II knows how to check that

One hypothesis is that the EPCS devices come from altera
with something on memory to tell that they are from altera.
and Quartus II also writes something to keep this
thread going. Would that be the trick ?

That was what I would like to know ;)
I'm sure I'm not the first one to use the 25P10A

Anyone can use them, just make an RBF file on quartus
and send it to the 25P10A using other software than quartus.

lc.


"Jim Granville" <no.spam@designtools.co.nz> wrote in message 
news:431e780e$1@clear.net.nz...
> Al Clark wrote:
>> "Luis Cupido" <cupidoREMOVE@REMOVEua.pt> wrote in
>> news:newscache$0vhemi$3um$1@newsfront4.netvisao.pt:
>>>Hi,
>>>
>>>I've been using the 25P10 flash to configure cyclone devices,
>>>as far as I can see they are exactly equal to the  EPCS1
>>>(even silicon ID is the same, I suspect it is the same chip inside)
>>>
>>>All altera devices (in AS) I tested can read it and configure fine,
>>>however the Quartus II fail to load data into the 25P10...
>
> Then SOMETHING must be different ?
>
>>>(I must use another software to load the 25p10 and that is less
>>>convenient)
>>>Does anybody knows why... what is the trick used ?
>>>
>>>Luis C.
>>
>> This is very interesting since the configuration roms are expensive 
>> compared to typical SPI flash. I noticed that Lattice is pushing the fact 
>> that they can configure using cheap standard SPI flash.
>>
>> Do you use the 25p10 A version. Have you tried SST parts?
>
> ... and you will see Xilinx have also hopped on this bandwaggon,
> with their newest Spartan 3E's - much hoopla about std SPI and also
> NOR flash loader options.
>  It cost them ~3 pins, to select the vendor/state engine for a given SPI
> memory.
>  Not before time, but it will mean Altera have to step into line as well, 
> and remove any 'deliberate' hurdles that might have found their
> way into their tool flows ( if that's really what's occured ? )
>
> -jg
>
>
> 



Article: 89182
Subject: ISE 64bit question
From: "Matthew Plante" <maplante@iol.unh.edu>
Date: Wed, 7 Sep 2005 10:26:23 -0400
Links: << >>  << T >>  << A >>
XST 7.1i says that it has support for redhat linux enterprise 64 bit 
edition.  I installed enterprise 3 on a system we have, which is a quad 
Itanium 2.  However, I can't get the xst binaries to execute.  Apparently 
the binaries provided only work on AMD cpus?  Is there an Intel 64bit 
version available??

xilsetup: ELF 64-bit LSB executable, AMD x86-64, version 1 (SYSV), for 
GNU/Linux 2.4.0, dynamically linked (uses shared libs), not stripped

/sbin/init: ELF 64-bit LSB executable, IA-64, version 1 (SYSV), for 
GNU/Linux 2.4.0, dynamically linked (uses shared libs), stripped

./xilsetup
bash: ./xilsetup: cannot execute binary file

Thanks,

-- 
-- Matt

+--
|Matthew Plante
| University of New Hampshire
| InterOperability Lab
| Research & Development
| SMTP: maplante@iol.unh.edu
| Phone: +1-603-862-0203
+-



Article: 89183
Subject: Re: Spartan-3E Starter Kit availability slips to December
From: "Alex Gibson" <news@alxx.net>
Date: Thu, 8 Sep 2005 00:38:44 +1000
Links: << >>  << T >>  << A >>

"Eric Smith" <eric@brouhaha.com> wrote in message
news:qhirxdvk6x.fsf@ruckus.brouhaha.com...
> I've been eagerly awaiting the September arrival of the Spartan-3E
> Starter Kit, but today the Xilinx Online Store indicates that the
> target availability is now December 2005.
>
> Sigh.
>
> I'll have to lay out my own board and try to get some XC3S500E chips
> through distribution.  Though I'll still likely buy the start kit when
> it becomes available.

Some one said Digilentinc was going to have
their s3e board ready for sale in about a month.




Article: 89184
Subject: Re: Simulation problems with EDK 7.1.02i and ModelSim SE 6.1a
From: Jiri Bucek <bucekj@cslab.felk.cvut.cz>
Date: Wed, 07 Sep 2005 17:14:21 +0200
Links: << >>  << T >>  << A >>
Experienced the same problem. It seems that it is a bug in 6.1a ModelSim 
version, because I've never faced a similar problem with the same EDK 
libraries in 5.x ModelSim versions.

However, the whole problem is in a VHDL construction that is somehow 
incorrectly interpreted by ModelSim when compiled with default (-O4) or 
higher optimization enabled. Here is a snippet of park_lock_logic.vhd 
(opb_arbiter_v1_02_e), which causes that FATAL ERROR:

GRANT_GEN: for i in 0 to C_NUM_MASTERS-1 generate

         -- ... skipped some code

         -- Register the grant signals if registered grant outputs
         -- reset this register with park_fe
         REGGRNT_GEN: if (C_REG_GRANTS) generate
             REGGRNT_PROCESS: process (Clk, park_fe(i))
             begin
                 -- asynchronously reset when park negates
                 if park_fe(i) = '1' then
                     mgrant_reg_i(i) <= '0';
                 elsif Clk'event and Clk='1' then
                     if Rst = RESET_ACTIVE then
                         mgrant_reg_i(i) <= '0';
                     else
                         mgrant_reg_i(i) <= mgrant_i(i);
                     end if;
                 end if;
             end process REGGRNT_PROCESS;
         end generate REGGRNT_GEN;
end generate GRANT_GEN;

The problem lies in the sensitivity list of the process, where a vector 
selection is used (i.e. park_fe(i) in this case). In my opinion, the 
VHDL construct is correct and should work.

To workaround the problem, at least two approaches may be used:
(a) replace the vector selection by the whole vector (i.e. use park_fe 
instead of park_fe(i)),
(b) recompile the mentioned source with -O1 optimization

Solution (a) requires that you locate all VHDL files with similar 
constructs and update them. However, this seems a bit complicated.

To apply workarround (b), a little "hack" of Xilinx's compedklib utility 
is necessary since it hasn't any means to specify -O1 optimization 
level. To overcome this problem, locate HdlModelCompiler.pm file in your 
EDK\bin directory and update runCmd("vcom ...") expressions to include 
-O1. Then, when you run compedklib (or, in Xilinx Platform Studio, 
select Options -> Compile Simultion Libraries), the proper optimization 
level will be used and the FATAL ERROR shouldn't occur any more. 
Unfortunately, using lower optimization level will affect performance of 
your simulation. So it's up to you, which kind of workaround (or if you 
find another one) to use.

Best regards,
Tomas Brabec & Jiri Bucek


Brian C. Van Essen wrote:
> I am attempting to simulate a very basic system built with Xilinx EDK 
> 7.1.02i, using VHDL.  After generating the ModelSim specific compiler 
> scripts, I can execute a do system.do, which works okay, but when I 
> execute the vsim system command I get the following results.  I have had 
> similar problems when trying to do a Verilog/VHDL mixed simulation 
> system.  Looking around on the Xilinx web site, I see that someone else 
> has had a similar problem 
> (http://toolbox.xilinx.com/cgi-bin/forum?50@233.ec6BaE6ihO8.4@.ee8f9bc), 
> but I did not see any responses or suggestions.
> 
> Any help would be appreciated.
> 
> Thanks,
> Brian
> 
> -------------
> 
> ModelSim> vsim system_conf system
> # vsim system_conf system
> # Loading c:\Modeltech_6.1a\win32/../std.standard
... (cut out) ...
> Loading 
> Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/opb_arbiter_v1_02_e/.park_lock_logic(implementation) 
> 
> #
> Loading 
> Z:/simlib/EDK7.1.2_mti_se_nt/EDK_Lib/proc_common_v2_00_a/.or_bits(implementation) 
> 
> #
> ** Fatal: INTERNAL ERROR in reset_trigger_process().
> #    Time: 0 ns  Iteration: 0  Process: 
> /system/mb_opb/mb_opb/opb_arbiter_i/opb_arbiter_core_i/multi_master_gen/park_lock_i/grant_gen__1/reggrnt_gen/reggrnt_process 
> File: 
> C:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/park_lock_logic.vhd 
> 
> #
> FATAL ERROR while loading design
> # Error loading design
> 
> 

Article: 89185
Subject: Re: ISE 64bit question
From: aholtzma@gmail.com
Date: 7 Sep 2005 08:56:49 -0700
Links: << >>  << T >>  << A >>
Xilinx is only shipping x86-64 binaries. Don't hold your breath waiting
for an Itanic version.

cheers,
aaron


Article: 89186
Subject: Re: ISE 64bit question
From: Hiding in Plain Sight <hidinginplainsight@earthlink.net>
Date: Wed, 07 Sep 2005 11:58:19 -0400
Links: << >>  << T >>  << A >>
On Wed, 07 Sep 2005 10:26:23 -0400, Matthew Plante wrote:

> XST 7.1i says that it has support for redhat linux enterprise 64 bit 
> edition.  I installed enterprise 3 on a system we have, which is a quad 
> Itanium 2.  However, I can't get the xst binaries to execute.  Apparently 
> the binaries provided only work on AMD cpus?  Is there an Intel 64bit 
> version available??
> 
> xilsetup: ELF 64-bit LSB executable, AMD x86-64, version 1 (SYSV), for 
> GNU/Linux 2.4.0, dynamically linked (uses shared libs), not stripped
> 
> /sbin/init: ELF 64-bit LSB executable, IA-64, version 1 (SYSV), for 
> GNU/Linux 2.4.0, dynamically linked (uses shared libs), stripped
> 
> ./xilsetup
> bash: ./xilsetup: cannot execute binary file
> 
> Thanks,

Doubtful that there is any support for Itanics. The 64 bit version of
Xilinx is for the AMD64. You need an Athlon 64 or Opteron system. Also
unless you are running out of memory on the 32 bit version of the Xilinx
tools it's doubtful that you'll see any improvement using 64 bit binaries.
I haven't tried the 64 bit version of the Xilinx tools so I can't say for
sure but the 64 bit version of NCVerilog is 40% slower then the 32 bit
version which is exactly what you would expect on code that uses large
integer data structures. By compiling for 64 bit you double the size of
all of your integers and pointers, which translates into a 50% reduction
in effective memory bandwidth. 

Article: 89187
Subject: Re: PPC405 32 bit aligned accesses
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 7 Sep 2005 09:09:16 -0700
Links: << >>  << T >>  << A >>
Hi Ulises, Peter,
Thanks guys for an interesting discussion! Comments below...

"I. Ulises Hernandez" <delete@e-vhdl.com> wrote in message
news:dfm5ei$6sq$1@nwrdmz01.dmz.ncs.ea.ibs-infra.bt.com...
> ...I'm still waiting for the softies to come back, in the meantime I have
> modified my DDR2 controller, actually the PLB side of it (I didn't want to
> change the controller itself for this mess) such that when it detects a
> byte/16-bit word write it performs a read-modify-write access. It works!
>
Hey, good job!! Sounds like something Xilinx might wanna add to their RAM
controllers in EDK! ;-)

> >>It's possible to make the
> >> BlockRAMs work uncached and with byte access, even though the external
> >> SDRAM
> >> is cached.
>
> The answer is yes, I have had our system using uncached BlockRAM and
cached
> SDRAM, no problem. Although as Peter said you would have to modify all
Linux
> device drivers and to me sounds painful (I insist, I'm not a software
> guy...yet)
>
> Regarding the soldering iron :O), in our design the Byte Data Mask signals
> are going to be toggling @ 200 MHz times two because its DDR nature, 400
> MHz... a wee bit too fast for a normal soldering jobby ;)
>
It's also a little tricky getting the iron underneath the BGA package!
(Although there are companies that can remove the BGA, add enamelled wires
to the pads you need, and replace the BGA.)

So, me and one of the guys were talking about this last night. He reckons
that MIPS processors only ever do 32 bit accesses, i.e. no byte mask signals
come out of the device.  How does Linux run on a MIPS processor? Does it do
read-modify-write, or does the software guy define all bytes as 32 bit words
in the compiler?

Cheers, Syms.



Article: 89188
Subject: chipscope/core implementation
From: Gardovan@web-dot-de.no-spam.invalid (Gardovan)
Date: Wed, 07 Sep 2005 11:16:20 -0500
Links: << >>  << T >>  << A >>
Hi, 
I'm experimenting lately with an Virtex2Pro Eval Board and with
chipscope. 
But I'm occuring some basic problems. The Main Problem is that I don't
know exactly how to implement a generated core manually into my
design.
Ok the Core inserter is one possibility to implement some of the
Cores. 
But what if I want to implement a VIO core?
Not possible with the core inserter and the VHDL example generated is
fine but not very helpful... 
If anybody can offer me some example Files I'd be very happy. 
Thx guys.


Article: 89189
Subject: re:chipscope and V2P problems
From: Gardovan@web-dot-de.no-spam.invalid (Gardovan)
Date: Wed, 07 Sep 2005 11:16:20 -0500
Links: << >>  << T >>  << A >>
In my opinion that sounds like a trigger assignment problem.
Do you have a clue if your DCM works fine etc.?
Try to trigger your chipscope process with the clock signal you input
into your DCM and then watch the DCM output. 
At least you should get some response. 

I hope I didn't missunderstand your problem.


Article: 89190
Subject: Re: Cyclone conf flash - 25p10 !
From: "Luis Cupido" <cupidoREMOVE@REMOVEua.pt>
Date: Wed, 7 Sep 2005 17:22:13 +0100
Links: << >>  << T >>  << A >>
Correct.

Only Quartus II refuses to program them, but you can load them
with external prog software.

lc.


<jai.dhar@gmail.com> wrote in message 
news:1126099709.061349.86050@f14g2000cwb.googlegroups.com...
> ST Micro's flash devices can be used instead since they are drop in
> replacements, correct? They are much cheaper.
> 



Article: 89191
Subject: Re: Fastest input IOB on a Spartan-3?
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 7 Sep 2005 09:25:20 -0700
Links: << >>  << T >>  << A >>
Paul,
Probably one of the differential inputs that can feed directly to a DCM. The
DCM inputs have a pre-divide-by-two feature. You should be aware that Xilinx
FPGAs have quite a large input capacitance (~12pF for Virtex II-Pro IIRC)
that you should take into account when trying to match your line to the pin,
especially at the high frequencies you're talking about.
You've considered an external prescaler?
HTH, Syms.
"Paul Boven" <p.boven@chello.nl> wrote in message
news:1125918116.537765@blaat.sara.nl...
> Hi everyone,
>
> I'd like to know which input pin/IOB of the Spartan-3 would be able to
> toggle (divide by 2) the highest frequency input signal. From earlier
> postings by Peter Alfke I understand that not all IOBs are created equal
> in this respect, although I don't know how big the differences between
> individual IOBs would be. I'm building a frequency counter, and the
> higher the input it can handle, the better. What would be the highest
> frequency input signal? And which IO-standard to use for highest
> performance? Ultimately I will need to design an input
> amplifier/discriminator, so input IO-standard is not fixed yet.
>
> Regards, Paul Boven.



Article: 89192
Subject: Re: Fastest input IOB on a Spartan-3?
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 07 Sep 2005 10:27:02 -0700
Links: << >>  << T >>  << A >>
All,

The LVDS input is 5 pF + 100 ohms.  Differential input is really two 
10pF in series.

So, for highest speed, the differential input is the best.

Austin

Symon wrote:

> Paul,
> Probably one of the differential inputs that can feed directly to a DCM. The
> DCM inputs have a pre-divide-by-two feature. You should be aware that Xilinx
> FPGAs have quite a large input capacitance (~12pF for Virtex II-Pro IIRC)
> that you should take into account when trying to match your line to the pin,
> especially at the high frequencies you're talking about.
> You've considered an external prescaler?
> HTH, Syms.
> "Paul Boven" <p.boven@chello.nl> wrote in message
> news:1125918116.537765@blaat.sara.nl...
> 
>>Hi everyone,
>>
>>I'd like to know which input pin/IOB of the Spartan-3 would be able to
>>toggle (divide by 2) the highest frequency input signal. From earlier
>>postings by Peter Alfke I understand that not all IOBs are created equal
>>in this respect, although I don't know how big the differences between
>>individual IOBs would be. I'm building a frequency counter, and the
>>higher the input it can handle, the better. What would be the highest
>>frequency input signal? And which IO-standard to use for highest
>>performance? Ultimately I will need to design an input
>>amplifier/discriminator, so input IO-standard is not fixed yet.
>>
>>Regards, Paul Boven.
> 
> 
> 

Article: 89193
Subject: Re: Spartan-3E Starter Kit availability slips to December
From: "jcarr@linuxmachines.com" <jcarr@linuxmachines.com>
Date: 7 Sep 2005 10:51:57 -0700
Links: << >>  << T >>  << A >>
> If I was about to start an FPGA design-in I think I'd be
> seriously looking at Altera right now....

If you use linux, then you will probably avoid using windows. Can you
even do Altera development using Linux? Lots of developers using FPGA's
are hobbiests and enthusiasts. Usually that == linux users. Xilinx's
Linux support is excellent.

That being said, I will admit that although I managed build the
xilinux_pp driver under 2.6.11&13, I can't seem to get the Webpack
version of iMPACT to use it. So, I'm stuck trying to take the Xilinux
created SVF file and use it to program the XCR02S on the S3BOARD via
jtag. It is a shame that Xilinx went so far, did so much great work to
make the webpack run under linux and then didn't spend the
(comparatively small) extra effort to make the xilinx_pp driver work. I
was going to start adding debugging the kernel driver to see what
Webpack was trying to do but haven't had time yet.

OT: I'll go on for what it's worth here is my attempt to use the driver
-- I'm guessing I'm not making the correct /dev/ entries for iMPACT.
Maybe someone else knows if this is possible?

Jeff

root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# make
make -C /lib/modules/2.6.11-1-686-smp/build
SUBDIRS=/home/gpl_xilinx_driver/xilinx_pp modules
make[1]: Entering directory `/usr/src/kernel-headers-2.6.11-1-686-smp'
  CC [M]  /home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.o
  Building modules, stage 2.
  MODPOST
*** Warning: "cleanup_module"
[/home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.ko] undefined!
*** Warning: "init_module"
[/home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.ko] undefined!
*** Warning: "cleanup_module"
[/home/gpl_xilinx_driver/xilinx_pp/windrvr6.ko] undefined!
*** Warning: "init_module"
[/home/gpl_xilinx_driver/xilinx_pp/windrvr6.ko] undefined!
  LD [M]  /home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.ko
make[1]: Leaving directory `/usr/src/kernel-headers-2.6.11-1-686-smp'
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# rmmod xilinx_pp
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# insmod ./xilinx_pp.ko
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# dmesg |tail -n 2
xilinx_pp: major 244
xilinx_pp: Xilinx parallel port driver 1.0a for kernel 2.6
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# grep device /proc/devices
Character devices:
Block devices:
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# grep xil /proc/devices
244 xilinx_pp
root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# (run ise; impact --
impact searches for a cable, doesn't find it)


Article: 89194
Subject: ISE7.1 SP4: proble and chipscope problem
From: "Tim Verstraete" <tim.verstraete@barco.com>
Date: Wed, 07 Sep 2005 18:03:47 GMT
Links: << >>  << T >>  << A >>
Hey,

Do some of you also have a problem with adding probes in fpga editor and
then generating the bit file? i have the same problem sometimes with
chipscope (especially when i assigned the wrong one and then change it back
to the right one and then generate the bit file) .... when i generate the
bit file in those 2 situations the fpga editor just closes and crashes ...

i was just wondering if i am the only one + if someone knows a solution to
this problem?

thanks in advance,

Y



Article: 89195
Subject: Re: Spartan-3E Starter Kit availability slips to December
From: Mike Treseler <mike_treseler@comcast.net>
Date: Wed, 07 Sep 2005 11:04:09 -0700
Links: << >>  << T >>  << A >>
jcarr@linuxmachines.com wrote:
>>If I was about to start an FPGA design-in I think I'd be
>>seriously looking at Altera right now....
> 
> If you use linux, then you will probably avoid using windows. Can you
> even do Altera development using Linux? 

Yes. Red Hat Linux 7.3, 8.0, and Enterprise 3.0 WS


       -- Mike Treseler

Article: 89196
Subject: RocketIO code example
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Wed, 07 Sep 2005 19:03:19 GMT
Links: << >>  << T >>  << A >>
I'm just starting out using RIO on VII Pro devices and I need some simple 
VHDL to get started. There are some code snippets in the RIO UG but I don't 
think it's complete by any means. I just need something that generates some 
data (probably with the Aurora primitive) so that I can test the hardware 
it's running on and see what's required to be implemented in user code e.g. 
SOP, EOP delimiter insertion, comma handling etc.

If anyone has anything that could be of use, I'd be grateful.

TIA,

Rog. 



Article: 89197
Subject: Re: Cyclone conf flash - 25p10 !
From: Jim Granville <no.spam@designtools.co.nz>
Date: Thu, 08 Sep 2005 07:15:51 +1200
Links: << >>  << T >>  << A >>
Luis Cupido wrote:

> Hi,
> 
> 
>>Then SOMETHING must be different ?
> 
> 
> Right :)
> ... but only Quartus II knows how to check that
> 
> One hypothesis is that the EPCS devices come from altera
> with something on memory to tell that they are from altera.
> and Quartus II also writes something to keep this
> thread going. Would that be the trick ?

  You could test that idea, by using your other SW to read back 100%
from a Altera tagged one, and copy that into the ST one, then see if
Quartus can still spot the difference... ?
-jg


Article: 89198
Subject: Re: Help finding Signetics Datasheets
From: "logjam" <grant@cmosxray.com>
Date: 7 Sep 2005 13:03:33 -0700
Links: << >>  << T >>  << A >>
I wanted to add some closure to this post.  A member of
comp.arch.apple2 in europe scanned the 3 datasheets from his databook
and posted them the same day.  Thanks everyone!

You can find them here:  http://www.hansotten.com/index 6502.html

Just making sure someone can find the documents when they find this
post in a google search.  ;)


Article: 89199
Subject: Re: Spartan-3E Starter Kit availability slips to December
From: Duane Clark <dclark@junkmail.com>
Date: Wed, 07 Sep 2005 20:12:53 GMT
Links: << >>  << T >>  << A >>
jcarr@linuxmachines.com wrote:
> 
> OT: I'll go on for what it's worth here is my attempt to use the driver
> -- I'm guessing I'm not making the correct /dev/ entries for iMPACT.
> Maybe someone else knows if this is possible?
> 
> Jeff
> 
> root@jcarr:/home/gpl_xilinx_driver/xilinx_pp# make
> make -C /lib/modules/2.6.11-1-686-smp/build
> SUBDIRS=/home/gpl_xilinx_driver/xilinx_pp modules
> make[1]: Entering directory `/usr/src/kernel-headers-2.6.11-1-686-smp'
>   CC [M]  /home/gpl_xilinx_driver/xilinx_pp/xilinx_pp.o
>   Building modules, stage 2.
>   MODPOST
> ...

I have no idea whether it works on a 2.6 kernel. But I notice you didn't 
mention installing the windrvr6 and xpc4drvr drivers. I believe these 
are needed before loading the xilinx_pp driver (at least that is what I 
do). In my 2.4 kernel, I have in /etc/rc.d/rc.local:

source /lib/modules/misc/install_windrvr6 windrvr6
source /lib/modules/misc/install_xpc4drvr




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