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CMOS wrote: > if i do that there will be an output ( out put of the input Buffer ) > without any connections. ( the IO buffer im talking about is made up of > one OBUF and one IBUF.). > is there a way to post images in this forum, so that i can post the > diagram? > CMOS Then you've found the problem. If you're using one pad for a bidirectional signal, don't use two primitives. Use the *one* IOBUF primitive which has four ports: .I, .O, .T, and .IO. That's what the tools are designed to do. If you wanted to use a primitive to instantiate a flip-flop, you wouldn't get the same results if you instantiated a master latch and a slave latch because (even though a register is a combination of those two) the tool understands the FF as a single element. The tool understands a bidirectional pad as a single element.Article: 90751
Just a few extra answers to the answers... Austin -snip- Martin Thompson wrote: > Well, we are an autmotive only company now, so I have no direct > Aero/Defense links most of the time, but we always get to the right > people when we have questions to ask :-) OK. Didn't know that. Congratulations. And for autos, we are VERY serious about SEUs, as we understand that no one wants their anti-lock brake system, or their collision avoidance system to suddenly freeze up! This is a good reason to check on the Spartan 3E, which has added features, as well as being even more than twice as "hard" as the Spartan 3 (more things were done to improve its already good SEU hardness). It will take another six months to tell just how good 3E is, but it is being assembled now. -snip- > OK, that's good to hear. Presumably the DFF rate is what I need to > compare with an ASIC (as they don;t have configuration latches)? True, they have no configuration memory. But they do have SRAM blocks, and these can be very bad. Fro a foundry report, for a standard cell SRAM block, they listed 5,000 FIT/Mb as the failure rate. Compare that to ours V4 rate (below) for our BRAM. In a 90nm ASIC, the DFF is a standard cell: the smallest, fastest possible, with practically no loading. Now we also use standard cell ASIC synthesis for blocks of IP on our chip, so we also know its SEU hardness. From a 90nm standard cell library, a M/S D FF was chosen: Qcrit = 6.3 fc Area affected is different (different layout) FIT/Mb = 191 598 years between upsets (for 1 million) Compare that with our DFF, and our DFF is 191 times BETTER (less likely to upset). Seriously, you MUST ask your ASIC vendor to justify their attitude that "they do not have a problem" as they most obviously DO have a problem! After all, we KNOW, as we, too, use standard cells, and we are forced to do things to our blocks to minimize the effects of neutron strikes. For example, we TMR some critical logic that is standard cell based. Right now, their (ASIC and ASSP vendors) attitude is to do nothing at all (because they are "better", which of course, they are no longer). -snip- >>We also are recording the upset rate in the BRAM. >> > > That'll be interesting! Yes, it is. 22 FIT/Mb, or 16 times better than 0.15u. Probably the most dramatic improvement in Virtex 4. Compared to a 90nm ASIC 5,000 FIT/Mb, I seriously suggest you have no choice but to use our FPGAs. Don't have a number for Spartan 3, or 3E BRAM, yet. Too few BRAM bits in those parts, so it takes forever to get any statistically significant data. We do have LANSCE beam test results, so we know we are better than we were in 0.15u, we just don't know by how much yet like we do for Virtex 4. By the way, all data (in these postings) is the mean for the 95% confidence level. The variation is +/- 20% based on all of the error factors (we and others have discovered). The list of error factors is quite long, but we have worked hard to get this as accurate as we possibly can. -snip > Our application is automotive, therefore will be something like > Spartan-3E. We will have to use cleverness to avoid spending too much > extra money on silicon - I don't think we can TMR the whole lot... > we'll be speaking to your experts! Talk with your FAE. TMR ONLY the critical element(s). The XTMR tool allows you to pick and choose your level of TMR (there are options for IO, voting, etc. that you may choose to use that apply to your application), and by block, which ones get TMR'd. The tool may have been developed for the aerospace/military market, but as any auto engineer knows, under the hood of a car is a far more hostile environment than a satellite in earth orbit, or on a battlefield (unless you are under the hood of a car on a battlefield).Article: 90752
Hi,
I'm a Phd student using EDK (7.1i) in order to prototype a multiple processor system in a single chip.
I have made a design with 16 microblazes editing the ".mhs" file. Each processor can communicate with 4 other processors using point to point with DMA connections.
I used the fast implementation flow with default options in the "fast_runtime.opt" file.
The design seems to fit easily in a xc4vlx200 but I get the following output from the par tool:
Starting Router Phase 1: 273083 unrouted; REAL time: 42 mins 50 secs
[...]
IMPORTANT MSG: UNROUTABLE DESIGN; CHANGE PLACEMENT or EASE CONSTRAINTS
Phase 4: 94054 unrouted;
[...]
34035 signals are not completely routed.
For more info about the design size Here is the output from map tool:
Design Summary:
Number of errors: 0 Number of warnings: 158 Logic Utilization: Total Number
Slice Registers: 31,944 out of 126,336 25% Number used as Flip Flops:
29,896 Number used as Latches: 2,048 Number of 4 input LUTs: 48,510 out
of 126,336 38% Logic Distribution: Number of occupied Slices: 36,209 out
of 63,168 57% Number of Slices containing only related logic: 36,209 out
of 36,209 100% Number of Slices containing unrelated logic: 0 out of 36,209
0% Total Number 4 input LUTs: 56,322 out of 126,336 44% Number used as
logic: 48,510 Number used as a route-thru: 465 Number used for Dual Port
RAMs: 4,096 (Two LUTs used per Dual Port RAM) Number used as 16x1 RAMs:
2,048 Number used as Shift registers: 1,203 Number of bonded IOBs: 4 out
of 768 1% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs:
1 Number used as BUFGCTRLs: 0 Number of FIFO16/RAMB16s: 128 out of 552
23% Number used as FIFO16s: 0 Number used as RAMB16s: 128 Number of DSP48s:
48 out of 192 25%
What are the possible ways to help the par tool find a sucessful placement/route?
Since I want to test a lot of different hardware configurations, I would prefer to implement my designs in a fully automated way.
Thanks for your help.
Regards, Lionel Damez.
Article: 90753If you are looking for low power static, you can't beat the XP or XO families from Lattice. They have a power down pin that reduces the power to ~ 100 micro amps. Of course the I/O tristate and such, but since these devices are flash + sram, the part boots up in less than a mili second. If Dynamic power is important and you can fit into a cpld, look at the CR2 or Mach 4000Z.Article: 90754
I got the answer. My counter not utilizing carry chain. and was using extra buffers , thats why delay was more.Now i think simple modules like counters,adders are better to infer then using them we can make a structural design.Article: 90755
Hello, I used the new version of Synplify (8.2.1) and the problem has dissapeared. It seems that there was a bug retiming option for Virtex4. Now with the new version it has been corrected and all works fine. Regards Javier Castillo On Wed, 12 Oct 2005 21:29:02 +0200, Javier Castillo <jcastillo@opensocdesign.com> wrote: >Hello, > > I have a design in a Virtex2 that uses RAMB16 primitives. In this >design I access to this memory to write and read the same address at >the same time. This gives a collision but over the board it has the >expected result, it means, it write the data and put in the output the >new data. >Porting this design to a Virtex4 I found that the behaviour of the >RAMB16 is different and the design doesnt work. I go around this >problem adding some logic to avoid collisions in the memory. But my >question is, is there any difference between RAMB16 primitive in >Virtex2 and Virtex4? > >Regards > >JavierArticle: 90756
Read 'Designing a Custom Processor Peripheral Using Xilinx EDK' - Part 3 and Part 4 available on the Xilinx website under techxclusives. You'll get what you need.Article: 90757
Event-based simulation allows you to have very fine resolutions. Just make sure that all your signals crossing clock domains are flopped and that there are no Clock-to-Q delays involved in your model. I have run the fast FIFO models in ModelSim PE 6.1a and Veritak 1.75A and they have indentical behavior to the Xilinx models.Article: 90758
langwadt@ieee.org wrote: > Tim Wescott skrev: > > >>Pramod Subramanyan wrote: >> > > snip > >>>http://www2.ele.ufes.br/~ailson/digital2/cld/chapter5/chapter05.doc5.html >>> >> >>Interesting. So that's what they actually do in practice, just copy a >>page out of a textbook? Wouldn't the stages of adders really cause a >>speed hit? To have your signal ripple through so many stages would >>require you to slow your clock way down from what it could be otherwise > > > afair the delay for the straight forward N*N bit parallel multiplier is > > only around double the delay of a N bit adder, i.e. the longest path in > the multiplier is lsb to msb plus top to bottom > > >>-- it seems an odd way to build a chip who's purpose in life is to be >>really fast while doing a MAC. > > > I think its more likely that they look at different options and find > the > smallest that is fast enough ;) > > have a look at http://www.andraka.com/multipli.htm > > > snip > > >>Yet DSP chips cost tons of money, which disappoints Jeorg who designs >>for high-volume customers who are _very_ price sensitive. The question >>was more a hypothetical "what would Atmel do if Atmel wanted to compete >>with the dsPIC" than "should I have a custom chip designed for my >>10-a-year production cycle". > > > I'm not sure the size of the multiplier makes a big difference, my > guess > is that if you look at the die you would see that most of it is memory > > > what price are you looking for?, how much memory?, how fast? > > Not that I will build you one, but I'm curious :) > > -Lasse > The original question was for an under-$2 DSP chip capable of doing audio frequency stuff, including FFTs. I'm not the fellow who asked; it just sparked a tangential thought in my head about why there isn't some intermediate step on the way to a full-speed DSP. So I couldn't tell you exactly how much speed and memory, given I don't know how often he was considering doing the FFTs, or how many points, etc. Hey Jeorg! You listening? What did you need to do, exactly? -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 90759
Has anyone had any luck programming the Spartan-3 Starter board RS-232 using C? I am trying to send/receive/monitor all data going over COM1 ThanksArticle: 90760
Jim, If I'm not mistaken, the datasheet of the 4000Z provides both static power, and a graph showing the dynamic power requirements. There is even a complete technical note about the power coefficients. On the FPGA side, the Power Calculator can be used for static power, and gives a very good idea of the requirements when a design is loaded. Unfortunately this is only true if a full timing simulation is done and the test vectors are fed back to the power calculator. If you don't simulate, then you need to give an activity factor. Luc On Thu, 20 Oct 2005 07:58:05 +1300, Jim Granville <no.spam@designtools.co.nz> wrote: >himassk wrote: >> I could nt make out the best low power FPGA among the Spartan3, Cyclone >> II and Lattice FPGAs. >> >> Regards, >> Himassk > > You need to work it out for your application: >using the vendors mA(Static) and mA/MHz numbers, and also determine if >Typical, or Worst case matters most to you. > Actual measurements will probably be needed as reality checks. > > Not all these numbers are clearly documented, and with everyone >claiming to be lowest power, your task will not be easy. > > In particular, Look for what they do NOT say. > >example: I see lattice make big claims for 4000Z static Icc over >coolrunner 2, but are very quiet on mA/MHz. > Perhaps that number does not stack up as well ? > >-jg > >Article: 90761
Hello I want to do a little EDK design that uses the embeded Tri-mode Ethernet MAC (TEMAC) of the Virtex4 FX parts. EDK offers several options for Ethernet MAC type but they are all soft MACs. The embedded MAC is a major selling point for me because of the logic saved and because compiling the soft MACs takes a long time. I will be connecting to a 10/100 switch using the MII port. Is there a convenient way to incorporate the embedded MAC into an EDK project? Thank you for any suggestions. Pete DudleyArticle: 90762
Lionel Damez wrote:
> The design seems to fit easily in a xc4vlx200
Looks like the logic fits but the wires don't.
> Number used as Latches: 2,048
I wouldn't expect any latches.
> What are the possible ways to help the par tool find a sucessful placement/route?
Try a simpler case first. Maybe four microblazes?
-- Mike Treseler
Article: 90763luc wrote: > Jim, > > If I'm not mistaken, the datasheet of the 4000Z provides both static > power, and a graph showing the dynamic power requirements. > There is even a complete technical note about the power coefficients. Yes, but I was refering to the Web hoopla, [ There are NO relative claims in the Data sheets ] see http://www.latticesemi.com/products/cpldspld/ispmach4000z.cfm and not a squeak on mA/MHz ? [Aug-27-04 is also getting a tad long in the tooth ? ] ISTR a quick compare did confirm that mA/MHz number was not so great.... -jgArticle: 90764
Raul, this may just reveal my ignornce, but anyhow: How do you model metastability, which needs sub-femtosecond resolution? How do you model that an asynchronous FIFO generates its EMPTY flag in time, even under the most adverse timing conditions between the two incoming clocks? Those have been things that kept me awake at night :-( Peter AlfkeArticle: 90765
I've got to say so far I have been extremely unhappy with Avnet's level of Technical Support. I purchased their Virtex-4 Evaluation Board and have not yet been able to get the most simplistic communication to the board to work. To be more in line with their supports knowledge base I migrated over to Window's as they told me they could not help me when I was running Xilinx software on Linux. Now that I am running on Window's XP I am experiencing the same issues and they are simply not responding to my emails. If basic support is what you are looking for, don't purchase an Avnet Board they don't provide it!Article: 90766
Is this the ML403 board?Article: 90767
Hi all, I have a FIR filter which I would like to make a RPM of to see what all the fuss is about. But I don't know the appropriate approach. I understand that I can get a RPM from the Floorplaner, but then I guess I have to place the logic by hand my self. Is there a way to write it in VHDL? Do anybody have a "how-to.." reference design to share? All the best, RickArticle: 90768
No, this is Avnet's Virtex-4 Evaluation Board. Not sure if it has a corresponding reference rumber. It does have Xilinx PROM and Xilinx's Virtex-4 on the board. The ML403 is Xilinx's own Development Board ChrisArticle: 90769
Peter Alfke wrote: > Newer FPGAs have lots of fast 18 x 18 multipliers. > The humble XC4VSX25 has, among other goodies, 128 such multipliers > running at max 500MHz single-cycle rate. > The mid-range SX35 has 192, and the top SX55 has 512 such fast 18 x 18 > multipliers each with its associated 48-bit accumulator structure. We > invite you to keep that kind of arithmetic performance busy... No > wonder these FPGAs can outperform sophisticated and expensive DSP > chips. Well, the original question was about $2 DSP's, presumably for low cost products. So are there any FPGA's currently available for $2 or less which include any built-in single-cycle 18 x 18 multipliers, plus enough logic cells to replace the rest of the functionality of a single low cost DSP? Thanks. -- rhn A.T nicholson d.O.t C-o-MArticle: 90770
What is the problem with the board? Maybe we can help. I guess it is the 'Virtex-4 FX12 Evaluation Board' with the OLED. KunalArticle: 90771
Hi, I am trying to synthesize hardware which changes one values in a register array at rising and falling edge of the clock. Basically I am trying to synchronize different actions on different edges of the clock and write, for example, signal1 to reg(1)(31 downto 0) and signal2 to reg(2)(31 downto 0). The line with *** gives an error. if reset='1' then -- initialization of reg ***elsif rising_edge(clock) and (write_flag = '1') then reg(CONV_INTEGER(unsigned(reg_address1))) <= signal1; elsif falling_edge(clk) and (write_flag = '1') then reg(CONV_INTEGER(unsigned(reg_address2))) <= signal2; end if; QUARTUS II 5.0 gives me the following error during compilation: "Cannot synthesize logic for reg because its value changes on both rising and falling clock edges". What should I do? If it's possible, I would like to keep rising and falling edge clocking. Thank youArticle: 90772
I think the problem happens due to to the same register being clocked
by different events - that's what the compiler does not like.
What would you suggest ?
I think maybe to have another process which sets RISING_FLAG to 1 at
rising edge and FALLING_FLAG to 1 at falling edge. Then make my other
process sensitive to the flags instead of clock.
process(clock, reset)
begin
if reset = '1' then
--reset flags
elsif rising_edge(clock) then
RISING_FLAG <= '1';
else
RISING_FLAG <= '0';
end if;
end process;
-- SeCOND PROCESS that changes FALLING_FLAG in the similar way.
I am not sure if it'll work and be stable.. because not sure how long
the flag will stay at one and will it be enough to trigger the main
process.
Article: 90773bobrics wrote: > Hi, > > I am trying to synthesize hardware which changes one values in a > register array at rising and falling edge of the clock. Basically I am > trying to synchronize different actions on different edges of the clock > and write, for example, signal1 to reg(1)(31 downto 0) and signal2 to > reg(2)(31 downto 0). The line with *** gives an error. > > if reset='1' then > -- initialization of reg > ***elsif rising_edge(clock) and (write_flag = '1') then > reg(CONV_INTEGER(unsigned(reg_address1))) <= signal1; > elsif falling_edge(clk) and (write_flag = '1') then > reg(CONV_INTEGER(unsigned(reg_address2))) <= signal2; > end if; > > QUARTUS II 5.0 gives me the following error during compilation: "Cannot > synthesize logic for reg because its value changes on both rising and > falling clock edges". > > What should I do? > If it's possible, I would like to keep rising and falling edge > clocking. The FPGA (and most of the world) doesn't have flip flops that clock on both edges, so what hardware do you expect the synthesizer to map to? You should not use a synthesis tool if you don't understand what the hardware will look like. Anyway, one possible fix would be to generate a double-rate clock with a PLL (Are you using Stratix?). Then you can clock everything on rising edge but use enables on alternating clocks to act like your code. Oh, you also have a typo - you have rising_edge(clock) but falling_edge(clk), so it thinks you have two different clocks. DavidArticle: 90774
unfrostedpoptart wrote: > bobrics wrote: >> Hi, >> >> I am trying to synthesize hardware which changes one values in a >> register array at rising and falling edge of the clock. Basically I am >> trying to synchronize different actions on different edges of the clock >> and write, for example, signal1 to reg(1)(31 downto 0) and signal2 to >> reg(2)(31 downto 0). The line with *** gives an error. >> >> if reset='1' then >> -- initialization of reg >> ***elsif rising_edge(clock) and (write_flag = '1') then >> reg(CONV_INTEGER(unsigned(reg_address1))) <= signal1; >> elsif falling_edge(clk) and (write_flag = '1') then >> reg(CONV_INTEGER(unsigned(reg_address2))) <= signal2; >> end if; >> >> QUARTUS II 5.0 gives me the following error during compilation: "Cannot >> synthesize logic for reg because its value changes on both rising and >> falling clock edges". >> >> What should I do? >> If it's possible, I would like to keep rising and falling edge >> clocking. > > The FPGA (and most of the world) doesn't have flip flops that clock on > both edges, so what hardware do you expect the synthesizer to map to? > You should not use a synthesis tool if you don't understand what the > hardware will look like. > > Anyway, one possible fix would be to generate a double-rate clock with > a PLL (Are you using Stratix?). Then you can clock everything on > rising edge but use enables on alternating clocks to act like your > code. Oh, you also have a typo - you have rising_edge(clock) but > falling_edge(clk), so it thinks you have two different clocks. > > David You could try using a DDR type register, if available in your target device. Not sure if they can be inferred or whether they'd have to be explicitly instanced. I'd say most probably the latter... That does sound like what you're after, though I'm not sure how the synthesis would handle to two different signal assignments to it, I guess it could use multiplexers though I wonder about setup and/or hold timings in this situation.
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