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Hello,
I am looking for some help with a particularily nasty problem I have
run into,
Out of our 10 prototype Virtex-4-FX20 (CES2 stepping) boards, roughly
half are exhibiting an issue with the PPC405 starting up out of reset.
After powerup, the bit file is loaded, done goes high, current load
kicks in, but the PPC never boots. Other logic on the chip is running.
When the device boots properly, there are no issues booting from BRAM,
loading DDR-DRAM from flash, or executing from DRAM. Everthing is
working good.
Using chipscope, I can see the data from address 0xfffffffc being
returned on the PPC405 PLB-I-Master side of the PLB arbiter correctly.
However, the second address put out is garbage (0x100600), resulting in
a bus error. The boot code is held in a BRAM off of the PLB. During a
successful boot, the second address is 0xffffc000 which is correct.
The reset sequence and first PLB bus cycle look identical in both the
failing/non-failing cases.
Observations:
* Freeze spray (now known around here as 'FPGA programming spray') will
without exception make this problem go away. (suggests a timing /
power issue??)
* Warm resets (through the EDK reset controller) have no effect. The
only way to make this problem go away is to reload the device.
* Reloading the device does not always work. Some boards will always
boot fine on the second try, while others will only boot once cooled.
* The emulator (tried both XMD and Greenhills probe) cannot talk to the
processor when it is in this state.
* Clocks, DCM locks, reset signals, debug/jtag signals, all look
normal.
* The PPC is in an unrecoverable state which is a little disturbing
regardless of how it got there.
What else have I tried (none of these have made a difference):
* clocking the PPC405 slower. Same clock as the PLB.
* JTAG loading -vs- selectmap loading
* Boot from the OCM bus instead of the PLB.
* Removed all other logic from the design except the PPC and an OCM
BRAM
* Looked closely at the power supplies / grounding.
* I have already successfully played 'Stump the Xilinx FAE/factory'.
* Spent hours in Timing Analyzer looking at any unconstrained nets.
* Looked closely at errata
What angles still left to explore
* I am 95% convinced this is either the result of an external
condition, or a chip defect.
* So, I am working up a power-supply change to delay VCCO from VCCINT.
I don't believe that is it, but I am running out of things to try.
...................
Has anyone ever seen an issue like this (V4, or 2VPro)? I have done
many FPGA designs over the years (although this is our first PPC-based
design) and have rarely been this stumped.....
Any and all advice is welcome. Email me or post here.
Thanks,
Chris
'<*{{{><
Article: 89976Which tools form vendor M ?? Does Pads have that feature?Article: 89977
I have a project EDK system.xmp in ISE. ISE does not initialize the bitstream even if I do a update bitstream in ISE. I had to import ISE to EDK and do update bitstream so that it works on my FPGA board. Looks like EDK does it correctly and not ISE. I also tried to use my project in ISE with an export to ProjNav with the EDK tool. Same thing I had to import my ISE project to EDK to initialize it correctly. I also tried to put my .elf and .bmm file in ISE. But does not change anything. I use ISE 7.1.04i and EDK 7.1.02i I found my answer to initialize my bitstream at: Exporting a EDK design to Project Navigator http://groups.google.ca/group/comp.arch.fpga/browse_frm/thread/c9dfcb22ff57862/fc5ff8c6327f16a2?lnk=st&q=export+edk&rnum=12#fc5ff8c6327f16a2 It is important that i use my EDK project in my ISE project and not the other way around. Why does ISE do not initialize the memory of the BRAM or bitstream? Francis St-Pierre École Polytechnique de Montréal http://www.grm.polymtl.ca/~stpierre/ Key Words: EDK in ISE, ISE with EDK, system.xmp in ISE project, unintiliazed .bitArticle: 89978
When I try to use more than one embedded system in ISE, it says: Only one source of type 'XPS FILE' is allowed in a project. Why can't I add more than one system.xmp file to ISE? I need two embedded systems because the hardware and software in each one are different. And I can not put the two EDK projects in only one because my VHDL Top Level in ISE will instantiate the first EDK project only once and the other several times. I want to create a multiembedded design. ISE should be able to have several embedded systems; that is not normal! I also tried to add a EDK project system.xmp in a ISE project created(export to ProjNav) with another EDK project. But it can not work because the two EDK project have "system" for name as sub-module. I try to put "system_something" as sub-module name, but EDK always export it as "system" name. How to have multiple EDK projects in ISE? Francis St-Pierre École Polytechnique de Montréal http://www.grm.polymtl.ca/~stpierre/Article: 89979
troy.scott@latticesemi.com wrote: > Gabor, > > I've been able to the GUI environments for ISE, ispLEVER, and Quartus > with no modifications under Win2000. However, if you run your program > executables from the command line, you will need to manage the > enviroment variables for ISE and ispLEVER since the tools use similar > executable names (NGDBuild, MAP, PAR, etc.). > > I've also found conflicts between the Actel and Lattice-Editions of > Synplify which are provided with the free "starter" tools. > > Best Regards, > Troy Scott > Lattice Semiconductor TME Thanks fo the info. I have already installed ispLEVER on my machine. The conflict with Quartus was not with ISE, but the older Foundation (Aldec-based) tools. With Quartus installed I lost the ability to compile Abel modules (yeah we have some really old code here). So now I have two versions of Xilinx and ispLEVER on the same machine and haven't found any conflicts yet (at least with Xilinx tools, I haven't played with the ispLEVER very much yet). Regards, Gabor SzakacsArticle: 89980
I really like the idea of using Icarus Verilog as a Synthesis tool in our FPGA flow. I have only used it with a few small test cases. What's the largest most complex design that you have successfully synthesized using Icarus? How much of a headache was it getting the design through synthesis? How steep is the learning curve if you are accustomed to other synthesis tools? Thanks, ChrisArticle: 89981
It would be a case if delta cycle in simulator is set to the same value as clk period.Article: 89982
Hi, I am just beginner of VHDL. I want to define a 2 dimensional input variable in entity. I think the syntax is something like this: v : in std_logic_vector(2 downto 0)(11 downto 0); Please advice. Thanks!Article: 89983
Hi, Orcad has these features? You think which is better Orcad or PADS? (why)Article: 89984
Only if you are an academic institution under our University Access Program. We give one year loans under certain conditions to worth projects. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "JASH" <jaffersultan@gmail.com> wrote in message news:1128107364.497876.212970@z14g2000cwz.googlegroups.com... > Any chance of donation..... >Article: 89985
John Adair wrote: > For all the hardened FPGA addicts and please excuse the sales push. > > If anyone is interested in our lower spec Broaddown2's BD2-400, BD2-1000 > then we are having a stock clearance next week. Details will follow on our > website shortly but pricing will be GBP£160 (BD2-400) and GBP£190 > (BD2-1000) only while stock lasts. > > Our MINI-CAN boards now have an uprated spec for those intersted in these > boards. Details to follow on the website but essentially you get a > XC3S1000 now in the FPGA hole. > > John Adair > Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development > Board. > http://www.enterpoint.co.uk MINI CAN seems to be intended for CAN applications, the FAQ gives no answer about your experiences using CAN IP cores. Which one did you use? Do you offer something? -- with best regards / mit freundlichen Grüßen Heinz-Jürgen Oertel +=================================================================== Merokok dapat menyebabkan kanker, serangan jantung, impotensi dan gangguan kehamilan dan janin.Article: 89986
first you create a type.. then assign it...
type v_typ is array (2 downto 0) of std_logic_vector(11 downto
0);
signal v: v_typ
now you can access it as
v(i)(j) <= -- something
Simon
"eeh" <eehobbyist@yahoo.com.hk> wrote in message
news:1128136736.906033.205550@z14g2000cwz.googlegroups.com...
> Hi,
>
>
> I am just beginner of VHDL. I want to define a 2 dimensional input
> variable in entity. I think the syntax is something like this:
>
> v : in std_logic_vector(2 downto 0)(11 downto 0);
>
> Please advice. Thanks!
>
Article: 89987I think if you are using Protel then stick with it.. the Auto-router has always sucked but if you are half pie any good.. then it should be a breeze to do a Xilinx.. I know.. I have done a half dozen boards in the last two years .. all with BGA Xilinxs. I would even worry about the equalize net lengths.. unless you are planning on running 300 MHz+ .. but then no auto-router will work for you unless you have a stray $100k to spare.... in which case I'll do the board for $50k and in Protel :-) Simon <henrique.portela@gmail.com> wrote in message news:1128100398.148033.295530@g47g2000cwa.googlegroups.com... > Hi All, > > I am developing a board using Virtex FPGA. Right now i am using Protel, > but i am not being able to use the "Equilize net lenghts" nor the > auto-route. > I wonder if there is any software better than protel to develop pcb > boards. Does any one know which software xilinx use?? > > Tanks >Article: 89988
If you see it go high late.. then it would tend to disagree with the results
you printed on the first page.
In saying that.. if you are looking in the wrong place this is quite
possible
if you are peeking in a process.. then check the sensitivity list.. that's
the usual culprit when things don't happen when you expect.
Simon
<fastgreen2000@yahoo.com> wrote in message
news:1128090988.252193.220510@o13g2000cwo.googlegroups.com...
> Yes, I'm doing just that for creating clock, and your post shed some
> light on what I wasn't paying attention to, but...
>
> I'm still confused. In the following testbench code, shouldn't it wait
> for a certain rising edge (whatever time it might correspond to), and
> assert 'sig1', at the time reported by 'now'? What I see is 'sig1' get
> asserted one clock after that.
>
> line 1 : wait until rising_edge(clk);
> line 2 : write (L, string'("1st rising edge : " & image(now)));
> line 3 : writeline (output, L);
> line 4 : sig1 <= '1'; -- I see this signal go high at 'now' + 1
> more clock cycle??
> -- note that lines 2,3,4 are
> occuring after the rising edge.
>
Article: 89989Simon he's asking about how to use multi-dimentional arrays in port declaration. not for signal/variable declaration. Rgds, Karthik Simon Peacock wrote: > first you create a type.. then assign it... > type v_typ is array (2 downto 0) of std_logic_vector(11 downto > 0); > signal v: v_typ > > now you can access it as > v(i)(j) <= -- something > > Simon > > > > "eeh" <eehobbyist@yahoo.com.hk> wrote in message > news:1128136736.906033.205550@z14g2000cwz.googlegroups.com... > >>Hi, >> >> >>I am just beginner of VHDL. I want to define a 2 dimensional input >>variable in entity. I think the syntax is something like this: >> >>v : in std_logic_vector(2 downto 0)(11 downto 0); >> >>Please advice. Thanks! >> > > > -- Karthikeyan Subramaniyam, Verification Engineer, TooMuch Semiconductor Solutions Pvt. Ltd. www.toomuchsemi.com A Bangalore based startup specialising on services in EDA & Verification.Article: 89990
Simon Peacock wrote: > first you create a type.. then assign it... > type v_typ is array (2 downto 0) of std_logic_vector(11 downto > 0); > signal v: v_typ > > now you can access it as > v(i)(j) <= -- something > > Simon > > > > "eeh" <eehobbyist@yahoo.com.hk> wrote in message > news:1128136736.906033.205550@z14g2000cwz.googlegroups.com... > > Hi, > > > > > > I am just beginner of VHDL. I want to define a 2 dimensional input > > variable in entity. I think the syntax is something like this: > > > > v : in std_logic_vector(2 downto 0)(11 downto 0); > > > > Please advice. Thanks! > > Very Thanks!Article: 89991
"Pete Fraser" <pfraser@covad.net> schrieb im Newsbeitrag news:11jqt4dj0bhh71b@news.supernews.com... > I'm doing a proof of concept that requires high quality video out. > Either RGB or composite is fine (both would be great). > > Spartan III or V4 preferred, with add-on modules OK. > > The ML401 is a great board, and great value, but the > rgb output just sucks. > > Anyone got any recommendations? http://www.hydraxc.com its not on the website yet, but there is base board for it that can be used standalone with following specs Chrontel CH7301 for DVI or RGB out V4 (SF363) can be fitted with LX15, LX25 or FX12 2 DDR2 memories header for micron camera header for char LCD rs232 uart there is no composite out though, if you need that then xilinx multimedia board has it, also several other boards are available AnttiArticle: 89992
"Francis" <NO_SPAM_stpierre_AT_grm.polymtl.ca_NO_SPAM> schrieb im Newsbeitrag news:0r6dnYvDxMRmNqDeRVn-gw@polymtl.ca... > I have a project EDK system.xmp in ISE. ISE does not initialize the > bitstream even if I do a update bitstream in ISE. I had to import ISE to 1 the .BMM support in ISE has been a problem forever. 2 DO NOT USE import or export between ise edk the only way to get it working properly is to add the edk as submodule in ISE project, to update the sw you double click on it, then compile the sw in xps and close xps and run bitgen in ISE. the only known way to me todo it. AnttiArticle: 89993
hetfield wrote: > Hi, all. > I'm using Xilinx FPGA with VHDL language. > > Now I try to build a system, and that system > needs a counter which counts "1" bit in bit stream. > like "11101001" => 5 > > I've tried several methods like adding all bits to one > integer signal, > (That is, result <= bit(0)+bit(1)+bit(2) ...;) > or by using Xilinx bit correlator with all "1" reference > bit stream. > > Is there any noble method for this problem? > Thanx for any help. > "in" is a standard_logic_vector( a downto 0) "result" is an integer. process(in) variable i:integer; variable sum:integer; begin sum := 0; for i in 0 to in'left loop sum := sum + in(i); end loop; result <= sum; end process; Hope there are not to much errors, I have no syntax check on hand right now. This is not executed sequentially. It only tells the compiler sequentially how to create the logic. You may need arithmetic libs to add bits to integer.Article: 89994
We did an integration of the Memec, now Avnet, CAN core some time back with our PCI/OPB bridge and a few other things that have been used successfully by a customer. In fact MINI-CAN started life as a "special" cut-down for the same customer who started out on Broaddown2 products. As to CAN cores of our own we have considered doing one. We don't see much of an issue in doing the actual design but handling of the licensing, and the approval by major car manufacturers, are a far more significant barrier to selling such a core. If can't sell it there isn't much point in us doing it and adding to our already very large roadmap of products to do. At the end of the day we are market driven in what we do so if someone can put a good case (usually money) we will do it. I will try and have the CAN core experience listed on our FAQ. Any constructive feedback on our products is always welcome and we do strive to be the best at what we do. I do hope we please most people with our new product Raggedstone1 and I will take the opportunity to thank those who recently contributed ideas to the design of this product. All of the ideas did not make it into the board design itself as we wanted to stay on selling cost budget. However we hope to cover most of those missed by way of add-on modules some of which are already in design. For those that are interested in the product we will have the bare boards back on Monday and be doing some real testing by early next week. Some pictures and specs should appear next week as should some release schedules. John Adair Enterpoint Ltd. - Soon to be home of Raggedstone1. The very cheap Spartan3 PCI Development Board. http://www.enterpoint.co.uk "Heinz-Jürgen Oertel" <hj.oertel@surfeu.de> wrote in message news:dhlj64$2ood$1@ulysses.news.tiscali.de... > John Adair wrote: > >> For all the hardened FPGA addicts and please excuse the sales push. >> >> If anyone is interested in our lower spec Broaddown2's BD2-400, BD2-1000 >> then we are having a stock clearance next week. Details will follow on >> our >> website shortly but pricing will be GBP£160 (BD2-400) and GBP£190 >> (BD2-1000) only while stock lasts. >> >> Our MINI-CAN boards now have an uprated spec for those intersted in these >> boards. Details to follow on the website but essentially you get a >> XC3S1000 now in the FPGA hole. >> >> John Adair >> Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development >> Board. >> http://www.enterpoint.co.uk > > > MINI CAN seems to be intended for CAN applications, the FAQ gives no > answer > about your experiences using CAN IP cores. Which one did you use? Do you > offer something? > > -- > > with best regards / mit freundlichen Grüßen > > Heinz-Jürgen Oertel > > +=================================================================== > > Merokok dapat menyebabkan kanker, serangan jantung, > impotensi dan gangguan kehamilan dan janin.Article: 89995
1. Clock doubling is only available in Low frequency Mode. 2. Tested, no such errors could be related to the problem.Article: 89996
Could you suggest some devices which are suitable to run at a clock rate more than 311MHz?Article: 89997
"Antti Lukats" <antti@openchip.org> wrote in message news:dhm897$gms$05$1@news.t-online.com... > > http://www.hydraxc.com > > its not on the website yet, but there is base board for it that can be > used > standalone with following specs > > Chrontel CH7301 for DVI or RGB out > V4 (SF363) can be fitted with LX15, LX25 or FX12 > 2 DDR2 memories > header for micron camera > header for char LCD > rs232 uart > > there is no composite out though, if you need that then xilinx multimedia > board has it, also several other boards are available > Thanks Antti, and welcome back. Do you know the quality of the video on any of these boards first hand? The ADI DAC that is used on the ML401 is a fine part (I've used it in many of my own designs). I just think the layout is not optimal for the RGB output.Article: 89998
"Antti Lukats" <antti@openchip.org> wrote in message news:dhm897$gms$05$1@news.t-online.com... > > http://www.hydraxc.com > > its not on the website yet, but there is base board for it that can be > used > standalone with following specs > > Chrontel CH7301 for DVI or RGB out > V4 (SF363) can be fitted with LX15, LX25 or FX12 > 2 DDR2 memories > header for micron camera > header for char LCD > rs232 uart > Do you know when it will be available, and how much it will cost?Article: 89999
I am using ISE tool for implementing my design.But i am facing a problem.In this tool it is written that some modules are supported to infer rather than inatantiate. My prof says to make design wholly structural . and using the modules available, just like we do in shematic. But since for some design elements , instatiating is not supported, i cant do it.I have to write a module code to infer that module.but according to prof this should not be the way. Second thing while making these design elements (like counter) with flip flop and gates (for which instantiation is supported), its min clock period is large compared to the one which is inferred.Suggest me what can do here. Third in case of inferring the element is mapped to some Macros and LUT.Can someone please explain me give some reference , what is phisically these are and to what hardware they are actually mapped.
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