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Messages from 525

Article: 525
Subject: Re: Any Way to Download a XNF to FPGA
From: andrew@atri.curtin.edu.au (Andrew Phillips)
Date: 20 Dec 1994 00:48:10 GMT
Links: << >>  << T >>  << A >>

It is possible to download an XNF file to any Xilinx FPGA. If you program the device to have, say, an asynchronous serial port you could download the file to it via a PC UART quite easily. Try designing further logic inside the FPGA to low-pass filter the incoming data with a 10th-order Bessel frequency chanracteristic and then construct interface logic to send the resulting data stream to an off-chip D/A converter. The resulting waveforms would be both interesting and useless.

Andrew Phillips (andrew@atri.curtin.edu.au)
Cooperative Research Centre for Broadband Telecommunications & Networking
Bentley, Perth Western Australia


Article: 526
Subject: wir2xnf License
From: alex@kodiak.vlsivie.tuwien.ac.at (Alexander Jaud)
Date: 20 Dec 1994 12:50:36 GMT
Links: << >>  << T >>  << A >>
Hi,

I just finished installing Xilinx SW 5.0.
My first test was to get a design from Powerview into a Xilinx FPGA.
But wir2xnf (and xnf2wir) is complaining about missing licenses.

My question:

Where do I get the license for wir2xnf (which I installed with the
Xilinx software) from? Xilinx or Viewlogic?

Thanks
ALex


--
--
******************************************************************************
Alexander Jaud | Dep. for VLSI Design | Univ. of Technology |  Vienna, Austria
Email: alex@vlsivie.tuwien.ac.at | Phone: +43 1 58801-8156 | Fax +43 1 5869697
******************************************************************************
Confidence is the feeling you have before you understand the situation.


Article: 527
Subject: Re: Analog FPGA ???
From: sgh@wdl.loral.com (Steve Hoeft)
Date: Tue, 20 Dec 1994 23:40:15 GMT
Links: << >>  << T >>  << A >>
In article <1994Dec17.013957.27818@sequent.com>, mittra@sequent.com
(Swapnajit Mittra) wrote:

>   Few days back I saw some posting regarding 'analog FPGA' in this
>   newsgroup. Somebody gave reference to some articles in Electronic
>   Design(?). Can someone repost the information regarding that ?
> 
>   Thanks in advance,
>   Swapnajit

-- Try Electronic Design Oct. 14,1994 page 63
+------------------------------------------------------------------------+
Steve Hoeft           e-mail sgh@wdl.loral.com      This is my very
                                                    personal opinion!
Loral WDL             voice  (408)473-6479          
3200 Zanker Rd.       fax    (408)473-4093
San Jose, CA 95134


Article: 528
Subject: Re: Analog FPGA ???
From: kruithof@hannover.sgp.slb.com (Andries Kruithof)
Date: 21 Dec 1994 11:47:32 GMT
Links: << >>  << T >>  << A >>
In article 27818@sequent.com,  mittra@sequent.com (Swapnajit Mittra) writes:
=>  Few days back I saw some posting regarding 'analog FPGA' in this
=>  newsgroup. Somebody gave reference to some articles in Electronic
=>  Design(?). Can someone repost the information regarding that ?
=>
=>  Thanks in advance,
=>  Swapnajit


The analog FPGA is actually called an EPAC (tm): Electrically Programmable
Analog Circuit.
It is made by IMP Inc., 2830 N. First Street, San Jose, California
telephone: 408.432.9100 or 1.800.438.3722

It consists of 8 mux-ed differential inputs (or 16 single ended inputs), 
input filter, input opamp, 2 differential inputs going to another op-amp,
internally 3 op-amps, and then 3 output op-amps, + some other stuff (pls 
see the data-sheets for details)
System bandwidth max.: 132KHz

I think it is an interesting device, for example when you're making a digital
design, and need to watch some sensors. Instead of needing op-amps, resistors
and all the stuff you use 1 IC (for up to 8 sensor-inputs).
And hopefully they'll come out with different EPAC's (the one they've got now
has limited filtering capability).

This is from the datasheets and my impression. Is there anybody out there who
already has actually used this chip (for prototyping or otherwise), who can
tell us how the chip is in real-life app's?


Andries

---
------------------------------------
| Message is author's opinion only |
|                                  |
| Andries Kruithof                 |
| Schlumberger Geco-Prakla         |
| kruithof@hannover.sgp.slb.com    |
------------------------------------




Article: 529
Subject: Re: wir2xnf License
From: alex@kodiak.vlsivie.tuwien.ac.at (Alexander Jaud)
Date: 22 Dec 1994 08:28:26 GMT
Links: << >>  << T >>  << A >>
Alexander Jaud (alex@kodiak.vlsivie.tuwien.ac.at) wrote:
: Hi,

: I just finished installing Xilinx SW 5.0.
: My first test was to get a design from Powerview into a Xilinx FPGA.
: But wir2xnf (and xnf2wir) is complaining about missing licenses.

: My question:

: Where do I get the license for wir2xnf (which I installed with the
: Xilinx software) from? Xilinx or Viewlogic?

: Thanks
: ALex

Thank to all who tried to help me.

I just want to summarize:

We are using Powerview 5.2 on an Sun Sparc.  

wir2xnf is still using the old name for the ini-file (workview.ini
instead of powerview.ini). All I had to do is to copy the line
"LICENSE_SERVER <name>" from the new ini-file to the old one. I got
this information directly from the XILINX people - thank you for
reading this group and helping me out.

ALex 
: --
: --
: ******************************************************************************
: Alexander Jaud | Dep. for VLSI Design | Univ. of Technology |  Vienna, Austria
: Email: alex@vlsivie.tuwien.ac.at | Phone: +43 1 58801-8156 | Fax +43 1 5869697
: ******************************************************************************
: Confidence is the feeling you have before you understand the situation.

--
--
******************************************************************************
Alexander Jaud | Dep. for VLSI Design | Univ. of Technology |  Vienna, Austria
Email: alex@vlsivie.tuwien.ac.at | Phone: +43 1 58801-8156 | Fax +43 1 5869697
******************************************************************************
Confidence is the feeling you have before you understand the situation.


Article: 530
Subject: Data compression schemes using FPGAs
From: sanjanai@carlserver.carl.ua.edu (A. Shakuntala)
Date: Thu, 22 Dec 1994 17:18:47 GMT
Links: << >>  << T >>  << A >>
Hi,

I will be working on the implementation of data compression schemes 
using FPGAs for my thesis. I would like to know if there is a good 
source in terms of hardware schemes (not necessarily FPGAs), some 
ftp site, or a book which can give me a brief insight on the 
implementation specifics. 

Any hints, references to articles, or experience in this field will
be highly appreciated. Thanks for your time and response.

Shakuntala

##################################################################
Shakuntala Anjanaiah
Electrical Engineering Department
University of Alabama
Tuscaloosa

e-mail: sanjanai@buster.eng.ua.edu
                  or
        sanjanai@carlserver.carl.ua.edu
##################################################################


Article: 531
Subject: Xilinx Configuration
From: borodin@sunhe.jinr.dubna.su (Borodin S.V.)
Date: Fri, 23 Dec 94 13:32:54 GMT
Links: << >>  << T >>  << A >>


Recently I encountered one strange thing which seems to be not
documented in Xilinx Handbooks. I have a setup where I can 
confugure XC3020 via 80C552 (it's a 8051 core + stuff) using
slave serial mode. When I do this after Power-Up (read - from
an on-board PROM) INIT pin seems to be not working properly,
e.g. a program responsible for downloading config info into Xilinx
constantly monitors the INIT pin and if (and only if) it goes
high it starts the process. At power up this scheme doesn't work,
while all hanbooks say that INIT tells the configuring micro when
to proceed. In other words, when it can starts the process. 

Can anybody tell me what I'm doing wrong? Consider the fact that
I cheated this by including a stupid very long delay before I 
start the confuguration ( for(i=0;i<65535; i++) ), which is obviously
not the best solution.

S.B.




Article: 532
Subject: multipliers!
From: h9219523@ (Chiu See Ming <EEE3>)
Date: Sat, 24 Dec 1994 13:29:08 GMT
Links: << >>  << T >>  << A >>


Hello.
	I am doing a project on a correlator and within 1000 ns I have to
get a result. I have to do 256 multiplication on 2 sets of 12-bit binary
numbers and then do 255 additions! Surely 1000ns is too little time, and the
problem is that I have to do that in REAL TIME~! :<

Can anybody suggest me any fast algorithm on multiplier and addition, or
any fast architecture on the whole system?


Thanks! Thanks! Thanks!

Regards,
David.



Article: 533
Subject: fpga-compiler (synopsys)
From: yaron@xvnews.unconfigured.domain (yaron kretchmer)
Date: 26 Dec 1994 08:18:50 GMT
Links: << >>  << T >>  << A >>
Hi everybody.
Can you read XNF files with CLB's & IOB's into synopsys fpga-compiler?
If not, how can you translate the CLB's into logic equations?
thanks
yaron


---
************************************************************************
*  Yaron Kretchmer                   LSI Logic ISRAEL          ------  *
*  Phone  +972-3-5403741                 Sokolov 40       LSI | LOGIC| *
*  Fax    +972-3-5403747                 Ramat Hasharon       |      | *
*                                        Israel 47100         |      | *
*                                        P.O.Box 1331         -------- *
*  email  yaron@lsi-logic.co.uk or      (outside LSI)                  *
*								       *
*								       *
*								       *
*	disclaimer: these views are mine, only mine		       *
************************************************************************





Article: 534
Subject: Re: multipliers!
From: chaseb@netcom.com (Bryan Chase)
Date: Mon, 26 Dec 1994 22:40:53 GMT
Links: << >>  << T >>  << A >>
Chiu See Ming <EEE3> (h9219523@) wrote:


: Hello.
: 	I am doing a project on a correlator and within 1000 ns I have to
: get a result. I have to do 256 multiplication on 2 sets of 12-bit binary
: numbers and then do 255 additions! Surely 1000ns is too little time, and the
: problem is that I have to do that in REAL TIME~! :<

: Can anybody suggest me any fast algorithm on multiplier and addition, or
: any fast architecture on the whole system?


: Thanks! Thanks! Thanks!

: Regards,
: David.

Although this probably doesn't belong in comp.arch.fpga, I'll fill my
design with FPGAs where I can...
 
You did not mention if you were concerned about the cost of this.  Since
I work for a defense contractor and my labor is more costly than the parts
could ever be, I am less concerned with cost.  Typical MAC (multiply-
Accumulate) chips, which are designed for your application, run at about
25Mhz (TTL/CMOS, if you really don't care about cost go for ECL at >250Mhz).
The brute-force method would say you buy 16 MAC chips at 25 Mhz and feed data
to all of them in parallel. This takes 16 times a 25 Mhz period, or 640nSec.
You'll need to come up with some way to store up the incoming data so that 
it can be distributed to each circuit properly.  The timing will get a 
little tricky here, and you'll probably want to throw in a few FPGAs to 
accomplish this, and the various glue-logic tasks associated with the MACs.

Then, you'll end up with 16 results that need to be added to each other.  
Because of your time constraint, you'll want to store these 16
results in some registers (just d-flip-flops, although if you wish to
preserve *all* the bits, you've got 16 x 24 bit registers) and start up 
the MACs on the next set of data.  This pipelined approach will save you 
time.  In order to add these 16 results, the cheapest way is probably with 
two accumulators (maybe built into another FPGA) and a multiplexer that
chooses two results at a time and keeps on accumulating to the final
result.  This will take, say, 9 cycles (with two accumulators, plus one
add of these two accumulators) at 25 Mhz period, or another 360nSec, but
remember that this is being done while the MACs are starting on the next
data set.  You'll need to then store this result somewhere.  With this 
architecture you can easily get your total through-put time down to less 
than 1000nsec.  It will be more than 640nSec because it will take some 
time to organize the distribution of data coming in, and maybe a cycle 
or two to clear out the MACs, depending on the brand.  It may also take
some time to put the final result somewhere.

If you don't wish to "carry all the bits" as they say, you can choose
to do the 12 bit multiplies and only pick, say, 12 bits of the result
to carry on.  You'll then need some saturation logic so that if you end
up picking *not* the top 12 bits, and the result is bigger than can fit 
in your register, the register should hold the largest number, and not
wrap-around zero.  That would be very bad.

In summary, if you throw enough money (a.k.a. hardware) at the problem,
you can do 256 Multiply-Accumulates fairly easily with TTL/CMOS parts
that you can buy at Fry's Electronics.  The solution is bulky and power
hungry, but it'll do the job.  If you throw even more money 
at it you can do the thing with fewer ECL parts, but they are much 
harder to get.

Good Luck!

-bryan chase
chaseb@netcom.com


Article: 535
Subject: Re: fpga-compiler (synopsys)
From: jason@cad.ccl.itri.org.tw (Jason Wang)
Date: Tue, 27 Dec 1994 03:06:39 GMT
Links: << >>  << T >>  << A >>
yaron kretchmer (yaron@xvnews.unconfigured.domain) wrote:
: Can you read XNF files with CLB's & IOB's into synopsys fpga-compiler?
: If not, how can you translate the CLB's into logic equations?

Please try as the followings:

xnf2syn                 (unrelased shell script provided by synopsys,
                        which solves the difference in library modeling)
read -f xnf design.sxnf (in your fpga compiler)

hope this helpful

--
***********************************************************************
*Design Automation Development Dept.                *Jason Wang       *
*  Communication & Computer Research Lab., Taiwan   *TEL:886-35-917593*
*E-mail : jason@kvsun11.ccl.itri.org.tw             *FAX:886-35-820025*
***********************************************************************


Article: 536
Subject: Re: multipliers!
From: Phillip Roberts <proberts@rmii.com>
Date: 27 Dec 1994 03:29:28 GMT
Links: << >>  << T >>  << A >>
chaseb@netcom.com (Bryan Chase) wrote:
>
> Chiu See Ming <EEE3> (h9219523@) wrote:
> 
> 
> : Hello.
> : 	I am doing a project on a correlator and within 1000 ns I have to
> : get a result. I have to do 256 multiplication on 2 sets of 12-bit binary
> : numbers and then do 255 additions! Surely 1000ns is too little time, and the
> : problem is that I have to do that in REAL TIME~! :<
> 
> : Can anybody suggest me any fast algorithm on multiplier and addition, or
> : any fast architecture on the whole system?
> 
> 
> : Thanks! Thanks! Thanks!
> 
> : Regards,
> : David.
> 
> Although this probably doesn't belong in comp.arch.fpga, I'll fill my
> design with FPGAs where I can...
>  
> A description of a time domain approach to solving the problem 
> follows.

	Brians time domain approach will work but is probobly not
the most efficient for a 256 point correlation.

	A frequency domain approach would work as follows:

	1. FFT 2k input data points with a overlap between 
	   input vectors of 256 point.

        2, Multiply the frequency domain data by the frequency
	   domain representation of the correlation data. (the
           correlation data may have to be time reversed)
	
	3. Perform the inverse FFT of the data and discard the
	   first 256 points.

	This will result with fewer multiply accumulate operations
than a time domain aproach. And more importantly their are dedicated
chips available from Sharp,Array,Plessy to do the FFT. They can
perform the correlation at a 1 Mhz rate with no problem.

****************************************************************************************
*  Phillip Roberts                             *     OPTIMUM SOLUTIONS                 *
*  Optimum Solutions                           *     Digital Design Consultants        *
*  E-Mail: proberts@rmii.com                   *                                       *
*  HTTP: ftp://rmii.com/pub2/proberts/home.htm *                                       *
****************************************************************************************





Article: 537
Subject: LCA file disassembler and other tools.
From: dh@fncrd7.fnal.gov (don husby)
Date: 27 Dec 1994 17:11:30 GMT
Links: << >>  << T >>  << A >>
yaron@xvnews.unconfigured.domain writes:
>Hi everybody.
>Can you read XNF files with CLB's & IOB's into synopsys fpga-compiler?
>If not, how can you translate the CLB's into logic equations?
>thanks

I have written a number of tools to make Xilinx a more pleasant 
experience.  One of these is a disassembler that takes an X4000 LCA 
file and lists it in a PAL like format.  There are other tools which 
you may find useful.  I have tried to package them in a useful format,
but this is hacker-stuff: I'm not getting payed to do a professional 
job.

I have used these tools extensively using pre-5.0 Xilinx software. 
These tools have not been tested under XACT 5.0.  Most of them should
work.  I will test them some time, but I have just discovered AT&T
ORCA and NEOCAD, and may abandon my Xilinx software altogether.

This is a uu-encoded, zipped archive.  To install it, do the 
following:

1) Save this message as a file named awks.uu.
2) Create an AWKS directory in your XACT path:
   > mkdir c:\XACT\AWKS
3) UUDECODE the file into that directory:
   > copy awks.uu c:\XACT\AWKS
   > uudecode awks.uu
4) Unzip:
   > pkunzip -d awks.zip

>>>>>>>>  file unpacked into awks.zip  <<<<<<<<


Article: 538
Subject: 6 th IEEE International Workshop Rapid Systems Prototyping
From: jma@descartes.super.org (Jeffrey M. Arnold)
Date: Tue, 27 Dec 1994 17:57:12 GMT
Links: << >>  << T >>  << A >>

                     7-9 June , 1995
       OMNI Europa Hotel, Chapel Hill, North Carolina


                         CALL FOR PAPERS
	
         Hardware-Software Codesign and Codevelopment:
             Reducing System Introduction to Market

The IEEE International Workshop on Rapid System Prototyping 
presents and explores the trends in rapid prototyping of Computer 
Based Systems including, but not limited to, communications, 
information, and manufacturing systems. The sixth annual workshop 
will focus on improved approaches to resolving prototyping issues and 
problems raised by incomplete specifications, increased system 
complexity and reduced time to market requirements for a multitude of 
products. The workshop will include a keynote presentation and formal 
paper sessions with a side range of system prototyping topics, which 
include, but are not limited to the following:

o System Emulation	
o Virtual Prototyping	
o Hardware-Software Codesign
o Tools for hardware prototyping
o Tools for software prototyping
o The role of FPGAs in system prototyping
o Prototyping case studies
o Very large scale system engineering
o Hardware/software tradeoffs
o System verification/validation
o Prototype to product transition

The program committee invites authors to submit five copies of an 
extended summary or a full paper (preferred) presenting original and 
unpublished work. Clearly describe the nature of the work, explain its 
significance, highlight its novel features, and state its current status. 
Authors of selected papers will be requested to prepare a manuscript for 
the workshop proceedings.

o Papers due.	  January 15, 1995
o Notification of Acceptance.	  February 15, 1995
o Final Camera Ready Manuscript due    March 15,1995

Submit all papers to:			For General Information, Contact:
Rudy Lauwereins				Nick Kanopoulos
Katholieke Universiteit Leuven		Center for Digital Systems Engineering
Kard. Mercierlaan 94			Research Triangle Institute
B-3001 Heverlee				3040 Cornwallis Road
Belgium	Research 			Triangle Park, NC 27709
+32 16 22-0931 / +32 16 22-1855 fax	(919) 541-7341 / (919) 541-6515 fax
Rudy.Lauwereins@esat.kuleuven.ac.be	rsp@rti.rti.org

The IEEE Rapid Systems Prototyping Workshop is cosponsored by:
	IEEE Computer Society
	Technical Committees on:
	Design Automation - Simulation - Test Technology

General Chair
N. Kanopoulos - RTI

Program Chair
R. Lauwereins - Katholieke Univ. Leuven

Publicity Chair
A.A. Jerraya - INPG/TIMA

Program Committee
K. Anderson - Siemens
T. Antonakopoulos - Univ. of Patras
J. Arnold - IDA Supercomputing Research Center
J. Beetem - MITRE
J-Y. Brunel - Philips
V. Calandra - Zycad
B. Candaele - Thomson-CSF
J.D. Carothers - Univ. of Arizona
B. Courtois - INPG/TIMA
W. Debany - Rome Laboratory
A. Dollas - Technical Univ. of Crete
M. Engels - Katholieke Univ. Leuven
P. Fiore - Lockheed
M. Glesner - Technische Hochschule Darmstadt
P. Henderson - Univ. of Southampton
P. Hulina - Penn. State Univ.
S. Note - Philips ITCL
B. Rector - U.S. Dept. of Defense
C. Tong - Colorado St. Univ.
S. Winkler - NIST




Article: 539
Subject: Re: multipliers!
From: petav@Physik.TU-Muenchen.DE (Peter Averkamp)
Date: 28 Dec 1994 19:45:16 GMT
Links: << >>  << T >>  << A >>
h9219523@ (Chiu See Ming <EEE3>) writes:

>Hello.
>	I am doing a project on a correlator and within 1000 ns I have to
>get a result. I have to do 256 multiplication on 2 sets of 12-bit binary
>numbers and then do 255 additions! Surely 1000ns is too little time, and the
>problem is that I have to do that in REAL TIME~! :<

>Can anybody suggest me any fast algorithm on multiplier and addition, or
>any fast architecture on the whole system?


>Thanks! Thanks! Thanks!

>Regards,
>David.


1000 ns for 256 multiplications and 255 additions that means roughly
2 ns per operation, including result storage. If you do not want to get into
fairly nasty custom ECL logic, it seems that you cannot solve this without
a certain degree of parallelization.

Let's see how far you could get: 12-bit binary means 2^12 possible
operands. As you do not specify what type of multiplication you want to
do, I assume it is 12-bit by 12-bit. If you have a 2^24 times 25 bit big
lookup table you could do lookups within memory bandwidth.
You can implement a 24-bit adder that takes 30-50ns easily with almost
any technology. Then you need another memory access to store the result.
If you want to reuse this engine to operate on multiple operands you
need some address and state engine to handle that.

So my estimation: around 100ns per op, giving 10 ops per unit, thus using
                  25 units.

                  As each unit would need ~24Mb of lookup, but only a
                  fairly trivial FPGA to do the rest, I'd say you are
                  limited by the cost of the memory in implementing this.


Maybe I am completely way off in understanding your problem, though...

Just my 2 Pfennigs,

 Peter

--
Peter Averkamp,                      | email:
Physics Department E20               | petav@radon.e20.physik.tu-muenchen.de
Techn. Univ. of Munich               | Phone: ++49 (89) 3209-2408 and -2814
D-85748 Garching, Germany            | Fax:   ++49 (89) 3209-2338


Article: 540
Subject: Problem with Flexlogic and PLDshell+
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 28 Dec 1994 20:34:39 GMT
Links: << >>  << T >>  << A >>
Iıve a problem with Altera PLDshell+ and Flexlogic FX780_84 (both née
Intel). At least for the design I have tried, using
input_pullup=ttl_level or input_pullup=cmos_level has no effect. That is
the JEDEC files produced using these options (and no other changes) are
identical. As I understand there should be differences resulting, at
least, from extra pullups in the TTL version.

I have sent the file to Altera, but I wonder if anyone else has noticed
this.

On a related point, does anyone have a document (or can point me towards
one) on decoding Flexlogic JEDEC files. I would like to know which way
the generated file is being produced.
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 541
Subject: Which FPGA should I be looking at
From: Chris@ruatha.demon.co.uk (Chris G Abbott)
Date: Wed, 28 Dec 1994 22:11:49 +0000
Links: << >>  << T >>  << A >>
I am working on a disign that requires some FPGA's. This is a low volume
play project so the device chosen needs to be cheep, easily available,
preferably programmable on board, or re-programable with a HILO-ALL3
programmer (If anyone knows the socket addaptor wiring envolved). The bigest
problem I seem to be up agains is a v-low cost (preferably free) design
program to compile to the device above.

I do have a good source of TI FPGA's, at low prices in small quantities,
but these are one-time-programmable, and I don't have the software.

Any ideas, ftp.sites would be most welcome.

-- 
God Bless

Chris Abbott
============================================================================


Article: 542
Subject: Dual Xilinx 4000->3000 question
From: jwcollin@chorizo.engr.ucdavis.edu (Jeff Collins)
Date: 28 Dec 1994 22:35:38 GMT
Links: << >>  << T >>  << A >>
Hello.  I am designing a system with 2 Xilinx chips, one a 4000 series 
and one a 3000 series.  The 4008 is the lead device and will be 
programmed by a 68k in synchronous peripheral mode.  I'm hoping that the 
3000 part can be daisy chained and programmed simultaneously.  I do 
realize that the other control pins are a bit different.  

Can this really work??  The 3000 & 4000 series parts have different frame 
styles and a different postamble.

Thanks,
Jeff
--
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-
Jeff Collins				    jwcollin@engr.ucdavis.edu	
Intelligent Manufacturing Systems/           collinsj@ece.ucdavis.edu
    Mechatronics Lab, 1065 Bainer Hall        collinsj@cs.ucdavis.edu
University of California, Davis                 jwcollins@ucdavis.edu
-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-



Article: 543
Subject: Virtual Computers ( a company ), location?
From: dcy@netcom.com (David C. Young)
Date: Wed, 28 Dec 1994 23:12:57 GMT
Links: << >>  << T >>  << A >>
I have read a few articles in EE-Times re: Virtual Computers and have been
unable to locate them.  Would someone send me e-mail if you know of them
or better yet, if you work there?

thanks,
David C. Young
dcy@netcom.com



Article: 544
Subject: Re: Which FPGA should I be looking at
From: jhallen@world.std.com (Joseph H Allen)
Date: Wed, 28 Dec 1994 23:48:16 GMT
Links: << >>  << T >>  << A >>
In article <788652709snz@ruatha.demon.co.uk>,
Chris G Abbott <Chris@ruatha.demon.co.uk> wrote:
>I am working on a disign that requires some FPGA's. This is a low volume
>play project so the device chosen needs to be cheep, easily available,
>preferably programmable on board, or re-programable with a HILO-ALL3
>programmer (If anyone knows the socket addaptor wiring envolved). The bigest
>problem I seem to be up agains is a v-low cost (preferably free) design
>program to compile to the device above.

>I do have a good source of TI FPGA's, at low prices in small quantities,
>but these are one-time-programmable, and I don't have the software.

>Any ideas, ftp.sites would be most welcome.

JDR Microdevices (800-538-5000) sells low-end Xilinx parts and programming
tools.  The parts are cheap: between $10 and $50 ($44 for a 270MHz XC3130). 
But the programming tool (Xact) costs $1000 (which sucks) and you need a
schematic capture program as well (another $500 for OrCAD).  This is a lot,
but the FPGAs are so useful that it's worth the investment.

BTW, does anyone know how much 4000 series parts cost and how much it is to
upgrade the base-level xact to the version which can program these?

The Xilinx parts are very nice since they use static-ram for their
configuration.  You usually just have a computer load them whenever the
machine boots.  The FPGAs are in PLCC packages, but you can stick a PLCC
solder socket into a PGA wire-wrap socket.

Also Intel sells FPGAs (I think they call them Flex Logic) and give their
programming tools away for free.  I've never used them, but I think they are
slower (at least in terms of peak speed), have fewer clocking options, but
allow you to trade part of the configuration ram for ram usable by your
application.

Has anyone used these?  I'd like to hear about their tools.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}


Article: 545
Subject: Re: Which FPGA should I be looking at
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 29 Dec 1994 00:06:11 GMT
Links: << >>  << T >>  << A >>
In article <788652709snz@ruatha.demon.co.uk> Chris G Abbott,
Chris@ruatha.demon.co.uk writes:
> I am working on a disign that requires some FPGA's. This is a low volume
> play project so the device chosen needs to be cheep, easily available,
> preferably programmable on board, or re-programable with a HILO-ALL3
> programmer (If anyone knows the socket addaptor wiring envolved). The
bigest
> problem I seem to be up agains is a v-low cost (preferably free) design
> program to compile to the device above. 

The general rule in this game is that you have to be prepared to purchase
the basic mapping software. There are few exceptions. You do not state
the purpose of the project, so it is difficult to discuss the devices. We
use Altera (formally Intel) Flexlogic ICs for control purposes and Xilinx
for more arbitary things ­ we often mix the two. 

The Flexlogic devices are not strictly speaking FPGAs (in my opinion) but
EPLDs, that contain several PAL like blocks. However, they are no means
unique in this, many do classify them in this bracket. Iıve done simple
counters and incrementers with them but they are best for state machine
style logic and equations. Typical prices are about £28+VAT for an FX780.
They are not reprogrammable but can be reconfigured - a new configuration
can be downloaded once the system has been powered up but only one can be
stored permanently. Free software (PLDshell+) is available from Altera
and will run on PCs. You need a download cable (last one I bought was
about £70+VAT) but it should be possible to make one up. The software was
still on ftp.intel.com last time I looked.

We use 4000 series Xilinx devices, but they are not cheap ­ 4005As were
about £100 six months back and the prices climb. If you are university
the best source in the EU is via Eurochip, but otherwise you can contact
microcall in the UK for a price. Eurochip prices are not normally zero,
but are much lower than commercial. I understand that the straight Altera
devices (Max and Flex) is free under the scheme ­ or at least it was.

Pilkington microelectronics do a demo version for their software - their
FPGA design is sold by motorola. The demo is apparently limited to 2000
gate complexity and I donıt know any prices for the ICs, but they are
SRAM based ­ so will be reprogrammable.

Iım sure other people have some better ideas.
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 546
Subject: Re: Which FPGA should I be looking at
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 29 Dec 1994 00:20:23 GMT
Links: << >>  << T >>  << A >>
In article <D1JosG.Cyy@world.std.com> Joseph H Allen,
jhallen@world.std.com writes:
> The Xilinx parts are very nice since they use static-ram for their
> configuration.  You usually just have a computer load them whenever the
> machine boots.  The FPGAs are in PLCC packages, but you can stick a PLCC
> solder socket into a PGA wire-wrap socket.

I usually use a microprocessor on the same board, but you can also use
serial or straight EPROM configurations. Xilinx also make a debugging
device that plugs into a serial port and allows one to download designs,
stop, return internal values etc - if one properly configures the
hardware and the designs.

>
> Also Intel sells FPGAs (I think they call them Flex Logic) and give
their
> programming tools away for free.  I've never used them, but I think
they are
> slower (at least in terms of peak speed), have fewer clocking options,
but
> allow you to trade part of the configuration ram for ram usable by your
> application.

At what they are good at - state machines and control equations -
flexlogic is if anything quicker. I normally use 10ns parts, where each
pin-to-pin delay is <10ns. The only catch is that any factorisation needs
its own 10ns. Xilinx is better for arithmetic, but still slower than
fuse-based devices such as Actels.
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 547
Subject: PCI with Xilinx XC3100 series
From: joel@hibp2.ecse.rpi.edu (Joel Glickman)
Date: 29 Dec 1994 15:18:07 GMT
Links: << >>  << T >>  << A >>
I downloaded the VHDL code to implement PCI on the XC3100 series FPGAs.
Has anyone successfully implemented PCI on a Xilinx FPGA? Any tips?
Also, email me if you want a copy of the VHDL code for Xilinx FPGAs &
EPLDs.

-Joel Glickman
 Spectrum Research Corporation



Article: 548
Subject: Re: Which FPGA should I be looking at
From: Chris@ruatha.demon.co.uk (Chris G Abbott)
Date: Thu, 29 Dec 1994 20:15:01 +0000
Links: << >>  << T >>  << A >>
Here is a bit more info on my project.

Basically I am building a CPU with FPGA/EPLD/PLD/Logic in that order of
preference as the PCB gets simpler, smaller and cheeper. One of the main
requirements are latches in one of the devices.

1 Section Needs      1 IC Solution              3 IC Solution
 
                      384 latches                128 latches
                       24 OP                       8 OP
                       32 IP                      18 IP 
                      Bit of Logic               Bit of Logic

Hope this clarifies things a bit. Thanks for the info so far.
-- 
God Bless

Chris Abbott
============================================================================


Article: 549
Subject: FlexiLogic - Few Questions
From: Chris@ruatha.demon.co.uk (Chris G Abbott)
Date: Fri, 30 Dec 1994 14:08:57 +0000
Links: << >>  << T >>  << A >>
1)  Does anyone know some UK suppliers
2)  I have the latest version of PLDShell from 'ftp.intel.com' but there
    is no documentation, it there any, how do I work the design language.

If any nice people out there can help I would be greatfull.

Hope you all have a Happy New Year.

-- 
God Bless

Chris Abbott
============================================================================




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