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Messages from 2600

Article: 2600
Subject: Re: Career value: VHDL or Verilog?
From: simond@vchips.com (Simon J Davidmann)
Date: Wed, 10 Jan 1996 11:30:14 +0000
Links: << >>  << T >>  << A >>
In article <CNUDDEP.96Jan2074140@btmq0f.sh.bel.alcatel.be>,
cnuddep@sh.bel.alcatel.be (peter cnudde sh146 8218) wrote:

> Sorry, in the US this might be the case, but in Europe nearly everybody is
> using VHDL. (Japan also has a preference towards VHDL)
> 

I am afraid the facts don't agree with your statement - having spent the
past 7 years involved with the sales & support of Verilog & Vhdl
simulators within Gateway, Cadence, Chronologic, Viewlogic - in Europe - I
KNOW that there are significant numbers of designers using Verilog IN
EUROPE - on a daily basis - building leading-edge chips and systems. It is
an interesting illusion that Europe is all Vhdl - I agree it probably is
for FPGA - but no way for ICs. Yes we talk a lot about Vhdl - (there is a
lot to talk about how to get Vhdl design systems/flows to work :-)) but
reality is a lot of people in Europe use Verilog.

[Currently my company provides both Verilog & Vhdl products - so I have no
axe to grind.]

Simon Davidmann
Virtual Chips, Inc.


Article: 2601
Subject: Re: Career value: VHDL or Verilog?
From: veit@mururoa.gmd.de (Holger Veit)
Date: 10 Jan 1996 11:56:31 GMT
Links: << >>  << T >>  << A >>
In article <30F006C0.167EB0E7@easics.be>, Jan Decaluwe <jand@easics.be> writes:
|> Apparently there is still a need to use assembler in software
|> design. However, I don't believe that there is still a real need
|> for schematic entry at the gate level in hardware design.

Make that "boolean equations" as in tools like PALASM. This is still assembler-
like level and is still used all around the world to express logic and optimize
small and medium programmable circuits. If you know how the cells are built and
arranged inside the PAL or FPGA and know how the placement and logic synthesis
mechanisms work, you can, with some experience still optimize the number of
used cells and gates in the circuit. I have seen this people doing more than
once in order to fit more logic into a limited chip. I consider this really
bad practice.

FWIW: expressing an FSM as a big case statement switching a state
variable and the outputs in VHDL doesn't make the description a high-level one
either.

-- 
         Dr.-Ing. Holger Veit             | INTERNET: Holger.Veit@gmd.de
|  |   / GMD - German National Research   | Phone: (+49) 2241 14 2448
|__|  /  Center for Information Technology| Fax:   (+49) 2241 14 2242
|  | /   Schloss Birlinghoven             | "They're not sending back [Win95]
|  |/    D-53754 Sankt Augustin, Germany  | because it's not selling well; they
         WWW: http://borneo.gmd.de/~veit/ | have overordered" (M$ spokesperson)


Article: 2602
Subject: Re: [q][Reverse Engineering Protection]
From: David Pashley <david@fpga.demon.co.uk>
Date: Wed, 10 Jan 96 12:13:14 GMT
Links: << >>  << T >>  << A >>
In article <PKH.96Jan10115036@fantti.tky.hut.fi>
           pkh@alpha.hut.fi "Petri Havanto" writes:

"Somehow it seems to me that 'easy' is not exactly the right word. I
"mean, if it was, I suppose the Xilinx bitstream-decryption wold have
"been cracked a long time ago. On the other hand, maybe it is, it would
"hardly be something to publish loudly. Maybe it is reasonable to feel
"a little bit paranoid about the security of the bitstreams as well...
"
The bitstream was cracked long ago by NeoCAD, who made a business 
out of providing place and route tools (which obviously had to have 
a bitstream output), initially against Xilinx's wishes.


-- 
David Pashley                 <
 ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| *The EDA Source*         <  <  <               Fax: +44 1280 700577      |
 ---------------------------  <  ------------------------------------------


Article: 2603
Subject: Re: [q][Reverse Engineering Protection]
From: Andrew Morley <andym@trend.demon.co.uk>
Date: Wed, 10 Jan 96 12:55:20 GMT
Links: << >>  << T >>  << A >>
In article <fliptronDKwrL4.2CK@netcom.com>
           fliptron@netcom.com "Philip Freidin" writes:

> To add to your entertainment, even if you figured out how to etch a plastic
> package without loosing power for even a few nanoseconds, and then E-beamed
> the device, what you would end up with is the Xilinx bitstream which is
> in itself an "encrypted" version of the design, for which their is NO 
> existing software tool that can decode the bitstream back into something
> more useable to a human (to my knowledge, which on this topic is not 
> minimal :-).

If you ever did manage to get at the Xilinx bitstream, (which given the
example you use is pretty unlikely), it is quite possible to reverse engineer
it into a schematic of Xilinx CLBs (configurable logic blocks).  It is very 
hard, but it can be done (by hand!). With a bit of trial and error you can 
deduce the format of Xilinx's bitstream.  This is all a bit academic....

-- 
 -----------------------------------------------------------------------------
| Andrew Morley, Design & Development, Trend Communications Ltd, High Wycombe.|
| email: andym@trend.demon.co.uk  Phone +44 1628-524977             Bucks, UK.|
 -----------------------------------------------------------------------------


Article: 2604
Subject: IIR FILTER
From: Laurent LE BOURHIS <lebourhl@esiee.fr>
Date: Wed, 10 Jan 1996 16:07:06 +0100
Links: << >>  << T >>  << A >>
I'm looking for projects about integrating an 10th order IIR FILTER on a
xC4005.

Thanks


Article: 2605
Subject: Re: Career value: VHDL or Verilog?
From: tgoodloe@adtran.com (Tony Goodloe)
Date: 10 Jan 1996 18:36:05 GMT
Links: << >>  << T >>  << A >>
In article <simond-1001961130140001@his-home.demon.co.uk>, simond@vchips.com (Simon J Davidmann) says:
Verilog vs. VHDL - IT DOESN'T MATTER! People have shipped products 
and made money using each. Learn one. Don't fret about the decision.
The hard part is understanding what HDLs are all about in general. 
Once you learn one, the other will come.

tony  


Article: 2606
Subject: Re: Career value: VHDL or Verilog?
From: GNEEC <krausrl@wkuvx1.wku.edu>
Date: 10 Jan 1996 21:04:08 GMT
Links: << >>  << T >>  << A >>
dfg




Article: 2607
Subject: Re: [q][Reverse Engineering Protection]
From: hbcsc388@csun.edu (eric schonning)
Date: 10 Jan 1996 21:22:51 GMT
Links: << >>  << T >>  << A >>
Rob-L (rob-l@superlink.net) wrote:

> When someone buys something, they should expect proper operation for some 
> time, but not forever.  If it can be repaired, great, but it can provide 
> value even if it fails later on.  That's not cheating the purchaser.

> With electronic components/assemblies, the manufacturer has configured 
> some materials for you, in order to perform some function you desire.  
> You pay them for the product, and you get that function for at least the 
> warranty period or some reasonable time for the type of device.

> So you make a protected chip, and make it to last some number of hours 
> minimum.  If it fails before then, it gets replaced free.  If it lasts 
> beyond its expected lifetime, that's free use of a product, which is a 
> benefit to the purchaser.  If a product is not used as intended and it 
> fails, or if it's tampered with and self-destructs, the purchaser eats 
> the loss.  That's the way it's always been.

Please warn all the members of these newgroups of any possible commerical
or any other products that may have your design in them so we don't by the
unrepairable crap you make.  I only hope that all who think like you are
miserably put out of business.  


Article: 2608
Subject: Re: Emulation for a wireless chip
From: <jasonf>
Date: 10 Jan 1996 21:51:54 GMT
Links: << >>  << T >>  << A >>
Dear Hsien-Ho Chuang,

Xilinx has had a university program for 10 years, almost since the
company's founding. 
We have the best programmable logic universtiy program available.  
For an overview, and to register to get further
access to our brochure on the web, please take a look at our website.
(The registration section is only open for accredited university students
such as yourself, professors, or university staff; not for commercial 
customers or general public.)

Main Xilinx site: http://www.xilinx.com/
University Program: http://www.xilinx.com/programs/univ.htm/

The registration portion of the university page is experiencing
technical difficulty but it should be resolved by January 11.

Xilinx offers significant discounts to universities on software and 
hardware as well as donations to those who have no budget 
(pending review of a donation proposal).
We also plan to have a university workshop in Taipei in the late spring
or early summer '96.

For any further questions about the Xilinx University Program, contact
Jason Feinsmith at xup@xilinx.com, or in the USA, tel: 408-879-4961.

Sincerely,
Jason Feinsmith
Xilinx University Program



Article: 2609
Subject: Transmogrifier C 3.1 - a C based hardware description language
From: drg@eecg.toronto.edu (Dave Galloway)
Date: 10 Jan 96 21:53:22 GMT
Links: << >>  << T >>  << A >>
I'm making a copy of release 3.1 of Transmogrifier C available for
anonymous ftp, on the host ftp.eecg.toronto.edu, in the directory
/pub/software/tmcc.
 
Transmogrifier C (or tmcc) is a compiler for a simple hardware description
language.  It takes a program written in a restricted subset of the
C programming language, and produces a netlist for a sequential circuit that
implements the program.  The netlist is intended for a Xilinx XC4000 series
FPGA, but there is some support for the Altera Flex 8000 FPGAs, and other
FPGAs, CPLDs and even ASICs could be used.

The compiler compiles and runs under:

	SunOS 4.1.X
	Solaris 2.4 using gcc
	Solaris 2.4 using SUN's C compiler

You will need your own copy of the Xilinx ppr and makebits programs.  The
compiler's output is compatible with both Xilinx XACT 4.31, and XACT 5.1.

The distribution includes the source for the tmcc compiler, a 9 page
programming manual and a few sample circuits written in tmcc.

WEB PAGE

The tmcc World Wide Web page has the URL:

http://www.eecg.toronto.edu/EECG/RESEARCH/tmcc/tmcc

WHO DID THIS ?

The Transmogrifier 1 (TM-1) is a field-programmable system consisting of FPGAs,
RAMs and programmable interconnect chips.  It was designed and built at
the Department of Electrical and Computer Engineering, University of
Toronto, by Dave Karchmer under the supervision of Jonathan Rose, Paul Chow,
David Lewis, and Dave Galloway.

Transmogrifier C has been used to produce circuits that run on the TM-1.
It was written by Dave Galloway.

IS THIS USEFUL ?

The compiler has been used by a handful of people.  It was used during
the summers of 1994/95 to produce several circuits that did graphics on LCD
screens.  The largest circuit was about 1200 lines of tmcc code, and fit
into four XC4010s.  The circuits work.

Tmcc is not a replacement for VHDL or Verilog for people who are serious
about producing a circuit design on time, and under budget.  It will have
bugs.

It may be interesting to someone who does know C, and wants to throw together
a circuit in a couple of days to investigate its properties, or get an upper
limit on the size or cycle time of a proposed design.

CHANGES FROM 3.0 to 3.1

Version 3.0 of tmcc was released in November, 1994.  Version 3.1 is better
in a number of ways:

Implemented more of the C language, and expanded the language definition:

- Implement these operators: +=, -=, <<=, >>=, &=, |= and ^=, ++, --
- Allow assignments in local variable declarations
- Allow declaration of function types and widths
- Allow portflags bits to be or-ed together
- Add PORT_PULLUP and PORT_PULLDOWN.

Produces smaller, faster circuits.  The 3 circuits in the examples directory
are now 15-29% faster, and 16-36% smaller than tmcc 3.0 could do:

- Use the clock enable input on XC4000 flip flops
- Use carry select adders and subtractors, unless -fno-carry-select
- Output circuit as simple gates, to give ppr and optimization tools more scope
- Improve multiplexor construction
- Assume that XC4000 flip flops start at 0
- Improve implementation of function return values

A number of bug fixes, many due to John Forrest of UMIST in Manchester, UK
and Michael Barnett of the University of Idaho:

- Fix syntax of return statement.
- Fix scope of enable input on busports
- Fix XNF output for busports
- Pre-define PORT_* with cpp
- Fix memory allocation bugs in makeffinputs()
- Fix order of include files in syntax.l
- Make makefile more portable
- Save the lca file, so that xdelay can be used
- Fix shift right when shift is greater than variable width
- Check width of function return values
- Check number of function arguments
- Check for assignments to input ports
- Fix output format so that XACT 5.X doesn't complain about it
- Fix usage message

Other changes:

- Add -dverbose, to give some information on the size and speed of the circuit
- Some support for the Altera Flex 8000 parts

BUG FIXES

We are interested in getting feedback from people who try tmcc.  If you
find a problem, fix a bug, or improve tmcc, please send me mail at the
address below.  If you try it and you like it, please tell us that too.
Unfortunately, we don't have a lot of time to work on tmcc so we can't
promise anything in the way of support.

	Dave Galloway, University of Toronto, drg@eecg.toronto.edu


Article: 2610
Subject: looking for free LATTICE ispLSI compiler
From: ROBERT <robe0929@eurobretagne.fr>
Date: 10 Jan 1996 22:06:16 GMT
Links: << >>  << T >>  << A >>
I am looking for a free compiler for pLSI and ispLSI from LATTICE.
Could you give me an answer :does it exist or not.
			
THANK YOU
Michel ROBERT
robe0929@eurobretagne.fr



Article: 2611
Subject: ECL PALs or FPGAs
From: sgh@wdl.loral.com (Steve Hoeft)
Date: Wed, 10 Jan 1996 12:33:16 -1100
Links: << >>  << T >>  << A >>
I am looking for vendors that make ECL PALs and/or FGPAs. My frequency
range is
100MHz to 500MHz and 500MHz to 1.2 Ghz.
Thanks

-- 
+------------------------------------------------------------------------+
Steve Hoeft           e-mail sgh@wdl.loral.com      This is my very
                                                    personal opinion!
Loral WDL             voice  (408)473-6479          
3200 Zanker Rd.       fax    (408)473-4093
San Jose, CA 95134


Article: 2612
Subject: Re: Need Re-programable VXI Module
From: Dan Blow <blow>
Date: 10 Jan 1996 23:43:50 GMT
Links: << >>  << T >>  << A >>
ganley@world.std.com (Timothy P. Ganley) wrote:
>Dan Blow <blow> wrote:
>
>>I have a need for a re-programable module to be used in the implementation of
>>VXI based test sets.  The module would need to accept program data from the VXI
>>interface and provide prewired addressing and data bus interfaces between the
>>module FPGA('s) and the VXI bus.  The remainder of the pins on the FPGA('s)
>>would be wired to connectors on the front of the module to be used in
>>transmiting to, or receiving data from the unit under test.  The module needs
>>to have about 128 I/O pins.
>
>>Does any one know of such a device, or would anyone be intrested in designing
>>and building a module of this type.  My current needs are for 3 to 5 modules.
>
>
>From the preceding description and the December 21 posting I assume
>that you are looking for a VXI Board with on-board connectors for
>reprogrammable (FPGA based) modules.
>
>I know of no vender that currently offers such a system.  I have
>experience designing systems similar to this and may be interested in
>building a module of this type.  Contact me so that your requirements
>can be further asessed.
>
>Tim Ganley
>ganley@world.std.com
>
Please send me your phone so that I can call you regarding these requirements.



Article: 2613
Subject: Re: Emulation for a wireless chip
From: stchen@cic02.cic.edu.tw (Sze-Tang Chen)
Date: 11 Jan 1996 02:02:02 GMT
Links: << >>  << T >>  << A >>
Chuang Hsien-Ho (eea80593@maddux.EE.NCTU.edu.tw) :
: We have a project, "A Baseband Chip Set for Digital Cellular Phone", in
: progress. We will soon finish the verilog coding. Now we want to prepare
: for the emulation step. We have about tens of thousands of gates, targeting
: on at least 6MHz.
: Being a academic project, we might not able to afford a complete commercial
: system. We plan to buy some RAM-based FPGAs(like XC4000 or ALTERA FLEX series),
: maybe some FPICs(like Aptix).
: Could you experienced persons give me some comments or suggestions? Or where
: can I get the detail information of these vendors?  Thanks a lot.

Hello,

You can contact CIC(Chip Implementation Center) directly to get some
information of FPGA vendors. CIC administers the university programs
of Xilinx and Altera in Taiwan, including the application of software
and technical supports. If you need buy some FPGA devices, you should
contact the local distributors of FPGA vendors.

Sze-Tang Chen,
Assistant Researcher,
Chip Implementation Center.
Tel: (035)773693*148
Email: stchen@mbox.cic.edu.tw



Article: 2614
Subject: Re: [q][Reverse Engineering Protection]
From: pkh@fantti.tky.hut.fi (Petri Havanto)
Date: 11 Jan 1996 08:21:19 GMT
Links: << >>  << T >>  << A >>
In article <821275994snz@fpga.demon.co.uk> David Pashley <david@fpga.demon.co.uk> writes:

> In article <PKH.96Jan10115036@fantti.tky.hut.fi>
>            pkh@alpha.hut.fi "Petri Havanto" writes:

>> "Somehow it seems to me that 'easy' is not exactly the right word. I

> The (Xilinx)bitstream was cracked long ago by NeoCAD, who made a business 


Yes, you're right. I should have thought about this, stupid of me...
I just wonder how the NeoCAD cracked the system. Did they analyze
designs and their bitstreams or did they study the silicon? 

By the way, what is happening with this NeoCAD thing at the moment?
After the buy-out, I mean.

All the best,
Petri


Article: 2615
Subject: place/route for LUT-based FPGA
From: Laurent Lemarchand <lemarch$univ-brest.fr>
Date: 11 Jan 1996 13:28:16 GMT
Links: << >>  << T >>  << A >>
Hello,

I'am looking for (electronically available if possible) papers on
placement and global routing phases of synthesis for LUT-based FPGA
of combinational/sequential circuits.

Thanks in advance for answers.

please mail answers to : lemarch@univ-brest.fr


L. Lemarchand

-------------------------------------------------------------------
Laurent Lemarchand                    PhD student
Universite de Bretagne Occidentale    e-mail: lemarch@univ-brest.fr
6 av. Le Gorgeu                       tel: +33 98 01 62 17         
29200 Brest - France                  fax: +33 98 01 69 80
-------------------------------------------------------------------



Article: 2616
Subject: Re: ECL PALs or FPGAs
From: kgold@watson.ibm.com (Ken Goldman)
Date: 11 Jan 1996 13:34:16 GMT
Links: << >>  << T >>  << A >>
sgh@wdl.loral.com (Steve Hoeft) writes:
> I am looking for vendors that make ECL PALs and/or FGPAs. My frequency
> range is 100MHz to 500MHz and 500MHz to 1.2 Ghz.

Last time I looked . . .

National and Cypress made a part that was similar enough that they
could be interchangable in some designs.  I don't think they had any
flip flops.

Phillips made a part that was 20V8'ish but single source.

-- 
Ken Goldman   kgold@watson.ibm.com


Article: 2617
Subject: Re: [q][Reverse Engineering Protection]
From: David Pashley <david@fpga.demon.co.uk>
Date: Thu, 11 Jan 96 15:48:30 GMT
Links: << >>  << T >>  << A >>
In article <PKH.96Jan11102120@fantti.tky.hut.fi>
           pkh@alpha.hut.fi "Petri Havanto" writes:

"> The (Xilinx)bitstream was cracked long ago by NeoCAD, who made a business 
"
"
"Yes, you're right. I should have thought about this, stupid of me...
"I just wonder how the NeoCAD cracked the system. Did they analyze
"designs and their bitstreams or did they study the silicon? 
"
I heard it was by examining designs and bitstreams. You change one 
bit, and see what the effect is. Then you change another bit...

"By the way, what is happening with this NeoCAD thing at the moment?
"After the buy-out, I mean.
"
Most of the people went to Xilinx, a few to AT&T. The Xilinx people 
are working on Xilinx support, and the AT&T folks on AT&T support - 
so no more universal place and route.

-- 
David Pashley                 



Article: 2618
Subject: What exactly does an FPGA do?
From: 3app@qlink.queensu.ca (Teknomage)
Date: 11 Jan 1996 16:41:49 GMT
Links: << >>  << T >>  << A >>
I'm not sure if I know what an FPGA does and it's applications.
>From what I've been able to deduce, it's somewhat analogous to 
a fully programmable CPU, microcode and all, sort of like a 
RAM-based PAL...  How correct am I?  If this is so, have any 
groups been involved in designing an FPGA-based multiprocessor 
bus architecture? - Instead of a shared set of physical wires, 
something more like a modern telecom network with routing 
intelligence.  Any information available online?

Thanks!

Andrew.

--
--
     -------------------------------------------------
     >>>  Adrift amongst the blooms of knowledge,  <<<
     >>>  Swept along by the tides of change...    <<< 
     -------------------------------------------------

Real Name:  Andrew Plumb, VE3SLG
E-mail:  3app@Qlink.QueensU.CA
Web:  http://www.io.org/~tekmage/


Article: 2619
Subject: Lattice isp Starter Kit and 3 ispLSI1016-80LJ Devices For Sale
From: Jeffrey Yuan <yuan@phoenix.princeton.edu>
Date: 11 Jan 1996 20:26:17 GMT
Links: << >>  << T >>  << A >>
For Sale

Lattice Semiconductor's isp-Starter Kit
     and 
   3 extra ispLSI1016-80LJ CUPL/FPGA Devices (never used)

The kit includes samples of the following devices:
      ispLSI1016-60LJ (4 total)
      ispGAL22V10B-15LJ
      ispGDS14-7J
All unprogrammed and never used.

Software for IBM PC/Windows 3.11
      pDS1016-PC Design Development Software for ispLSI1016
      ispGAL22V10 Download Software
      ispGDS Compiler and Download Software
      ispCODE ANSI C source programming download routines

And a ispDOWNLOAD cable and all the literature.  A letter of transfer of
the license is included.

$80 + shipping

Contact Jeff Yuan at 609-258-5939 or email yuan@phoenix.princeton.edu


Article: 2620
Subject: Job Openings - Reconfigurable Computing
From: annapmicro@aol.com (AnnapMicro)
Date: 12 Jan 1996 01:14:07 -0500
Links: << >>  << T >>  << A >>
ENGINEERING CAREER OPPORTUNITIES 
IMMEDIATE OPENINGS
for
WILDFIRE, FAMILY OF XILINX FPGA BASED RECONFIGURABLE COMPUTING ENGINES
DESIGN ENGINEERS

WILDFIRE SOFTWARE ENGINEERS

Annapolis Micro Systems, Inc., a high tech R&D and electronic product
development firm, has developed WILDFIRE, a revolutionary new computer
architecture that uses Xilinx FPGA's as parallel processing elements.
Annapolis Micro Systems, Inc encourages initiative and creativity and
offers opportunities for continued development of analytical and technical
ability. 
        
QUALIFICATIONS
Requires BSCE/CS; Expertise programming in a multi-threaded environment
such as UNIX, OS/2 or multi-threaded Windows; familiarity with multiple
operating systems; C and C++.  Motorola 68000 embedded programming a plus.


JOB DESCRIPTION
Software engineers will assist in the development of multi-platform tools
and applications for the WILDFIRE Reconfigurable Computing Engine product
line.

JOB LOCATION INFORMATION 
Annapolis Micro Systems, Inc. is located in Annapolis, Maryland. Annapolis
is an historic city located on the Chesapeake Bay and within easy driving
distance of Washington D.C. and Baltimore.  Annapolis is a sailing capital
and offers a rich variety of cultural experiences. 


To apply send resume and copy of recent transcripts to:
Annapolis Micro Systems, Inc.
Attn:  Betsy Jenkins, HR/Software Engineer
190 Admiral Cochrane Drive, Suite 130
Annapolis, MD  21401-7386

(410) 841-2514   (301) 970-2672   FAX:  (410) 841-2518

        
**************************************************************************
************

WILDFIRE HARDWARE DESIGN ENGINEERS


QUALIFICATIONS 
Requires BSEE/CE/Physics. Must be familiar with digital design techniques
and principles.  Experience with VHDL, FPGA design, PCB design a plus.
Desire to be involved with challenging hardware design projects and work
with state of the art equipment and technologies.

JOB DESCRIPTION
Annapolis Micro System's hardware design group specializes in
microprocessor based board level design, ASIC design and Xilinx FPGA
design. We are seeking hardware designers to work on a variety of
electronic product designs including image processing and communications
equipment.  AMS engineers at all levels are directly involved in hands on
design work.  The development of leadership responsibilities is
encouraged.

JOB LOCATION INFORMATION 
Annapolis Micro Systems, Inc. is located in Annapolis, Maryland. Annapolis
is an historic city located on the Chesapeake Bay and within easy driving
distance of Washington D.C. and Baltimore.  Annapolis is a sailing capital
and offers a rich variety of cultural experiences. 
 To apply send resume and copy of recent transcripts to:
Annapolis Micro Systems, Inc.
Attn:  Betsy Jenkins, HR/Hardware Engineer
190 Admiral Cochrane Drive, Suite 130
Annapolis, MD  21401-7386
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Article: 2621
Subject: Re: What exactly does an FPGA do?
From: 3app@qlink.queensu.ca (Teknomage)
Date: 12 Jan 1996 15:49:35 GMT
Links: << >>  << T >>  << A >>
Well, thanks for the responses (via E-mail).  My initial 
questions have been answered...

Can anyone suggest any reasonable books about FPGAs, their 
interfacing, applications, implementations?

Teknomage (3app@qlink.queensu.ca) wrote:
: I'm not sure if I know what an FPGA does and it's applications.
: From what I've been able to deduce, it's somewhat analogous to 
: a fully programmable CPU, microcode and all, sort of like a 
: RAM-based PAL...  How correct am I?  If this is so, have any 
: groups been involved in designing an FPGA-based multiprocessor 
: bus architecture? - Instead of a shared set of physical wires, 
: something more like a modern telecom network with routing 
: intelligence.  Any information available online?

Thanks in advance!

Andrew.

--
--
     -------------------------------------------------
     >>>  Adrift amongst the blooms of knowledge,  <<<
     >>>  Swept along by the tides of change...    <<< 
     -------------------------------------------------

Real Name:  Andrew Plumb, VE3SLG
E-mail:  3app@Qlink.QueensU.CA
Web:  http://www.io.org/~tekmage/


Article: 2622
Subject: PCI-interface chip from PLX
From: thebert@tom.on-luebeck.de (Thomas Ebert)
Date: 12 Jan 1996 20:47:00 +0200
Links: << >>  << T >>  << A >>
Hi there !

We are about to realize an PCI interface with a PLX 9060 device.
Does anyone has any kind of experience with those chips ? If you know
some bugs or "features" ;-) about it please let me know.
Another point is that I am searching for a PCI interface chip which
includes a DRAM controller. Any ideas ?
I am not shure if I met the right newsgroup, if not I apologize for this.

! This is a copy of my earlier posting because my connectivity was pretty
! bad the last week and I lost the news in between - so please repost
! your ideas  - thank you -

Cheers Tom


## Thomas Ebert  e-mail: thebert@on-luebeck.de  Tel.:+49(0)451 391322 ##


Article: 2623
Subject: JOB- Linecard FPGA/ASIC Designer
From: fsihunter@aol.com (FSI HUNTER)
Date: 12 Jan 1996 15:35:41 -0500
Links: << >>  << T >>  << A >>
Linecard FPGA/ASIC  Designer
First Search Inc.
6584 N. Northwest Highway
Suite AC
Chicago, Illinois 60631

Contact: Al Katz
Phone: 312 774-0001
Fax: 312 774-5571
Business Line: Cellular, Wireless, Multi-Media, Datacommunications and
Telecommunications Executive Search. E-mail to fsihunter@aol.com

Description: 
We are looking for a candidate for our retained client who will be
involved
in  the designing of  "High Speed Internet Access" products. In this
position 
you would be involved in the linecard design. Your main responsibility
will be
designing the "glue logic" and packet processor circuitry.  The design
task
also includes gate-level design, simulation, timing verification and lab
debugging
of the prototype system.    
 
Qualifications:
Ideal Candidates will have:1) 5+ years of digital design 2) At least 2
years on 
datacommunications or telecommunications equiptment 3) Have hands-on 
experience with Unix or PC-based EDA tools (e.g., Viewlogic) 4) Be
familiar
with modem technology, DSP and low power design techniques.
 
For IMMEDIATE consideration fax, mail or E-mail resume to above location
ATTENTION - Al Katz, Suite AC.  Our preferred method is fax, if resumes 
are sent e-mail they are to be sent in plain ascii text format.

SPECIAL NOTE - Due to the amount of responses we get we will only contact
candidates who are qualified for this assignment, but we will notify you
as to other
assignments as your qualifications match up.

Company:     

First Search Inc, was founded in 1984 specializing in Executive search
primarily 
for Engineering, MIS, Operations, Technical, Sales and Marketing
personnel.  
Each recruiter has 15+ years of search expertise.  Our clients include
domestic 
and international companies representing the Cellular, Wireless,
Multi-Media,
Datacommunications and Telecommunications industries.

First Search Inc. recruits on both permanent and temporary (contract)
assignments.  
All fees are employer paid.

Our exact specializations include the following -

*  Cellular
*  PCS
*  Wireless
*  Paging
*  ATM
*  SONET
*  Broadband
*  Fiber-to-the-curb
*  Intelligent Networks
*  Advanced Intelligent Networks
*  Network Management
*  Multi-Media

Salary: $70 to 90K, plus a stock equity plan upon hire.
Location: Northern California


Article: 2624
Subject: CA-ATM/MUX Linecard FPGA/ASIC Designer
From: fsihunter@aol.com (FSI HUNTER)
Date: 12 Jan 1996 16:42:20 -0500
Links: << >>  << T >>  << A >>
ATM/Mux Linecard FPGA/ASIC  Designer
First Search Inc.
6584 N. Northwest Highway
Suite AC
Chicago, Illinois 60631

Contact: Al Katz
Phone: 312 774-0001
Fax: 312 774-5571
Business Line: Cellular, Wireless, Multi-Media, Datacommunications and
Telecommunications Executive Search. E-mail to fsihunter@aol.com

Description: 
We are looking for a candidate for our retained client who will be
involved
in  the designing of  "High Speed Internet Access" products. In this
position 
you would be involved in the ATM/Mux linecard design. Your main
responsibility 
will be the design of the multiplexer that mux's and demux's packet
traffic. Work 
with the other designers as to the defining of the interface between the
respective
subsystems. The design task also includes gate-level design, simulation,
timing
verification and lab debugging of the prototype system.    
 
Qualifications:
Ideal Candidates will have:1) 7+ years of digital design 2) At least 2
years 
of experience designing high speed switching or muxing  3) Have hands-on 
experience designing PLD/FPGAs using Unix or PC-based EDA tools (e.g., 
Viewlogic) 4) Be familiar with ATM and packet technology. Note: This
client
will look at Canadian's and help bring them down.
 
For IMMEDIATE consideration fax, mail or E-mail resume to above location
ATTENTION - Al Katz, Suite AC.  Our preferred method is fax, if resumes 
are sent e-mail they are to be sent in plain ascii text format.

SPECIAL NOTE - Due to the amount of responses we get we will only contact
candidates who are qualified for this assignment, but we will notify you
as to other
assignments as your qualifications match up.

Company:     

First Search Inc, was founded in 1984 specializing in Executive search
primarily 
for Engineering, MIS, Operations, Technical, Sales and Marketing
personnel.  
Each recruiter has 15+ years of search expertise.  Our clients include
domestic 
and international companies representing the Cellular, Wireless,
Multi-Media,
Datacommunications and Telecommunications industries.

First Search Inc. recruits on both permanent and temporary (contract)
assignments.  
All fees are employer paid.

Our exact specializations include the following -

*  Cellular
*  PCS
*  Wireless
*  Paging
*  ATM
*  SONET
*  Broadband
*  Fiber-to-the-curb
*  Intelligent Networks
*  Advanced Intelligent Networks
*  Network Management
*  Multi-Media

Salary: $70 to 90K, plus a stock equity plan upon hire.
Location: Northern California




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