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Messages from 1050

Article: 1050
Subject: VHDL -> Xilinx synthesis
From: msnook@armltd.co.uk (Mark Snook)
Date: 21 Apr 1995 08:32:46 GMT
Links: << >>  << T >>  << A >>
I am currently using the Compass synthesis tools including ASYL FPGA
optimiser, to target my VHDL at a 3000L series Xilinx part. My problem
is that somewhere along the way, what I thought were outputs get
turned into inouts, i.e. bi-directional buffers. This has two effects:

1. When I try and generate a timing annotated VHDL model using the
VBAK tool from Topdown, my entity doesn't match the original because
some outs are now inouts.

2. When I expect an output FF I get an OBUF that is driven from a
output FF of another signal that has been fed back in. This will give
skew across what I expected to be simultaneously switching
outputs. The optimiser was set to optimise for speed, so this doesn't
make sense.

By way of an example:

        if ((clk = '1') and clk'event) then
          if (siga = '1') then  
            sigb <= "0011";
          else
            sigb <= "1100";
          end if;
        end if;

when synthesised sigb(1) and sigb(2) are output FFs, but sigb(0) is
sigb(1) fed back in through an IBUF and out again through an
OBUF. Similarly for sigb(3) and sigb(2). I can see that this is
logically correct, but I can't see how to write the VHDL to prevent it
happening.

Has anyone any suggestions?

Mark Snook

mark.snook@armltd.co.uk


Article: 1051
Subject: Re: Neocad merges with Xilinx
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 21 Apr 1995 13:07:03 GMT
Links: << >>  << T >>  << A >>
> Certainly the Neocad takeover is inconvenient, but AT&T is 
> not in the same position that Motorola seems to be in.

Is anyone from Motorola out there?  

Please comment.


---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 1052
Subject: subscription
From: cemchp@faces.ula.ve (Charles Paez - CEMISID - ULA)
Date: Fri, 21 Apr 1995 13:13:12 GMT
Links: << >>  << T >>  << A >>
please subscribe me in the news group

cemchp@zeus.faces.ula.ve

Charles R Paez
Cemisid-ULA





Article: 1053
Subject: Re: VHDL -> Xilinx synthesis
From: will@fpga.demon.co.uk (William White)
Date: Fri, 21 Apr 1995 17:14:01 +0000
Links: << >>  << T >>  << A >>
In article <MSNOOK.95Apr21093246@sun61.armltd.co.uk>
           msnook@armltd.co.uk "Mark Snook" writes:

"I am currently using the Compass synthesis tools including ASYL FPGA
"optimiser, to target my VHDL at a 3000L series Xilinx part. My problem
"is that somewhere along the way, what I thought were outputs get
"turned into inouts, i.e. bi-directional buffers. This has two effects:
"
<snip>

I synthesized your VHDL for Xilinx 3000 target using ASYL+ v3.2.

Inspection of the .XNF showed that your problem was not duplicated.

I can only guess that this is a peculiarity of your synthesis tool.

Hope this helps.

-- 
Will White                    <
 ------------------------  <  <  <  ---------- Email: will@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| *The EDA Source*         <  <  <               Fax: +44 1280 705196      |
 ---------------------------  <  ------------------------------------------


Article: 1054
Subject: Free WinEDA / PLD Con Evening Discussion
From: jcooley@world.std.com (John Cooley)
Date: Fri, 21 Apr 1995 18:17:50 GMT
Links: << >>  << T >>  << A >>
         EDA After Hours with Richard Goering and Rita Glover
         ----------------------------------------------------

WinEDA '95 is offering a free, open discussion session for all (Windows &
UNIX based) EDA tool users on Wednesday, April 26, 6:00 - 7:30 p.m.,
Santa Clara Convention Center.  (There are two conferences going on at
this time: WinEDA '95 and PLD Con '95 -- both of which you have to pay to
enter -- this evening discussion is an open, free event.)

This is meant to be a user oriented session -- enjoy a beer and "speak out"
to a panel of EDA vendors, advocates, and other users about what you really
need and want in Windows-based EDA tools today and in the future.

  Moderators for the Evening are:
    Richard Goering of EE Times
    Rita Glover of EDA Today

  Session Chairman:
    Jeff Edson, Vice President, Intergraph Electronics

  EDA Panelists:
    Mark Miller, Vice President, Escalade
    John Birkner, Vice President, QuickLogic
    David Kohlmeier, Director of Marketing, Data I/O

  EDA Advocates and Users:
    John Cooley, Consultant and User Advocate
    Sean Murphy, President, Leader Murphy, Inc.
    Adam Levinthal, Director of Engineering, Silicon Gaming          


          WinEDA '95,  Santa Clara Convention Center
         Wednesday Evening, April 26, 6:00 - 7:30 p.m.

Make Richard Goering's "Top-Ten" list of issues and questions from users!
Send your provocative questions or burning issues about Windows-based EDA
tools to Richard Goering at "edausers@cmp.com".  The "Top-Ten"  list
will be the starting point for lively discussion!

*Session open to all users of EDA tools.  Need not be registered for 
conference to attend.  For information or a complete program guide for
WinEDA'95 and PLDCon'95, call 1-800-839-2429.

                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3349 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1055
Subject: Re: See Newborn Lambs Plus Meet The Real Aart & Harvey
From: jcooley@world.std.com (John Cooley)
Date: Fri, 21 Apr 1995 18:58:03 GMT
Links: << >>  << T >>  << A >>
>         Come See Newborn Lambs Plus Meet The "Real" Aart & Harvey!
>             Holliston Poor Farm Open House (Noon to 4:30 PM)
>                   Earth Day, Saturday, April 22nd, 1995
>
>  If you're part of the greater New England electronic design engineering
>  community (or just visiting), I'm inviting you and your family to the
>  Holliston Poor Farm in Holliston, Massachusetts to see 18 sheep and 12
>  newborn lambs plus two goats...


 Quick follow-up on tommorrow's Holliston Poor Farm Earth Day:

   - Although the farm has 14 acres of pastures & woodlands, please DO NOT
     bring you family dog.  Dogs, whether they be angry Doberman pinschers
     or timid teacup Chihuahuas, all have the inresistible urge to chase
     and chomp on the jugular veins of of fat, grazing ungulates.  (Yes,
     your "Fidoux" my be a mouse around people -- but get him around sheep
     and he'll instinctively turn into "Cujo" with bloodlust in his eyes.)

   - This is a rain or shine event.  Bring an umbrella or rain coat if
     it's looking a little like rain.  (Either way, the sheep, goats, my
     girlfriend and I will be there!)

   - Yes, you can bring friends, etc. -- this is a drop-in/see-what-you-
     want-to-see/drop-out *social* gathering.  If you're a Technonerd who
     has no life beyond technology, you will be asked to create an
     imaginary social life to reference when interacting with the guests
     or (if failing this) to leave.  No Engineering-Speak Allowed!

   - What inspired this local event was going into Boston's Earth Day only
     to find faceless crowds, cops, no parking and lots of left over garbage
     on the streets.  You will be expected to bring home whatever garbage
     you may generate.
                           - John Cooley
                             Part Time EDA Consumer Advocate
                             Part Time Sheep & Goat Farmer
                             Full Time ASIC, FPGA & EDA Design Consultant

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3271 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 1056
Subject: Xilinx Device Information
From: geocaris@cse.ucsc.edu (Tom Geocaris)
Date: 21 Apr 1995 19:24:21 GMT
Links: << >>  << T >>  << A >>
Hello All,

I am writing a place and route program for Xilinx FPGA's, for my Masters
Thesis at UC Santa Cruz. To make my program general enough, I need Xilinx
device information, such as the IO pad placement geometry. At the
present time, all I can do is run Xact to visualy see the die layout.
In other words, I need to be able to map the symbolic CLB/IOB names in
the LCA file to an aproximate geometric location on the die. I could
create my own database by running Xact on all the devices supported, but I
don't want to. If anybody knows if such information is available I would
apreciate it.

Thanks in advance.

Tom Geocaris   (geocaris@cse.ucsc.edu)




Article: 1057
Subject: Is anybody using FPGA's to do PCI interfaces?
From: gbchoy@nachos.engr.ucdavis.edu (Garett B Choy)
Date: 21 Apr 1995 20:37:40 GMT
Links: << >>  << T >>  << A >>
Oh well, I'll type it again:

Is anybody using FPGA's to do PCI interfaces?  If so, which
one's?  Any part recommendations and/or horror stories?

Garett


Article: 1058
Subject: GATRAN - Retargetting tool
From: ast@actcom.co.il (Gideon Amir)
Date: Sat, 22 Apr 1995 09:44:59 GMT
Links: << >>  << T >>  << A >>
Has any of you used GATRAN?  I am looking for a quality tool to retarget
FPGA's (XILINX and ALTERA primarily) to ASIC libraries (I use Chip 
Express and LSI Logic.   I can easily map LSI to Chip, so that a tool 
that supports LSI is fine).  Please don't send me to Synopsis again.

Viewlogic is now offering GATRAN.   I'd like to know if it is any good.

Thanks for your inputs.



Article: 1059
Subject: anyone using 4025 Xilinx??
From: rossr@tcs.com (rossr)
Date: 22 Apr 1995 18:43:51 GMT
Links: << >>  << T >>  << A >>
Hi I would like to know if anyone out there is using 4025 FPGA's
   I just got the s/w data and speed files to load into XACT 5.1
   my next problem is to getting parts from xilinx, has anyone had
   problems getting parts?? or at least got parts??.

   RR.
 


Article: 1060
Subject: SIS (where do I find it)
From: bjrosen@aol.com (Joshua Rosen)
Date: Sat, 22 Apr 1995 16:01:12 -0500
Links: << >>  << T >>  << A >>
In which package is Berkeley's SIS tool located. I can't find it in the
Octtools package, is it there or somewhere else?

Thanks


Article: 1061
Subject: Re: Need "fusemap" information from vendor, likely?
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 23 Apr 1995 11:46:22 GMT
Links: << >>  << T >>  << A >>
In article <D6y3Hn.GtJ@undergrad.math.uwaterloo.ca> Peter D. Gray,
pdgray@undergrad.math.uwaterloo.ca writes:
>I want to write my own programs to "route and place" for FPGAs. This is
>for my own little project, not as another HDL compiler.  In
>particular, I've been looking at the ALTERA Flex 8000 chips, but at
>this stage I can still choose anything (must be SRAM based).
>
>The question is this: Can I, as a nobody, get the required information
>from the manufacturer so that I can generate the JDEC files/fusemaps
>(whatever you want to call them) so that I can program these chips
>without using their software? I would be willing to sign an NDA
>(non-disclosure agreement) but not pay money.
>
I recently expressed interest in the JEDEC map for Flexlogic 780s - once
Intel and now Altera. The reason was two fold:

* I did not trust the PLDShell tool - it turns out that stating
CMOS_LEVEL or TTL_LEVEL as options has no effect. I discovered this by
comparing the output files. I wanted to explicitly enable the
compatability pullups on unused inputs - to see if this removed the need
for externally pulling them up.

* I have a simulator which can simulate PLDs if you can describe the
JEDEC fuse map.

The basic reply was that it is commercially sensitive data, and only
available for companies with whom Altera have signed a software devopment
agreement. 

If you want to play around, though, my guess is that reverse engineering
the Xilinx lca format is probably possible - make some changes in the
layout editor and compare the results. [In Europe this is perfectly
legal, not sure elsewhere].

John

_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 1062
Subject: Lattice low-cost start kit
From: herb@case373.demon (Herbert Larbie)
Date: 23 Apr 1995 12:56:02 +0100
Links: << >>  << T >>  << A >>
23/4/95

I thunking about checking out the Lattice low-cost starter kit isp-sk, could
anyone who has been using it relay their experience to me please.

Thanks in advance.

Herbert Larbie

Forgive the typos.


Article: 1063
Subject: Re: Intel Flex Download Cable
From: John Forrest <jf@ap.co.umist.ac.uk>
Date: 23 Apr 1995 13:56:18 GMT
Links: << >>  << T >>  << A >>
In article <3mi5q1$99m@jazzmin.vnet.net> David Van den Bout,
devb@jazzmin.vnet.net writes:
>1. Connect a male DB-25 to a 26-pin socket.  Pin 26 of the socket
>   remains unconnected.  The DB-25 goes to the parallel printer port
>   while the 26-pin socket connects to a 13x2 header on the EPX780 board.
>2. Connect pin 2 of the header through two 7414 inverters to the TCK
>   pin of the EPX780.  The 7414 cleans up the clock signal.
>3. Connect pin 3 to the TMS input pin of the EPX780.
>4. Connect pin 8 to the TDI input pin of the EPX780.
>5. Connect pin 11 to the TDO output pin of the EPX780.
>6. Connect pins 9 and 12 of the header together so the downloading
>   software can detect the presence of the cable.
>7. Ground header pins 18 through 25.
>
>
This may work but it is not the equivalent of the Intel cable. The cable
itself has a linedriver IC, a load of 330R resistors (line termination?),
and a diode - never sure what for.

The downloader board in the PLDShell manual seems to come fairly close. I
would recommend adapting the above with the info there.
_____________________________________________________________
Dr John Forrest           Tel: +44-161-200-3315
Dept of Computation       Fax: +44-161-200-3321
UMIST                  E-mail: jf@ap.co.umist.ac.uk
MANCHESTER M60 1QD
UK


Article: 1064
Subject: (none)
From: cj@wizard-slip.caltech.edu (Craig Jin)
Date: Mon, 24 Apr 1995 07:34:49 GMT
Links: << >>  << T >>  << A >>
Comment for FCCM '95 Attendees:

The issue of mainstreaming FCCM's was brought up for discussion.
In this regard, I would like to re-iterate a point made by an attendee:

A twelve year-old interested in computing several years ago (a generation
ago?) may have played w/ TTL parts and the like. Now these same kids
are going into software programming. Why? Open up a calculator and you'll
find one chip inside -- boring and uninformative. Playing w/ hardware 
is going out of fashion??

Point is: you can't pop into an electronics store and buy a FPGA and the
tools to play w/ it cheaply. What does a XC4002 cost ... a few bucks. 
What does the software cost ... 

When it becomes possible to walk into say, radio-sh***, and come out
$5.00 poorer but w/ a basic FPGA and tools to build things w/ it on the
family PC ... might things not be different?

Why isn't there a simple radio-s**** FPGA kit that can be bought for
a couple dollars? No market ... maybe or maybe NOT ...

/craig jin cj@wizard-slip.caltech.edu


Article: 1065
Subject: Re: (none)
From: dh@fncrd7.fnal.gov (don husby)
Date: 24 Apr 1995 13:31:09 GMT
Links: << >>  << T >>  << A >>
cj@wizard-slip.caltech.edu (Craig Jin) writes:
> A twelve year-old interested in computing several years ago (a generation
> ago?) may have played w/ TTL parts and the like. Now these same kids
> are going into software programming. Why? Open up a calculator and you'll
> find one chip inside -- boring and uninformative. Playing w/ hardware 
> is going out of fashion??
>
> Point is: you can't pop into an electronics store and buy a FPGA and the
> tools to play w/ it cheaply. What does a XC4002 cost ... a few bucks. 
> What does the software cost ... 

While I agree with your conclusion (the world needs a hacker-friendly
entry into FPGA programming), I disagree with your premises:

1) I think the number of kids becoming hardware hackers has probably 
increased since I was a kid.  The number of kids doing sotware hacking
is much greater, but I don't think this draws kids away from hardware.

2) Yes it's difficult to get into FPGAs, but there are tons of 
interesting chips out there: way more than when I was a kid trying to 
build computers out of TTL chips.  You can buy a $10 microcontroller 
that can do just about anything an FPGA can do at slow speeds.  You 
can buy PALs, A/D, D/A converters, speech synthesizers, music 
synthesizers...  and you have access to a powerful computer to 
interface to and develop your software.  Who could ask for anything 
more (except maybe for the FPGA thing)?


Article: 1066
Subject: Re: SIS (where do I find it)
From: niranjan@vlsi45 (Niranjan Cooray)
Date: 24 Apr 1995 13:43:06 GMT
Links: << >>  << T >>  << A >>

In article <bjrosen-2204951601120001@bjrosen.tiac.net>, bjrosen@aol.com (Joshua Rosen) writes:

|>In which package is Berkeley's SIS tool located. I can't find it in the
|>Octtools package, is it there or somewhere else?
|>
|>Thanks
|>

Berkeley SIS tool is available for anonymous ftp from:
ftp://ic.eecs.berkeley.edu/pub/Sis

It does'nt come with the octtools pkg, but having the octtool pkg when you
compile SIS, will give you added features in SIS.

Hope this helps. 


-- Niranjan

------------------------------------------------------------------------------
Niranjan Cooray	     	     E-mail (Internet): niranjan@nuvlsi.coe.neu.edu
ECE Department			                niranjan@splinter.coe.neu.edu
Northeastern University	
Boston, MA 02115

      HREF="http://www.ece.neu.edu/personal/niranjan/niranjan.html"
------------------------------------------------------------------------------


Article: 1067
Subject: fpga design advantages
From: harihara@sunburn.eng.usf.edu (Shankar Hariharan (EE))
Date: 24 Apr 1995 15:35:39 GMT
Links: << >>  << T >>  << A >>


	hi,
		I am doing a research on the studying the advantages of implementing application specfic archtectures on FPGA's. I would like to hear ur view point on this issue. Any pointers in this direction would be greatly appreciated. 

	I promise to  post the summary of the reply after compilation.

H.Shankar.
-- 
*************************************************************************************

      _/    _/   _/_/_/_/   _/_/_/_/   		  HARIHARAN , SHANKAR
     _/    _/   _/         _/           	  2301, ABERDEEN CT, #A1,
    _/    _/   _/_/_/_/   _/_/_/    	      	  TAMPA  FL-33612
   _/    _/         _/   _/        	 
  _/_/_/_/   _/_/_/_/   _/        	    	  PHONE : 813-979-9260.
						  OFFICE PHONE: 813-974-2858.
					 
*************************************************************************************
--
*************************************************************************************

      _/    _/   _/_/_/_/   _/_/_/_/   		  HARIHARAN , SHANKAR
     _/    _/   _/         _/           	  2301, ABERDEEN CT, #A1,


Article: 1068
Subject: Re: (none)
From: cburns@crl.com (Charlie Burns)
Date: 24 Apr 1995 09:29:54 -0700
Links: << >>  << T >>  << A >>
In article <1995Apr24.073449.15424@super.org> cj@wizard-slip.caltech.edu (Craig Jin) writes:
>When it becomes possible to walk into say, radio-sh***, and come out
>$5.00 poorer but w/ a basic FPGA and tools to build things w/ it on the
>family PC ... might things not be different?
>
>Why isn't there a simple radio-s**** FPGA kit that can be bought for
>a couple dollars? No market ... maybe or maybe NOT ...

I bought an epXboard from XESS for less than $200 including the book.
It comes with the PLD shell software from intel, a FLEXlogic NXF780-15
with a little circuit board and a cable that goes to your PC printer
port.

It's not $5.00 but it's pretty fun and I'm happy with it.

Charlie

ps: I have nothing to with XESS, I'm just a happy customer.
(You can reach xess at devb@vnet.net).

`


Article: 1069
Subject: Re: (none)
From: wirthlim@fpga.ee.byu.edu (Michael J. Wirthlin)
Date: 24 Apr 1995 11:44:54 -0600
Links: << >>  << T >>  << A >>

In article <1995Apr24.073449.15424@super.org>, cj@wizard-slip.caltech.edu (Craig Jin) writes:
|> Comment for FCCM '95 Attendees:
|> 
|> The issue of mainstreaming FCCM's was brought up for discussion.
|> In this regard, I would like to re-iterate a point made by an attendee:
|> 
|> A twelve year-old interested in computing several years ago (a generation
|> ago?) may have played w/ TTL parts and the like. Now these same kids
|> are going into software programming. Why? Open up a calculator and you'll
|> find one chip inside -- boring and uninformative. Playing w/ hardware 
|> is going out of fashion??
|> 
|> Point is: you can't pop into an electronics store and buy a FPGA and the
|> tools to play w/ it cheaply. What does a XC4002 cost ... a few bucks. 
|> What does the software cost ... 
|> 


There is an inexpensive FPGA prototyping board with free tools available from
XESS corporation. It is based on the old Intel Flex FPGA. The tools can be
downloaded via ftp (PLDasm). I don't know what it costs, but for ~$150 you can
get a book and a demo board with the FPGA. I do not think it is a very big FPGA,
but it is probably a good way to learn digital design.
-- 
Michael J. Wirthlin
Brigham Young University - Electrical Engineering Department
Reconfigurable Logic Laboratory (801) 378-7206


Article: 1070
Subject: Sunrise ???
From: "Terry E. Koontz" <tkoontz@uncc.edu>
Date: 24 Apr 1995 18:38:48 GMT
Links: << >>  << T >>  << A >>

Viewlogic recently add ViewTest to their Powerview product line.

ViewTest is based on Sunrise 2.0 software (their words)

Does anyone have an address and telephone number for Sunrise.

Terry Koontz
UNCC

tkoontz@uncc.edu


Article: 1071
Subject: AD for Training
From: suzanne@world.std.com (suzanne M southworth)
Date: Mon, 24 Apr 1995 21:49:24 GMT
Links: << >>  << T >>  << A >>
Widman Associates offers training classes on the Hardware Description
Language and Synthesis Methodology Training.

VHDL---Verilog---Verilog vs. VHDL---Design for Synthesis (Verilog or VHDL).
PLI--C++

If you book a Verilog or VHDL class for more than ten students, we will
give you the Design for Synthesis class for free.

To obtain a course outline; please send us your fax#, and or company address,
to: Suzanne@world.std.com


Thanks!

The staff at Widman Associates



Article: 1072
Subject: Re: Sunrise ???
From: pn@anuxt.mv.att.com (a.palmieri)
Date: Tue, 25 Apr 1995 03:04:27 GMT
Links: << >>  << T >>  << A >>
In article <3ngr7o$5fb@news.uncc.edu>,
Terry E. Koontz <tkoontz@uncc.edu> wrote:
>
>Viewlogic recently add ViewTest to their Powerview product line.
>
>ViewTest is based on Sunrise 2.0 software (their words)
>
>Does anyone have an address and telephone number for Sunrise.
>
>Terry Koontz
>UNCC
>
>tkoontz@uncc.edu


If I am not mistaken, ViewLogic has not continued with the addition
of ViewTest. I was initially making it part of their package,
however, there were many difficulties with the intergration. So
they were moving back to the stand alone Sunrise package.
(ViewLogic purchased Sunrise as it did many other co.s)

Tony



Article: 1073
Subject: Re: Is anybody using FPGA's to do PCI interfaces?
From: murray@src.dec.com (Hal Murray)
Date: 25 Apr 1995 07:05:01 GMT
Links: << >>  << T >>  << A >>
We've used Xilinx 3190 for config and misc target (PIO) and a 3195 for
initiator (DMA).  Two chips on a card connecting to the PCI bus is a no-no
so we used a DEC 21050 PCI-PCI bridge chip.  Since the "bus" on the board
is only 2 inches long, we used the 10 ns normally allocated to let the
bus settle as additional setup time for the 3190 and 3195.  (The 3195 is
working pretty hard to cooperate with the control logic on the other side.)

We have another board with the PCI-PCI bridge chip and a Xilinx 4xxx.  I haven't
worked with it.  I don't think it has done any initiator activity yet, but it
should work.


Article: 1074
Subject: Re: Sunrise ???
From: Meryem.Marzouki@imag.fr (Meryem Marzouki)
Date: 25 Apr 95 07:05:11 GMT
Links: << >>  << T >>  << A >>
"Terry E. Koontz" <tkoontz@uncc.edu> writes:

>Viewlogic recently add ViewTest to their Powerview product line.

>ViewTest is based on Sunrise 2.0 software (their words)

Sure : Sunrise has become for some months "a ViewLogic Company" (their words,
too).
Sunrise software current version is 2.1. What does "based on" mean ? I'm
curious to know whether ViewTest provides more features than Sunrise
Test Software.

BTW, Viewlogic has its W3 server at http://www.viewlogic.com, you can
find some info on Sunrise products at
http://www.viewlogic.com/sunrise/srover.html

>Does anyone have an address and telephone number for Sunrise.

Main address (corporate headquarters) is :

Sunrise Test Systems, Inc.
47211 Lakeview Blvd,
Fremont, CA 94538
Phone : 510/440-1000

Their e-mail adresses are : somebody@srtest.com (try postmaster@srtest.com
if you don't have a specific correspondant).
Info_Request@srtest.viewlogic.com also works.

Meryem.
-- 
Meryem Marzouki - TIMA/INPG - Meryem.Marzouki@imag.fr - Tel: (+33)76574696  
46 avenue Felix Viallet, 38031 Grenoble Cedex, France - Fax: (+33)76473814




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