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Messages from 325

Article: 325
Subject: Analog FPGAs
From: hadleyj@fpga.ee.byu.edu (James Hadley)
Date: 19 Oct 1994 18:27:58 -0600
Links: << >>  << T >>  << A >>

I found the following posting on usa-today.tech

>  IMP ANNOUNCES EPAC PRODUCT:
>     IMP Inc. introduced Tuesday the electrically programmable 
>  analog circuit (EPAC). It is the analog counterpart to the digital 
>  field programmable gate array (FPGA). EPAC is a highly flexible 
>  analog solution offering integrated circuit and system designers 
>  significant ease-of-use, cost, time-to-market and technological 
>  advantages over alternative products.

Does anyone know anything more about this device?  If so, how closely does it
match its FPGA "counterpart"?  Is is SRAM based or is it fused based?  Is it
run-time reconfigurable?  Does it currently have a set of development tools? And
if so, what are they?

On a side note, what would it mean to have a run-time reconfigurable analog
device?  Where would it be used?  Would we be looking at the beginning of a new
area in the capabilities of analog devices, or would such a device be only good
for rapid prototyping.  Any thoughts?

Jim Hadley
hadleyj@fpga.ee.byu.edy


Article: 326
Subject: Re: Analog FPGAs
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 20 Oct 1994 12:53:39 GMT
Links: << >>  << T >>  << A >>
Catalyst made a big splash about programmable analog devices a couple years ago.
I never heard what came of it.

As far as applications for run-time reconfiguring - sure, there are plenty of 
applications.  For example, by varrying the control around switch capacitor 
filters you can change filter characteristics on the fly.

Personally, I don't see what is taking the analog industry so long to get some 
programmability.  Probably an engineering hang up over any compromise on specs.

---
~ Bill Wolf, Raleigh NC           ~          I can see         ~
~ wolf@aur.alcatel.com            ~           the fog          ~
~ My opinions, NOT my employer's  ~  at the end of the tunnel  ~




Article: 327
Subject: Re: Analog FPGAs
From: devb@elvis.vnet.net (David Van den Bout)
Date: 20 Oct 1994 13:06:25 -0000
Links: << >>  << T >>  << A >>
In article <1994Oct19.180130@fpga.ee.byu.edu>,
James Hadley <hadleyj@fpga.ee.byu.edu> wrote:
>>  IMP ANNOUNCES EPAC PRODUCT:
>>     IMP Inc. introduced Tuesday the electrically programmable 
>>  analog circuit (EPAC). It is the analog counterpart to the digital 
>>  field programmable gate array (FPGA). EPAC is a highly flexible 
>
>Does anyone know anything more about this device?  If so, how closely does it
>match its FPGA "counterpart"?  Is is SRAM based or is it fused based?  Is it
>run-time reconfigurable?  Does it currently have a set of development tools? And
>if so, what are they?

The EPAC has much lower I/O and "gate" counts than FPGA-enthusiasts are
used to.  It has approximately 16 single-ended analog inputs and 3
analog outputs.  Internally, it has an analog multiplexer that selects
one of the inputs for processing by a collection of switched-capacitor
OPAMPs and low-pass filters (I assume for anti-aliasing).  The various
connections between the OPAMPs are made through a reconfigurable "analog
highway".  This highway is also used to steer signals to a probe output
so the user can observe any signal during the debugging process.  The
EEPROM of the EPAC is configured through a 3-wire serial I/O port.
The development tool is called "Analog Magic" and they sell it along
with an evaluation board and 4 EPAC chips for $2500.  The EPAC chips
are supposed to cost $22 in quantities of 1000.  For all the details,
check out "Electronic Design" for Oct. 14.

>
>On a side note, what would it mean to have a run-time reconfigurable analog
>device?  Where would it be used?  Would we be looking at the beginning of a new
>area in the capabilities of analog devices, or would such a device be only good
>for rapid prototyping.  Any thoughts?

The 50E10 EPAC (that's the current model number) is supposedly for
signal conditioning applications.  The article shows how the chip can
house several different analog paths with varying characteristics that
can be switched between depending upon the amplitude or DC-offset of
the input signal.  (A microprocessor is used to detect these conditions
and switch the EPAC control signals; no dedicated logic functions in the
EPAC except for binary thresholding.)

The EPAC looks good for prototyping with analog inputs of less than
125 KHz bandwidth.  A DSP with an ADC and DAC is more powerful but much
more complex to build.  I'm a bit more hard-pressed to see an application
where you would use a $22 chip to replace a bunch of hard-wired analog
that probably costs a couple of bucks.  It's probably useful in many
of the same types of applications where FPGAs were first used: ramping
up a product in an area where the requirements are still changing and
reconfigurability gives you a time-to-market edge.  And as the density
goes up and more analog circuitry is placed on board, I'm sure that new
applications will be inspired that take advantage of the ability to
reconfigure the analog circuitry in real-time.  There's probably a 
neural nets guy out there already trying to use the 50E10 .....

I'd advise you to check out the Electronic Design article.  There's a 
lot of interesting stuff I left out.  It certainly is a unique chip.



-- 

||  Dave Van den Bout  ||
||  Xess Corporation   ||


Article: 328
Subject: Re: XC3000 series FPGA with XAbel
From: MoellerInc <mmoeller@delphi.com>
Date: Thu, 20 Oct 94 20:15:33 -0500
Links: << >>  << T >>  << A >>
Are you using V5  of the software. If you are check for
uneeded pin lock flags in the mapped file.
 
There are some "non features" in V5 when using externally generated
xnf, especially if it is in CLB form before the final mapping.
 
urning off the " respet hiearchy" flag, this can help
mapping. If it is on it can force uneeded buffers to remain.
 
Also did you see the "wire" through a CLB after routing, PPR now can
complete a difficult rout by jumping through an otherwise unused CLB.
There is a flag in PPR hatprhibits this.
 
Martin Moeller
mmoeller@delphi.com
 
We do video in Xilinx.


Article: 329
Subject: Re: Xilinx v5.0 unified libraries are wasting CLBs
From: edi@ife.ee.ethz.ch (Edi Hiltebrand)
Date: 21 Oct 1994 13:27:53 GMT
Links: << >>  << T >>  << A >>
As i didn't get any response i think my posting got lost.
So lets try again.... :-)

At last we got the release 5.0 of the xilinx tools!!!
We started to convert a design done with the 4k libs to the
new unified libs. We noticed that the disign now needs a lot
more CLBs than it used with the old libs. The reason for this
is that the clock enable input of the CLB flipflops isn't used
and the CE feature is realised using the LUT. We just had to modify
some counters and regs to bring the design to a reasonable CLB 
count. If someone has similar observations we would be verry 
interested to hear. 

An other problem is still alive. If you use the carry logic 
it happens that sometime the ppr is putting some other signals
to the dedicated carry inputs of the LUT. Wath makes things worse 
with the new release is that the simulation is based on your 
schematics and not on the xnf file that results from the routing.
So you have no chance in detecting the errors introduced by the ppr
prior to loading the design into the HW. If anyone made similar 
observations we would like to know. And if there is any work arround
other than manualy correct the design in XDE it would be verry 
wellcome.

Thanks for any help!

Edi
-- 
*****************************************************************************
 Swiss Federal Institute of Technology     *   Email: edi@ife.ee.ethz.ch
 Electronics Laboratory                    *
 High Performance Computing                *
 Edi Hiltebrand                            *   Tel: +41 1 632 27 61
 8092 Zurich, Switzerland                  *   Fax: +41 1 632 12 10
*****************************************************************************


Article: 330
Subject: iFX780's experiences
From: loi@conware.de (Duy Loi Vu)
Date: 21 Oct 1994 13:42:52 GMT
Links: << >>  << T >>  << A >>
Hi all of you,
does any one there have any experiences with the Intel FPGA iFX780,
especially concerning the fitting problem while using PLDShell software
from Intel itself. I've used LOG/iC with ODC option to implement my design
and PLDShell software to fitt my design into the iFX780. Althrough I've used
the "correction mode" from LOG/iC, the pinout has changed after fitting even
I've made a small change in my design. I known that it is not possible to
prevent it totally. I would like to thank you for any hints to prevent it
as far as possible.
Best regards,
Vu Duy Loi


Article: 331
Subject: FPGA's to use with other devices
From: hrubin@b.stat.purdue.edu (Herman Rubin)
Date: 21 Oct 1994 13:32:52 -0500
Links: << >>  << T >>  << A >>
Some time ago, it was suggested to me that there may be a point
to using fpga's for operations used in generating non-uniform
random variables from a random bit stream, some of the operations
requiring procedures which are computationally very simple, but
very difficult to program on present computers.

The most needed one of these is the distance to the next bit which is
equal to one.  If used, it will be used quite frequently.  What makes
things difficult is that the operation is

	if(there is a one in the available portion of
	the bit stream)
		{value = the distance to the one;
		set the pointer so that this part
		of the bit stream is no longer used;
		return value;}

	else
		{x = number of bits left;
		refill the bits available and reset the 
		pointer;
		y = distance to the next one;
		set pointer as above;
		return x+y;}

As you see, there are things still left our, such as the location
of the end of the buffer, and the extreme possibility that a one 
will not be found the second time.  This will be very rare. 

Alternatively, the buffer could be augmented when it runs low,
in which case, from the standpoint of probability, the else part
could be ignored.  But it would still have to keep track of it,
and refill would not be very fast.  

How hard is this to do, and could such a unit be interfaced with
the CPU of another computer?  The other computer may be the 
appropriate unit for storage, and for refill.


		
		
-- 
Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907-1399
Phone: (317)494-6054
hrubin@stat.purdue.edu (Internet, bitnet)  
{purdue,pur-ee}!snap.stat!hrubin(UUCP)


Article: 332
Subject: I/O pin currents on Xilinx FPGAs?
From: cburian@ux4.cso.uiuc.edu (Christopher J Burian)
Date: 22 Oct 1994 03:32:31 GMT
Links: << >>  << T >>  << A >>
How much current can the pins source and sink?  Individually and
collectively?  

I saw a worst case spec of 4ma, and a best case of 25-30 times that.
I'd like to drive LED's between a 4017 on the anode side and the FPGA
on the cathode side with no current limiting resistors, using duty cycle
to limit instead.  I want to source up to 28 LED's in parallel off each
4017 line, and sink up to 28 LED's total, one per I/O line, from the FPGA,
at a duty cycle of 1/20 (2 4017's) or shorter (modulated by the FPGA) if
it's necessary.  Can the 4017 even light up 28 LED's in parallel?  Can it
continuously light 28 LED's without melting?  Will I get inconsitent 
brightness due to the 4017's internal resistance?  

This project must be kept outrageously cheap.  The LED arrays are surplus,
the gate arrays are free.  We want to pay for wire and solder and homemade
PC boards and batteries, and that's it.  If you've done this before, let
me know, yes I can do this, or no I need to add external buffers/drivers
on the 4017/FPGA/both side(s).  Please, don't waste bandwidth speculating
or reading specs out of a book.  I want to squeeze max performance out of
these things, so speak from experience, please.  I don't mind smoking 4017's
in testing, but I don't want to fry the very expensive (borrowed) FPGAs.  

Suppose I'm testing and a chip gets hot to the touch.  How hot can I let
it go?  Too hot to touch, like Pentiums get?  I've burnt the shape of a
heatsink into my fingers before with a DC motor driver I built, without 
apparent ill effects to the transistors.  I don't suppose a 4017 is that
rugged?

BTW, where can be buy those Polaroid flat batteries?  Preferably very cheaply.

Thanks much,

For SigArch, ACM@uiuc,

Chris



Article: 333
Subject: Final Call for Participation -- PhysComp 94
From: bhanu@seas.smu.edu (Bhanu Kapoor)
Date: Sat, 22 Oct 1994 18:12:30 GMT
Links: << >>  << T >>  << A >>


	     Final Registration Information and Advance Program
	      Workshop on Physics and Computation, PhysComp '94
			   This Decade and Beyond
		    November 17 - 20, 1994, Dallas, Texas
		  Sponsored by Dallas IEEE Computer Society
			    Sponsored by ONR/ARPA
	      Corporate Sponsor: Texas Instruments Incorporated

Enclosed is the  registration information  for the  Workshop on  Physics  and
Computation, PhysComp  '94, to be  held in Dallas,  TX, November 17-20, 1994.
See  the enclosed   preliminary   schedule  of   speakers.   The   conference
registration form/information should be sent  ASAP to help with our  planning
(see registration).  Please make your   own hotel reservations directly  with
the hotel by Tuesday October 25 (see hotel) or our special room rate will not
apply.

			    WORKSHOP REGISTRATION
			    ---------------------

To confirm your  plans to attend the workshop,  please  fill out registration
form enclosed below, and send it to one of the following addresses.

 date:  Please send in registration form ASAP

 email: matzke@hc.ti.com
  
 mail:  Doug Matzke
        Texas Instruments Incorporated
        PO Box 655474, MS 446
        Dallas, TX 75265

 fax:   Doug Matzke @ (214) 995-6194

The workshop  registration  fee  is  $200.  We  will accept  both  checks and
Visa/Master Card for registration. We can accept payment  by CHECK drawn from
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Additional  PhysComp 94 (and   PhysComp  92) proceedings can be   preordered.
Information about the location of the  reception and other workshop functions
will be available at the hotel desk at check-in.

		      HOTEL REGISTRATION/ACCOMMODATIONS
		      ---------------------------------

The Workshop will be  held at The  Harvey Hotel in  Addison, Texas.   We have
reserved a block of rooms at a discounted per night rate  of US$59 for single
or US$69 for double occupancy.   Please make your hotel reservation  directly
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 date: Tuesday October 25 (***Notice New Deadline***)
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 mail: The Harvey Hotel
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 phone: (800) 922-9222 or (214) 980-8877

**WARNING: PLEASE REGISTER EARLY**.  Because  of another large conference  in
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Please  mention  the  "PHYSCOMP  or IEEE  or Texas  Instruments Workshop"  to
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				    -----

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Ask for directions to The Harvey Hotel/Addison at the rental desk.

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			   QUESTIONS OR ASSISTANCE
			   -----------------------
Please feel free to contact me if you need any assistance with arrangements.

Douglas Matzke                                  Net: matzke@hc.ti.com
Texas Instruments                               Tel: (214) 995-0787
PO Box 655474, MS 446                           Fax: (214) 995-6194
Dallas, TX 75265   				MSG: MTZK

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---------------------------------- cut here ----------------------------------

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---------------------------------- cut here ----------------------------------

			     Preliminary Program
		Workshop Physics and Computation, PhysComp 94
			    Harvey Hotel-Addison

====================================================================
====================  Wednesday pm, Nov 16, 1994 ===================

 6:00 -  9:00  Registration, Reception, and cash bar

====================================================================
====================  Thursday am, Nov 17, 1994  ===================

 7:30 -  8:30  --- Continental Breakfast ---

Session 1:     The Technologist's Perspective on Nanoelectronics
----------     Chair: Gary Frazier

 8:30 -  9:00  Integrated Circuits, Nanoelectronics, and
               21st Century Electronic Systems
               Bob Bate (Texas A&M University)

 9:00 -  9:30  The Life Expectancy of CMOS Technology
               Bob Doering (Texas Instruments)

 9:30 - 10:00  Research Toward Nanoelectronic Computing
               Technologies in Japan
               Rick Kiehl (Fujitsu)

10:00 - 10:30  --- BREAK ---

Session 2:     Computing With Quantum Devices
----------     Chair: Gary Frazier

10:30 - 11:00  Resonant Tunneling Quantum Devices and Circuits
               Alan Seabaugh (Texas Instruments)

11:00 - 11:30  Quantum Cellular Automata: The Physics os Computing
               with Arrays of Quantum Dot Molecules
               Craig S. Lent, P. Douglas Tougaw,
               and Wolfgang Porod (Univ. Notre Dame)

11:30 - 12:00  Results on Two-Bit Gate Design for Quantum Computers
               David DiVincenzo (IBM)

12:00 -  1:30  --- LUNCH ---

====================================================================
====================  Thursday pm  =================================

Session 3:     Architecture Issues in Nanoelectronics
----------     Chair: Wolfgang Porod

 1:30 -  2:00  Horizons of Parallel Computation
               Gianfranco Bilardi (University of Padova)

 2:00 -  2:30  Multiprocessor Architectures and Physical Law
               Paul Vitanyi (CWI / Univ. of Amsterdam)

 2:30 -  3:00  Algebras and Architectures for Nanoelectronics
               Gary Frazier (Texas Instruments)

 3:00 -  3:30  --- BREAK ---

Session 4:     Architecture Issues for Computation
----------     Chair: Doug Matzke

 3:30 -  4:00  The Latest in Adiabatic Computing
               John Denker (AT&T)

 4:00 -  4:30  Impact of Locality and Dimensionality Limits
               on Architecture Trends
               Doug Matzke (Texas Instruments)

 4:30 -  5:00  Space, Time, Logic, and Things
               Dick Shoup (Interval Research)

 5:00 -  5:30  Space and Time in Computation, Topology
               and Discrete Physics
               Louis H. Kauffman (Univ. Illinois at Chicago)

====================================================================
====================  FRIDAY am, Nov 18, 1994  =====================

 8:00 -  9:00  --- Continental Breakfast ---

Session 5:     KEYNOTE ADDRESS      
----------     General Chair: Doug Matzke

 9:00 - 10:00  Computation in Analog and Digital Physical Systems
               Carver Mead  (Cal Tech)

10:00 - 10:30  --- BREAK ---

Session 6:     QUANTUM COMPUTERS
----------     Chair: Bill Frensley

10:00 - 10:30  Is Quantum Mechanics Useful?
               Rolf Landauer  (IBM)

10:30 - 11:00  The Stabilisation of Quantum Computations
               Andre Berthiaume (Univ. Montreal), David Deutsch 
               (Univ. Oxford), and Richard Jozsa (Univ. Plymouth)

11:00 - 11:20  Can Quantum Computers Have Simple Hamiltonians?
               Michael Biafore  (MIT)

11:20 - 11:40  Quantum Oblivious Transfer Is Secure Against All
               Individual Measurements
               Dominic Mayers and Louis Salvail (Univ. Montreal)

11:40 -  1:30  --- LUNCH ---

====================================================================
====================  FRIDAY pm  ===================================

Session 7:     QUANTUM COMPUTATION
----------     Chair: Wolfgang Porod

 1:30 - 2:15   A Fast Algorithm for Factoring on Quantum Computers
               Peter Shor (AT&T)

 2:15 - 3:00   Decoherence and Quantum Computers- A Problem
               Bill Unruh  (Univ. B. C., Vancouver)

 3:00 - 3:30   --- BREAK ---

Session 8:     PHYSICS as COMBINATORIAL COMPUTATION
----------     Chair: Riley Jackson

 3:30 - 4:00   Physical Parallelism and Computation
               Keith Bowden (Univ. East London)

 4:00 - 4:30   Bit-String Physics: A Novel "Theory of Everything"
               H. Pierre Noyes  (Stanford Univ.)

 4:30 - 5:00   Toward an Information Mechanics
               Michael Manthey  (Aalborg Univ.)

====================================================================
====================  SATURDAY am, Nov 19, 1994 ====================

 7:30 -  8:30  --- Continental Breakfast ---

Session 9:     REVERSIBLE LOGIC
----------     Chair: Paul Vitanyi

 8:30 -  9:00  Reversible Logic Issues in Adiabatic CMOS
               Bill Athas and Lars Svensson  (USC)

 9:00 -  9:20  Thermal Logic Circuits
               J. G. Koller, W. C. Athas, and L. J. Svensson (USC)

 9:20 -  9:40  A Reversible Instruction Set Architecture and Algorithms
               J. Storrs Hall  (Rutgers Univ.)

 9:40 - 10:00  Encoded Arithmetic for Reversible Logic
               Akhilesh Tyagi  (Iowa State Univ.)

10:00 - 10:30  --- BREAK ---

Session 10:    CELLULAR AUTOMATA & REVERSIBLE CA
-----------    Chair: Andrew Ilachinski

10:30 - 10:50  Some Results on Invertible Cellular Automata
               Andrea Clementi, Patrizia Mentrasti (Univ. Roma), 
               and Pierluigi Pierini (MIT)

10:50 - 11:10  On the Average-Case Complexity of the Reversibility
               Problem for Finite Cellular Automata
               Andrea Clementi (Univ. Roma), Pierluigi Pierini (MIT), 
               and Russell Impagliazzo (UC San Diego)

11:10 - 11:30  Necessary and Sufficient Conditions for Reversibility in
               One Dimensional Cellular Automata
               Jose Alberto Baptista Tome (INESC Lisbon)

11:30 - 12:00  Coupling Computations Through Space
               Pedro P. B. de Oliveira (Nat'l Inst. Space Res.,  Brazil)

12:00 -  1:30  --- LUNCH ---

====================================================================
=========================  SATURDAY pm  ============================

Session 11a:   QUANTUM COMPUTATION 
------------   Chair: Bill Frensley

 1:30 - 1:50   Quantum Waveguide Structures and Devices
               Stephen M. Goodnick, A. Weisshaar, A. Ecker,
               and V. K. Tripathi (Oregon State Univ.)

 1:50 - 2:10   On a Method of Solving SAT Efficiently Using
               the Quantum Turing Machine
               Takashi Mihara and Tetsuro Nishino
               (Japan Adv. Inst. Sci. & Technol.)

 2:10 - 2:30   Chu Spaces: Automata with Quantum Aspects
               Vaughan Pratt  (Stanford Univ.)

Session 11b:   STATISTICAL MECHANICS and INFORMATION
------------   Chair: Riley Jackson

 2:30 - 2:50   Statistical Mechanics of Combinatorial Search
               Tad Hogg (Xerox PARC)

 2:50 - 3:10   Phase Transitions and Coarse-Grained Search
               Colin P. Williams and Tad Hogg (Xerox PARC)

 3:10 - 3:30   --- BREAK ---

Session 12:    ENTROPY and INFORMATION
-----------    Chair: Andrew Ilachinski

 3:30 - 4:00   The Boltzmann Entropy and Randomness Tests
               Peter Gacs  (Boston Univ.)

 4:00 - 4:20   Entropy Cost of Information
               Paul N. Fahn  (Stanford Univ.)

 4:20 - 4:40   The Complexity and Entropy of Turing Machines
               Paul A. Dufort and Charles J. Lumsden  (Univ. Toronto)

 4:40 - 5:00   A Fast Algorithm for Entropy Estimation of Grey-Level Images
               Salvatore D. Morgera and Jihad M. Hallik (McGill Univ.)

 6:30 - 9:00   --- Reception, cash bar, and Banquet  --- 
               Making waves with our troubadour
               Gilles Brassard (Universit\'e de Montr\'eal
               and Ecole Normale Sup\'erieure)

====================================================================
======================  SUNDAY am, Nov 20, 1994  ===================

 7:30 - 8:30   --- Continental Breakfast ---

Session 13:    PARALLEL COMPUTATION
-----------    Chair: Sharad Saxena

 8:30 -  9:00  Computational Spacetimes
               E. Theodore L. Omtzigt  (Intel)

 9:00 -  9:20  Evolution, Entropy, and Parallel Computation
               Kurt Thearling  (Thinking Machines)

 9:20 -  9:40  On Physical Models of Neural Computation and Their 
               Analog VLSI Implementation
               Andreas G. Andreou  (Johns Hopkins Univ.)

 9:40 - 10:00  Analog Computation with Continuous ODEs
               Michael S. Branicky  (MIT)

10:00 - 10:30  --- BREAK ---

Session 14:    Panel session on Physics and Computation
-----------    Chair: John Denker

10:30 - 12:00  Topic:  How will PhysComp make an impact? 
               
==============================================================================
==============================================================================

			   PLEASE POST AND FORWARD




Article: 334
Subject: High Bus Drive (24mA) FPGAs/CPLDs?
From: kevsteele@aol.com (KevSteele)
Date: 23 Oct 1994 00:19:08 -0400
Links: << >>  << T >>  << A >>
I'm familiar with the Xilinx 4kH series that can drive busses
directly...are there any others out there that are capable of IOL 24mA?


Article: 335
Subject: Xilinx ROMS
From: nb0@engr.uark.edu (NAGARAJAN BALAKRISHNAN)
Date: 23 Oct 1994 16:00:38 GMT
Links: << >>  << T >>  << A >>
  I  have just start to use Xilinx software for FPGA. I was able to write ROM 
initialization file and generate .XNF file from it using MEMGEN in xilinx. It also 
generated symbol for powerview. When I used that symbol in my schematics, powerview 
doesn't give any error messages, but I was not able to do XMAKE in Xilinx to create
bitstream. Can anyone tell me what is the procedure to be followed for using ROMs.

-NAGARAJAN BALAKRISHNAN.
 nb0@engr.uark.edu 






Article: 336
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: tabarr@ix.netcom.com (Timothy Barr)
Date: 23 Oct 1994 16:17:16 GMT
Links: << >>  << T >>  << A >>
In <38a14f$cmp@vixen.cso.uiuc.edu> cburian@ux4.cso.uiuc.edu (Christopher J Burian) writes: 

>
>How much current can the pins source and sink?  Individually and
>collectively?  
>
>I saw a worst case spec of 4ma, and a best case of 25-30 times that.
>I'd like to drive LED's between a 4017 on the anode side and the FPGA
>on the cathode side with no current limiting resistors, using duty cycle
>to limit instead.  

The 4000H series has higher output current than the 4000 or 4000A parts.

>Suppose I'm testing and a chip gets hot to the touch.  How hot can I let
>it go?  Too hot to touch, like Pentiums get?  I've burnt the shape of a
>heatsink into my fingers before with a DC motor driver I built, without 
>apparent ill effects to the transistors.  I don't suppose a 4017 is that
>rugged?
>
I have had 3000 series and 4000 series parts get hot enough to give me
a second degree burn, and still seem to work. The reason mine get hot,
FYI, is because of initialization problems. If you "phantom power"" I/O
pins, the chip may not configure correctly.


Article: 337
Subject: Re: High Bus Drive (24mA) FPGAs/CPLDs?
From: fliptron@netcom.com (Philip Freidin)
Date: Mon, 24 Oct 1994 03:01:54 GMT
Links: << >>  << T >>  << A >>
In article <38co7s$n48@newsbf01.news.aol.com> kevsteele@aol.com (KevSteele) writes:
>I'm familiar with the Xilinx 4kH series that can drive busses
>directly...are there any others out there that are capable of IOL 24mA?

As well as the Xilinx XC400?H products, the XC400?A products are also
guaranteed for 24 mA per pin. You can also get 24 mA by pairing pins on
the rest of the XC4000 products, i.e. send the same signals to a pair
of IOBs that are adjacent, and then tie the pins together outside the
chip. It is important that the timing to the two drivers is as close
as possible, to minimize contention.

Unless you are driving a load that has a static DC current of 24mA such
as a terminating resistor of 220 ohms to VCC, then the 12mA per pin from
the XC4000 may be enough. For example, I am currently designing a board
that directly drives a PC (ISA) bus with an XC4010. This is quits safe,
because data pins on the ISA bus eithe dont have termination resistors,
or they have wimpy 10K pullups so the lines dont float (ISA and EISA
Theory and Operation by Edward Solari, page 444, 445).

For transient current behaviour, The Xilinx databook gives typical I/V
curves on pages 8-6 thru 8-9, as well as ground bounce and derating
calculations for various capacitive loads. Very instructive :-)

All the best
		Philip Freidin


Article: 338
Subject: Re: SRAM and antifuse for interconnects
From: dwg@hpqmdla.sqf.hp.com (David Qmd Grieve)
Date: Mon, 24 Oct 1994 13:30:14 GMT
Links: << >>  << T >>  << A >>
Bob Elkind (bobe@soul.tv.tek.com) wrote:
: gbchoy@salsa.engr.ucdavis.edu (Garett B Choy) writes:

: 1. Altera makes both RAM-based (reconfigurable) and non-RAM based
:    (i.e. one-time-programmable) FPGAs.

Erm, the Altera 5000 series are EPROM the 7000 series are EEPROM.

The only "one-time" programmable parts are the EPROM parts that
are encapsulated in windowless plastic for cost reasons.

Makes a difference, when you get the logic wrong!

David.


Article: 339
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: awolfe@oink.Princeton.EDU (Andrew Wolfe)
Date: Mon, 24 Oct 1994 17:32:54 GMT
Links: << >>  << T >>  << A >>
In article <38a14f$cmp@vixen.cso.uiuc.edu>, cburian@ux4.cso.uiuc.edu (Christopher J Burian) writes:
|> How much current can the pins source and sink?  Individually and
|> collectively?  
|> 
...
|> 
|> This project must be kept outrageously cheap.  The LED arrays are surplus,
|> the gate arrays are free.  We want to pay for wire and solder and homemade
|> PC boards and batteries, and that's it.  If you've done this before, let



Why bother.  Transistors cost a nickel each!  Since you seem to be cost (not
space) driven - just add a transistor to each output as a driver.  Current
limit each segment with a resistor.  For under $2 you can get a very bright
display.  No worries about burning up a Xilinx chip.

(Of course - we know that the real problem is that most EE's don't know how
to design a circuit with a transistor anymore :-)

-- 
--------------------------------------
Andrew Wolfe
Assistant Professor
Department of Electrical Engineering
Princeton University


Article: 340
Subject: Suggestions for low power FPGAs/CPLDs needed
From: npomponi@cmdl.gatech.edu (Nick Pomponio)
Date: 24 Oct 1994 18:03:49 GMT
Links: << >>  << T >>  << A >>
I have a project coming up that will require very low power (sub-mA), 3V
logic operating in the few hundreds of KHz.  I would like to persue a
FPGA/CPLD design.  What manufacturers offer the lowest operating
power devices?

Thanks.



Article: 341
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: pfile@sun33.cs.wisc.edu (Rob Pfile)
Date: 24 Oct 1994 19:05:38 GMT
Links: << >>  << T >>  << A >>
In article <fliptronCy5pz4.98A@netcom.com> fliptron@netcom.com (Philip Freidin) writes:


   Actually, the XC4000A parts are also specified for 24mA. In the realm
   of FPGAs, only Xilinx makes FPGAs with 24mA drive. There are some PAL 

Is this true? I thought that Altera FLEX8000 parts can sink or source
25mA per pin.

rob
pfile@cs.wisc.edu






Article: 342
Subject: Re: SRAM and antifuse for interconnects
From: gbchoy@salsa.engr.ucdavis.edu (Garett B Choy)
Date: 25 Oct 1994 15:25:02 GMT
Links: << >>  << T >>  << A >>
dwg@hpqmdla.sqf.hp.com (David Qmd Grieve) writes:

>Bob Elkind (bobe@soul.tv.tek.com) wrote:
>: gbchoy@salsa.engr.ucdavis.edu (Garett B Choy) writes:

>: 1. Altera makes both RAM-based (reconfigurable) and non-RAM based
>:    (i.e. one-time-programmable) FPGAs.

Just for clarification, I did not write the above statement, I believe
it was a response to my question.  I (G Choy) was the one who asked the
original question.  But, but I did want a discussion on different fpga
technologies (good and bad experiences).

>The only "one-time" programmable parts are the EPROM parts that
>are encapsulated in windowless plastic for cost reasons.

>Makes a difference, when you get the logic wrong!

I'm not sure, but it seems to me that there are two main advantages to
using an fpga: 1) design is quicker because it may be programmed through
software  2) production is quicker/cheaper because there is no "glue-logic"
all over the place and you don't have to wait for in-factory designed ASICs.

For reason 1, I see why reprogrammability is a good thing.
For reason 2, why is reprogrammability important?

If I'm missing something, please let me know.

Garett



Article: 343
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: pak@cse.ucsc.edu (Pak K. Chan)
Date: 25 Oct 1994 15:26:54 GMT
Links: << >>  << T >>  << A >>
>
>Actually, the XC4000A parts are also specified for 24mA. In the realm
>of FPGAs, only Xilinx makes FPGAs with 24mA drive. There are some PAL 

           4000A can drive 4mA, and sink 24 mA.


Article: 344
Subject: Re: High Bus Drive (24mA) FPGAs/CPLDs?
From: carr@procyon.pmc-sierra.bc.ca (Larrie Carr)
Date: Tue, 25 Oct 1994 12:13:24 -0800
Links: << >>  << T >>  << A >>
I believe the (was) Intel FlexLogic 8160 was designed for this
(PCI).

In article <38co7s$n48@newsbf01.news.aol.com>, kevsteele@aol.com
(KevSteele) wrote:

> I'm familiar with the Xilinx 4kH series that can drive busses
> directly...are there any others out there that are capable of IOL 24mA?

-- 
Larrie Carr
Product Designer
PMC-Sierra, Inc.
Burnaby, B.C.


Article: 345
Subject: Memory
From: lfadden@harris.com (Lee Fadden)
Date: Tue, 25 Oct 1994 21:30:39 GMT
Links: << >>  << T >>  << A >>
Hi,
  Can anyone point me to a forum or book on work being done in associative 
memory architecture?  I'd appreciate any info on alternative 
computer architecuture. Thanks.

LF



Article: 346
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: cburian@ux4.cso.uiuc.edu (Christopher J Burian)
Date: 25 Oct 1994 21:54:12 GMT
Links: << >>  << T >>  << A >>
awolfe@oink.Princeton.EDU (Andrew Wolfe) writes:

]Why bother.  Transistors cost a nickel each!  Since you seem to be cost (not
]space) driven 

Actually, bulk and weight are factors--these are going to be digital nametags.

](Of course - we know that the real problem is that most EE's don't know how
]to design a circuit with a transistor anymore :-)

I'm an electronics hobbyist first--we still know how to use those archaic
technologies.  And I worked on tube amplifiers in the Navy.

Thanks,
Chris


Article: 347
Subject: Xilinx and mentor
From: kky@itd.dsto.gov.au (Ken Yiu)
Date: 26 Oct 1994 02:42:04 GMT
Links: << >>  << T >>  << A >>
Hi. 
We are having a series of strange bugs with our Mentor/XACT 5 software.
We are using both .XNF logic blocks and schematic components on 
a Design Architect sheet. 

1) When we place symbols with schematic models, the software cannot read
the models under the symbol. Design archect refuses to open the sheet. e.g.:

//  Error: $$open_sheet returned error status at line 13250 of file /usr2/idea/shared/pkgs/des_arch/userware/En_na/schematic.ample within function $choose_model (from: Uims/Ample/Ample_eval 1D)
//  Error: Attempt to connect failed (for child of schematic named schematic) (from: DDMS/DDMS_Core/DDMS General 05)
//  Error: Attempt to connect child Design object failed (child $LCA/xblox/bus_if15/schematic/sheet1) (from: DDMS/Ddms_do 0025)
//  Note: Design object $LCA/xblox/bus_if15/schematic contains a reference to $LCA/xblox/bus_if15/schematic/sheet1 (from: DDMS/Ddms_do 0083)
//  Error: Type Rep mismatch (Type_name: Eddm_fraction, Type_uid: 4f9039495000.0d.00.02.e7.6d.00.00.00, Type_version: 7)
//  Version on stream (Stream version: 8) is newer (from: DDMS/DDMS_Core/Type Management 0E)

Building xnf files using EDIF2XNF won't work either, for the same reason.
This occurs with quite basic components like fdre (a D flip flop) etc
. 

2) The other problem seems to be in gen_sch8. This exits with the following error.
gen_sch8 -w rx_test_fnc.xnf
 
ld.so: call to undefined procedure ___sti__ddms_propl_C_init_name_type_hash_ from 0x323558

We are in touch with Xilinx about these problems. The Xilinx software and libraries
have been freshly reinstalled and the enviroment variables checked. 
What I'd like to know is this: Are we alone in having these problems or do other
people have the same problems? If so, what did you do about them? 

Thank you,
Ken Yiu.

 






Article: 348
Subject: Re: I/O pin currents on Xilinx FPGAs?
From: rick@cs.sunysb.edu (Rick Spanbauer)
Date: 26 Oct 1994 13:02:42 GMT
Links: << >>  << T >>  << A >>
Andrew Wolfe (awolfe@oink.Princeton.EDU) wrote:
: In article <38a14f$cmp@vixen.cso.uiuc.edu>, cburian@ux4.cso.uiuc.edu (Christopher J Burian) writes:
: ...
: |> This project must be kept outrageously cheap.  The LED arrays are surplus,
: |> the gate arrays are free.  We want to pay for wire and solder and homemade
: |> PC boards and batteries, and that's it.  If you've done this before, let


: Why bother.  Transistors cost a nickel each!  Since you seem to be cost (not
: space) driven - just add a transistor to each output as a driver.  Current
: limit each segment with a resistor.  For under $2 you can get a very bright
: display.  No worries about burning up a Xilinx chip.
: (Of course - we know that the real problem is that most EE's don't know how
: to design a circuit with a transistor anymore :-)
: Andrew Wolfe
: Assistant Professor
: Department of Electrical Engineering
: Princeton University

	Off on a tangent: in the real world, that $0.05 transistor may cost
	you up to $0.20 to get stuffed on a board, has a cost in manpower
	to aquire/inventory/debug on failure, etc.  When you're doing commercial
	design, every cent counts.  Tell me about any place besides the land 
	of $299 hammers where this isn't true :-)

	These comments made with my "small businessman" hat on.

					Rick Spanbauer
					Dept Of Computer Science
					State University of New York



Article: 349
Subject: NIM: FPD '95 - Call for Papers
From: janet@classic3.ic.cmc.ca (Janet Tite)
Date: Wed, 26 Oct 1994 16:01:09 GMT
Links: << >>  << T >>  << A >>


~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
NEWS IN MICROELECTRONICS                 Volume 6, Number 51, October 26, 1994
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
                                                          
TODAY'S ISSUE: 	FPD '95: The Third Canadian Workshop on Field-Programmable
 		Devices: Technology, Tools and Applications
		May 29-June 1, 1995, Montreal, Quebec

ADVANCE NOTICE AND CALL FOR PARTICIPATION
The Ecole Polytechnique de Montreal and the Universite du Quebec a Montreal 
will host the Third Canadian Workshop on Field-Programmable Devices (FPD'95).  
The goal of this Workshop is to bring together workers from throughout Canada 
for a wide-ranging discussion on all forms of field-programmable devices and 
their applications.  Discussion will focus on industrial applications, advanced 
CAD tools and systems, novel system architectures and educational experience.
English will be used for discussions and the principal printed materials, but 
contributions can be submitted and presented in either English or French.

SPECIFIC OBJECTIVES AND SCOPE OF THE WORKSHOP
-       To continue to provide a forum for discussion on the design and 
	application of FPGAs
-       To provide an appropriate forum, both for those in industry and 
	those in post-secondary education
-       To allow manufacturers of field-programmable device software and 
	hardware an opportunity to present their products to a specialized 
	group
-       To include a wide range of field-programmable devices such as 
	interconnect components, analog arrays, etc.
-       To increase the emphasis on designing at the system level, using 
	synthesis to generate the circuit details
These objectives will be implemented through:
-       Hands-on training
-       Tutorials and demonstrations
-       Industrial and academic case studies
-       Industry, university and educational paper sessions (lecture and/or 
	poster formats)
-       A session on commercial opportunities and business implications

SUBMISSION OF PAPERS
Prospective participants are invited to submit one (1) copy of an extended 
summary to the Organizing Committee Chairs for review.  The summary should be 
no more than four (4) pages in length, including title pages and figures.  
Submissions must be marked "FPD'95 WORKSHOP" and may be in hard copy or 
electronic format.  Acceptable electronic formats are PostScript, FrameMaker
and WordPerfect.  Authors should indicate whether their preferred presentation 
format is lecture, poster or demonstration.  If possible, authors should also 
provide an e-mail address to facilitate rapid communication. Authors of accepted
papers (lecture, poster and demonstration) will be asked to prepare a
camera-ready version for publication in the Workshop proceedings. As this is a 
Workshop emphasizing the exchange of ideas and research results, the material
does not have to consist of unpublished results, but novelty is desirable.  The
referees will favour material that is of interest to industrial and/or 
university users of field-programmable devices.

AUTHORS' SCHEDULE
-       Submissions of extended summaries:      Friday, January 27
        (to Organizing Committee Chairs)
-       Notification of acceptance:     	Friday, March 10
-       Final version of paper: 		Friday, April 21
        Submissions should be addressed to: 
		Prof. Mohamad Sawan (Co-Chair) 
		Ecole Polytechnique de Montreal 
		Department of Electrical and Computer Engineering 
		P.O. Box 6079, Station centre-ville
		Montreal, (Quebec) H3C 3A7  CANADA 
		Fax:     (514) 340-4147 
		E-mail:  sawan@vlsi.polymtl.ca.

AREAS OF INTEREST
It is expected that there will be a wide range of discussion topics because 
of the versatility of field-programmable device technology.  Some suggested
topic areas are:
    - Architecture and technology
    - Design and development tools
    - Industry case studies
    - Educators' experiences
    - Novel approaches to and utilizations of the technology
    - Design approaches
    - Business/commercial aspects of the technology
    - Entrepreneurial opportunities and support
    - System design issues
    - Synthesis opportunities for programmable devices
    - Partitioning across multiple FPGAs and/or interconnects.

PAPER SESSIONS
Researchers and industrial users are encouraged to show the results of their 
field-programmable device activities - the projects presented can be of an 
ongoing nature.  Educators are welcome to present experiences with incorporating
field-programmable devices into their curriculum. This is expected to be an 
active forum for the exchange of ideas for course and laboratory development.
Industrial users are also encouraged to present case studies utilizing 
field-programmable devices in their particular environment.  Papers describing 
how practical problems have been overcome are welcome. Manufacturers of 
field-programmable device software and hardware may also make presentations on 
the engineering characteristics of their software and/or devices. We are also 
soliciting presentations on the commercial and business aspects of this 
technology, including entrepreneurial issues.  Examples of topics are: financial
considerations of introducing field-programmable devices into the product life 
cycle; when to switch from field-programmable to mask-programmable gate arrays; 
etc. A combination of both lecture-style presentations and poster/demonstration 
sessions are planned for the workshop.  The poster/demonstration sessions are 
provided for those applications where it makes more sense to present results 
using this format. Ecole Polytechnique may be able (reservation required) to 
lend workstations, PCs and other large equipment for use in demonstrations.
Vendors of field-programmable-related products will also have a forum for 
demonstrating and promoting their products among workshop attendees.

HANDS-ON SESSIONS
During this Workshop, we anticipate hosting several hands-on sessions for a 
wide variety of users from novice to expert.  Plans are being made to include 
tutorial sessions given by the major tool and device vendors.

WORKSHOP COMMITTEES
ORGANIZING COMMITTEE:
- Mohamad Sawan (Co-Chair), Ecole Polytechnique de Montreal
        Telephone: (514) 340-5943,      Fax: (514) 340-4147
- Jacob Davidson (Co-Chair), Universite du Quebec a Montreal (UQAM)
        Telephone: (514) 987-3323,      Fax: (514) 987-8477
- Raymond Levesque (Administration), Ecole Polytechnique de Montreal
- Lynda Moore (Network Communications), Canadian Microelectronics Corporation

PROGRAM COMMITTEE:
Paul Chow      	  
University of Toronto           
pc@eecg.utoronto.ca

Jacob Davidson (Co-Chair) 
Universite du Quebec a Montreal 
davidson.jacob@uqam.ca

Baher Haroun             
Concordia University            
haroun@ece.concordia.ca

John Knight             
Carleton University     
jknight@doe.carleton.ca

Bob McLeod               
University of Manitoba  
mcleod@ee.umanitoba.ca

Michael Miller          
University  of Victoria 
dmill@csr.uvic.ca

Mohamad Sawan (Co-Chair)  
Ecole Polytechnique de Montreal 
sawan@vlsi.polymtl.ca

Ted Szymanski           
McGill University       
teds@macs.ee.mcgill.ca

Claude Thibeault         
Ecole de Technologie Superieure 
thibault@ele.etsmtl.ca

Laurence Turner         
University of Calgary   
turner@enel.ucalgary.ca

LOCATION, REGISTRATION AND ACCOMMODATION
The Workshop will be held at the Ecole Polytechnique de Montreal, 2900 Chemin 
de la Polytechnique, May 29-June 1, 1995.  Accommodation at the Radisson Hotel 
will be available at a special rate from the evening of May 28 (Sunday) until 
breakfast on June 2 (Friday), i.e. five nights. Additional nights and 
accommodation for non-participants can be arranged (see Registration Form).
Montreal has numerous cultural and tourist attractions. Social programs will 
be organized for non-participants.

OTHER USEFUL INFORMATION
GENERAL: Montreal, a fusion of European style and the American way of life, is 
one of the loveliest cities in North America and is situated between the 
St-Lawrence River and Mount Royal. After Paris, Montreal is the second-largest 
French-speaking city in the world, with the advantage of offering services in 
English as well.
TRANSPORTATION:  Both airports offer convenient public transportation into 
downtown Montreal. The one-way shuttle bus fare is $8.50 Cdn. from Dorval and 
$13.50 from Mirabel. By taxi, the trip into town is about $25 from Dorval and 
$60 from Mirabel.  In Montreal, there is an extensive bus and subway network
(Montrealers call the subway the "Metro"), and a ticket for either costs $1.75.
WEATHER: During the month of May, temperatures can vary quite a bit.  During 
the day, they may reach 22 C, or drop to as low as 8 C.  Evenings are 
generally cool (4 to 10 C).

============================= CUT HERE =======================================
        

Title: 	Ms. _____  Mrs. ______  Mr.______  Dr.______  Prof.______

Last Name: _____________________  First Name: ___________________

Affiliation: ____________________________________________________

Address: ________________________________________________________

City: ____________________________ Postal code: _________________

Country: ____________________  Phone: ___________________________

                                 Fax: ___________________________

I intend to participate:                Yes____, No_____.

Keep my name on the mailing list:       Yes____, No_____.

I hope to present a paper:              Yes____, No_____.

Tentative title:______________________________________________

______________________________________________________________

------------------------------------------------------------------------------
CMC -  NEWS  IN MICROELECTRONICS is distributed electronically by the Canadian
Microelectronics  Corporation  for   information  exchange  primarily  between
Canadian individuals and groups  working  in VLSI-related fields.  Some issues
are available in printed form.
 
For further information contact Janet Tite     Internet:   vlsiic@cmc.ca
                                               Fax:        (613) 548-8104
                                               Telephone:  (613) 545-2914
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
CANADIAN MICROELECTRONICS CORPORATION/SOCIETE CANADIENNE DE MICRO-ELECTRONIQUE
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~








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2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

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