Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 2575

Article: 2575
Subject: Solved -> Re: Need help: Actel "bibuf" working with Q
From: rjmyers@ti.com (Bob Myers)
Date: 4 Jan 1996 18:36:35 GMT
Links: << >>  << T >>  << A >>
In article <4cee3h$775@mksrv1.dseg.ti.com>, ToddThuss says...
>
>
>  rjmyers@ti.com (Bob Myers) wrote:
>>I'm having problems with using "bibuf" primitives on an Actel schematic
>>simulation.  In the design that I'm trying to simulate, I have valid data
>>going to the "D" pins and can see either a "1" or "0" on the "E" pins,
>>however when I look at the traces for the "Y" or "PAD" pins, I always
>>see unknown values.  These values appear whether or not I have the pads
>>connected (via ripped bus) to the I/O pins of a dram chip (LMC smartmodel).
>>
>

I found out what the problem was and am not having any problems at this time.
Turns out that aftert Quicksim comes up, I have to immediately change the
setup->environment state to use "wired" versus "charged" for signals.

Since the bidirectional bus I'm working with is not taking inputs from 
stimulus files (just from the design itself and also i/o from some SRAMs 
that have bidirectional pins), I needed to change the system environment to
handle the "wired" signals for me.

Thanks to all who sent me mail directly and/or posted in the news group.

Regards,
bob



Article: 2576
Subject: FPGA'96 Adv. Program
From: cong@rabbit.cs.ucla.edu (Dr. Jason Cong)
Date: 4 Jan 1996 11:24:17 -0800
Links: << >>  << T >>  << A >>
******   Most up-to-date on-line symposium program is available at   *********
****** http://www.cs.washington.edu/research/projects/lis/www/fpga96 *********

			FPGA `96 Advance Program
			------------------------

1996 ACM/SIGDA Fourth International Symposium on Field-Programmable Gate Arrays

			     February 11-13, 1996
		Monterey Beach Hotel, Monterey, California, USA

Sponsored by ACM SIGDA, and Xilinx, Inc., Altera Corp. and Actel Corp.

Over the past ten years FPGAs have revolutionized the way many systems are 
designed by providing a low-cost, fast-turnaround implementation alternative. 
This is an exciting time in an exciting field that is still expanding as new 
technologies appear, new architectures are proposed, and new CAD tools are 
developed to address problems specific to FPGAs. This Symposium focuses on the 
architectural and algorithmic issues that FPGA architects and CAD designers 
face today and in the future. This is a forum where researchers from industry 
and university present and debate the latest ideas in FPGA design and 
application.

The technical program consists of papers concerning both the practical 
and theoretical aspects of FPGA architecture, CAD algorithms for using 
and testing FPGAs, and applications. The Symposium will be of interest 
to those developing FPGA architectures, both at the chip and board level, 
and those developing CAD algorithms for FPGAs. The Symposium is not of direct 
interest to immediate users of FPGAs.

General Chair: 	Jonathan Rose, University of Toronto
Program Chair: 	Carl Ebeling, University of Washington
Publicity Chair: 	Jason Cong, UCLA
Local Chair: 	Pak Chan, UC Santa Cruz
Finance Chair: 	Steve Trimberger, Xilinx

 Program Committee
Michael Butts, Quickturn
Pak K. Chan, UCSC
Paul Chow, U. Toronto
Jason Cong, UCLA
Ewald Detjens, Mentor
Carl Ebeling, U. Washington
Gareth Jones, Pilkington
Dwight Hill, Synopsys
Brad Hutchings, BYU
Sinan Kaptanoglu, Actel
Jonathan Rose, U. Toronto
Richard Rudell, Synopsys
Rob Rutenbar, CMU
Takayasu Sakurai, Toshiba
Martine Schlag, UCSC
Tim Southgate, Altera
Steve Trimberger, Xilinx
Nam-Sung Woo, ATT

Program Sunday February 11, 1996

6:00pm	Registration

7:00pm	Welcoming Reception, 
	Monterey Beach Hotel, Monterey

Monday February 12, 1996

7:30am	Continental Breakfast/Registration

8:20am	Opening Remarks

Session 1: Novel FPGA Architectures 

Chair: Jonathan Rose, University of Toronto

8:30am	Hybrid FPGA Architecture, 
	A. Kaviani and S. Brown, University of Toronto

8:50am	Plasma:	 An FPGA for Million Gate Systems, 
	V.R. Amerson, R. Carter, W. Culbertson, 
	P. Kuekes, G. Snider, L. Albertson, HP Labs

9:10am	Flexible FPGA Architecture Realized of General 
	Purpose Sea of Gates, K. Azegami, S. Kashi-
	wakura, K. Yamashita, Fujitsu Laboratories

Posters: Novel FPGA Architectures

9:30-10:30am Coffee & Posters	

Session 2: Logic Module Design

Chair: Richard Rudell, Synopsys

10:30am Using BDDs to Design ULMs for FPGAs, 
	Z. Zilic and Z.G. Vranesic, University of Toronto

10:50am Series-Parallel Functions and FPGA Logic 
	Module Design, 
	S. Thakur, D.F. Wong, University of Texas, Austin

11:10am Combined Spectral Techniques for Boolean 
	Matching, E. Schubert, W. Rosenstiel, University 
	of Tuebingen

Posters: Logic Module Design 11:30-12:00

LUNCH 12:00 - 1:30

Session 3: Performance Issues

Chair: Steve Trimberger, Xilinx

1:30pm  The Wave Pipeline Effect on LUT-Based FPGA 
	Architectures, E.I. Boemo, S. Lopez-Buedo, 
	J.M. Meneses, Universidad Politecnica de Madrid

1:50pm  Timing Optimization for Hierarchical Field-
	Programmable Gate Arrays, 
	V.C. Chan, D.M. Lewis, University of Toronto

2:10pm  Technology Mapping of Sequential Circuits for 
	LUT-Based FPGAs for Performance, 
	P. Pan, C.L. Liu, Clarkson University

Posters: Performance Issues

2:30-3:30pm Coffee & Posters

Session 4: Theoretical Issues in Routing Architectures

Chair: Jason Cong, UCLA

3:30pm  A Method for Generating Random Circuits and 
	Its Application to Routability Measurement, 
	J. Darnauer and W.W-M. Dai, University of 
	California, Santa Cruz

3:50pm  Entropy, Counting, and Programmable 
	Interconnect, A. DeHon, MIT

4:10pm  Universal Switch Modules for FPGA Design, 
	Y-W. Chang, D.F. Wong, C.K. Wong, University of 
	Texas, Austin

Posters: Theoretical Issues in Routing Architectures

4:30-6:00pm Free time/Posters

Dinner 6:00-7:30pm

7:30-9:00pm  PANEL 
	     FPGAs vs. Gate Arrays and Processors: Who Will Win?

The FPGA industry has enjoyed rapid growth in the past ten 
years in terms of chip density and speed as well as ASIC 
market share. In the same period, however, we have also 
observed significant advances in all sectors of the semi-
conductor industry -- state-of-the-art gate arrays have a 
capacity of over 10 million transistors and enable the 
`system-on-a-chip'. Design automation tools have made 
semi-custom designs much faster and easier to achieve while 
yielding both high density and high performance. High-end 
microprocessors have reached over 250 Mhz and can satisfy 
the needs of many real-time control and DSP/multi-media 
applications. New rapid prototyping technologies, such as 
laser-programmed gate arrays, have emerged for high-speed 
high-density prototyping.

Given such a dynamic industry undergoing exponential 
growth, it is interesting to ask where FPGAs will stand five 
or ten years from now in the wide spectrum of design 
technologies. Will its share of the ASIC market continue to 
increase, or will it become more of a niche technology? It is 
likely that the relative importance of these technologies will 
change drastically over the next five to ten years.

This panel comprises technology experts in the competing 
areas of FPGAs, gate arrays, processors and other 
technologies. They will focus on the technological and 
economic issues that give one implementation medium an 
advantage over others and discuss how new technologies and 
architectural developments may change the competitive 
balance. They will discuss the past, present and future of the 
technological forces driving the industry and debate where 
those forces are likely to take us in the future.

Tuesday February 13, 1996

Session 5a: Field-Programmable Analog Arrays

Chair: Paul Chow, University of Toronto

8:30am  Design and Implementation of a Field- 
	Programmable Analogue Array, A. Bratt and 
	I. Macbeth, Pilkington Microelectronics

8:50am  The EPAC Architecture: An Expert Cell
	Approach to Field-Programmable Analog 
	Arrays, H.W. Klein, IMP

Posters: Field-Programmable Analog Arrays

9:10-9:40am Coffee & Posters

Session 5b: Testing

Chair: Martine Schlag, UC Santa Cruz

9:40am  Diagnosing Programmable Interconnect Systems 
	for FPGAs, D. Ashen and F. Lombardi, 
	Texas A&M University

10:10am Evaluation of FPGA Resources for Built-In Self-
	Test of Programmable Logic Blocks, 
	C. Stroud, P. Chen, S. Konala, M. Abramovici, 
	University of Kentucky

Posters: Testing

10:30-11:00am Coffee & Posters

Session 6: The Future of Fuse and SRAM FPGA Technologies

Chair: Tim Southgate, Altera

11:00am Two invited speakers will present the state of the 
	art in (anti-)fuse and SRAM technologies and 
	discuss the impact of recent developments in 
	these technologies on future architectures.

Posters: FPGA Vendors 11:40-12:00 

LUNCH 12:00 - 1:30

Session 7: Applications

Chair: Dwight Hill, Synopsys

1:30pm  DPGA Utilization and Application, 
	A. DeHon, MIT

1:50pm  Integrating Software with Run-Time Re-
	configured Hardware, M.J. Wirthlin and B.L. 
	Hutchings, Brigham Young University

2:10pm  Computing the Discrete Fourier Transform on 
	Virtual Systolic Arrays, 
	C. Dick, La Trobe University

Posters: Applications

2:30-3:30pm Coffee & Posters 

Session 8: Design Systems

Chair: Pak Chan, UC Santa Cruz

3:30pm	RASP: A General Logic Synthesis System for 
	SRAM-based FPGAs, J. Cong, J. Peck, UCLA, and 
	Eugene Ding, AT&T Bell Laboratories.

3:50pm  Emerald - An Architecture-Driven Tool Compiler 
	for FPGAs, D. Cronquist and L. McMurchie, 
	University of Washington

4:10pm  Structured Design Implementation - A Strategy 
	for Implementing Regular Datapaths on FPGAs, 
	A. Koch, Technical University, Braunschweig

Posters: Design Systems 4:30-5:00

5:00pm Symposium Ends.

		Hotel Information
		-----------------

The Symposium will be held at the Monterey Beach Hotel, 
2600 Sand Dunes Dr., Monterey, CA 93940, USA. The 
phone number for room reservations is 1-800-242-8627 or 
+1-408-394-3321 (Fax +1-408-393-1912). Reservations 
must be made before January 6, 1996. Identify yourself 
with the group Association for Computing Machinery 
FPGA `96 Symposium to receive the special Symposium 
rates, which are $75 for single or double Gardenview and 
$105 for single/double Oceanview. Parking is free. Check-
in time 4pm.

Directions to Hotel: From San Jose (a 1.5 hour trip) or 
San Francisco Airport (2.5 hrs) take HWY 101 South to 
HWY 156 West to HWY 1 South. On HWY 1 South, take 
Seaside/Del Rey Oaks exit. The hotel is at this exit, on the 
ocean side.

You can also fly directly to the Monterey Airport, which is 
served by United, American and other airlines with at least 
8 flights per day.

FPGA `96 REGISTRATION 
---------------------

The Symposium registration fee includes a copy of the symposium proceedings, 
a reception on Sunday evening, February 11, coffee breaks, lunch on both days, 
and dinner Monday evening, February 12.


First Name:___________________________________________
Last Name:____________________________________________
Company/Institution___________________________________
Address:______________________________________________

City:___________________State:________________________
Postal Code:_______________Country:____________________

Email:__________________________________________________
Phone:_______________________Fax:_______________________


ACM Member #____________
Circle Fee:   Before January 25, 1996  	After January 25, 1996 

ACM/SIGDA Member  	US $320    		US $390

*Non-Member 		US $420 		US $490

Student 		US $90			US $90 
(does not include reception or banquet, available for $20 and $35 respectively)

*If you are not an ACM/SIGDA member we are giving you the opportunity to 
join by paying your first year's dues out of your conference non-member 
registration fee -- a US$100 value. Forms will be available at on-site 
registration.

Guest Reception Tickets #Tickets______x US $20 ______
Guest Banquet Tickets #Tickets______x US $35 ______

Total Fees:____________________(Make checks payable to ACM/FPGA'96)

Payment Form (Circle One): AMEX   MASTERCARD  VISA   CHECK

Credit Card#:____________________________________
Exp. Date:_______________________________________
Signature:_______________________________________

Send Registration with payment to:

 FPGA `96 - Colleen Matteis, 
 553 Monroe St., 
 Santa Clara, CA. 95050, 
 USA. 

 Phone: +1(408)296-6883 Fax: +1(408)985-8274.

For registration information contact Colleen Matteis, 
e-mail: sigda@nextwave.com, or cmatteis@aol.com. 
Cancellation must be in writing, and received by Colleen Matteis 
before January 24,1996.



Article: 2577
Subject: Advanced Program & Registration For SNUG '96
From: jcooley@world.std.com (John Cooley)
Date: Fri, 5 Jan 1996 05:33:57 GMT
Links: << >>  << T >>  << A >>

      !!!     "It's not a BUG,                     jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                           (508) 429-4357
    (  >  )
     \ - /         Advanced Program & Registration For SNUG '96
     _] [_    

  [ Here's the advanced schedule for the upcoming Synopsys User's Group 
    meeting in San Jose, California from Feb 21-23.  It's a pretty good
    conference for Synopsys users to attend because no Synopsys sales 
    or marketing staff are allowed to attend (so it's not a thinly 
    disguised sales pitch.)  What you will find are fellow Synopsys 
    users, Synopsys R&D and technical support people, and the Synopsys
    bigwigs.  The emphasis is on finding better ways to use Synopsys 
    software to get your job done via real user's experiences.  Also,
    in planning travel don't forget that OVI & VIUF are happening
    around the same time.  Hope to see ya'll there!      - John   ]


Schedule

Wednesday, February 21
  12:00 -  2:00  Tutorial registration
   2:00 -  5:00  Tutorial sessions
   5:00 -  7:00  Welcoming R&D cocktail party/Synopsys new product demos

Thursday, February 22
   7:30 -  9:00  General session registration/breakfast
   9:00 -  9:15  Welcome/agenda
   9:15 -  9:45  Synopsys Direction (Aart de Geus, President)
  10:00 - 11:30  Breakout sessions.
  11:45 -  1:00  Lunch
   1:45 -  2:45  Breakout sessions.
   3:00 -  4:30  Breakout sessions.
   4:45 -  5:30  Keynote speaker
   5:45 -  6:00  Wrap-up
   6:00 -  8:00  Cocktail party/vendor fair

Friday, February 23
   7:00 -  8:00  Tutorial registration/breakfast
   8:00 - 11:30  Tutorial sessions



General Session: Thursday, February 22

User Breakout Sessions
These sessions are always the hit of the conference. Hear Synopsys users'
experience on specific topics. Each user breakout session will consist of
two presentations, thirty minutes each, with another thirty minutes for
questions and answers.

Preliminary topics include:

Design Productivity/Synthesis (A1)
Strategies, experiences and best practices for design productivity with an
emphasis on synthesis.  Automation techniques for synthesis.

Verification and Simulation (A2)
Verification strategies covering design for test and system level
verification. Users share experiences in developing a test bed to verify
the combined hardware and software systems.  Design for test strategies for
complex, large designs.

Design Reuse (B1)
This session includes a practical methodology for design reuse based on the
real world experience.  Issues and guidelines are explored.

Deep Submicron/Large Designs (B2)
Concentration on the unique challenges of submicron and large designs.
Sessions provide
experience with automating scripts for submicron, special techniques for
managing wire loading, floorplanning and non-linear delay modeling.

Higher Levels of Abstraction (C1)
Synopsys users cover a variety of designs using COSSAP and Behavioral
Compiler. Special interest on COSSAP behavioral code generation and the
interface to Behavioral Compiler. Shared experience on the transition to
your first behavioral design with Behavioral Compiler.

Design Productivity Replay (C2)
Repeat presentation from last year's most popular sessions. Added by users
request.

Semiconductor Vendor Sessions (B3 & C3)
Back by popular demand! Feedback from last year's sessions was very
popular. This year we will repeat last year's format with two sessions.
This gives you an opportunity to hear about the latest technologies
available from the semiconductor vendors and their recommended customer
design flow using Synopsys tools.

Synopsys Partner Presentations (B4 & C4)
These sessions have a format similar to the semiconductor sessions. They
are an opportunity to see other EDA vendors show how they can help you
leverage your high-level design tools from Synopsys



Half-Day Tutorials: Wednesday, February 21

Behavioral Synthesis Using VHDL (W1)
For any synthesis user interested in making the transition to the next
generation design paradigm.  Behavioral synthesis offers a higher level of
abstraction for increasingly complex, data-intensive, algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal architecture.
Content is the same as the tutorial on Friday, but examples are presented
in VHDL.

Get High Performance Source Using HDL Advisor (W2) (new for SNUG'96)
You can meet your aggressive timing or area goals using HDL Advisor.
Understand why the quality of your source is important and how HDL Advisor
helps you determine quality of source.  Learn the concepts behind "logic
levels", "component count" and "Selection Inspector".

Learn how experienced designers have used HDL Advisor to meet their
critical timing and area needs.

VHDL Synthesis Techniques and Recommendations (W3)
Back by popular demand and updated with lots of new material, this tutorial
will present a wide range of VHDL synthesis coding styles and issues.
Caveats based on real-world VHDL synthesis models will be explored in full
detail. Topics will be presented in the following areas: VHDL synthesis
fundamentals, importance of VHDL coding styles, relying on hardware design
experiences, disparities between efficient simulation models and optimum
synthesized hardware, potential simulation and synthesis mismatches, and
VHDL coding style differences between targeted CMOS, ECL, and FPGA
technologies.



Half-Day Tutorials: Friday, February 23

Behavioral Synthesis Using Verilog (F1)
For any synthesis user interested in making the transition to the next
generation design paradigm.  Behavioral synthesis offers a higher level of
abstraction for increasingly complex, data-intensive, algorithmic
applications. This tutorial will show you how to enter your design
specifications at the behavioral level and use Behavioral Compiler to
explore implementation alternatives and determine the optimal architecture.
Content is the same as the tutorial on Wednesday, but examples are
presented in Verilog.

Test Synthesis Methodology (F2) (new for SNUG'96)
An intermediate presentation of Design For Test techniques and issues using
Test Compiler. This session assumes a basic knowledge of Test Compiler and
test design practices. Scan insertion, JTAG synthesis, design rule checking
and custom test protocols will be addressed. Also valuable insight on
debugging techniques learned by Synopsys Design Application Engineers.

DSP Design Techniques Using COSSAP (F3)
This session provides a language independent crash course on DSP topics. It
provides a good overview of DSP issues and provides an overview of the
COSSAP design methodology to solve these issues. This session is intended
for the designer who is new to using EDA tools for solving DSP
applications. It is not intended for the designer who is proficient in the
use of the COSSAP tools.



Registration Information

Advance Registration

                     Call 1-800-344-SNUG

                           ~ OR ~

       Register by Mail
       Complete and print registration form and mail it with your 
       check or credit card
       information to:

                    Synopsys
                    Attention: SNUG
                    PO Box 310
                    Beaverton, OR 97075-0310

       Please complete a separate registration form for each attendee.
Specify breakout sessions for Thursday, and your choice(s) of tutorials.


----------------------------------------------------------------------

General Session Registration
Registration includes all materials for the general and breakout sessions.

Due to limited space, breakout session sign-up will be done on a
first-come-first-serve basis. Both cocktail parties, breakfasts on Thursday
and Friday, and the Thursday lunch are included.

Tutorial Session Registrations
Registration for each tutorial includes the session and all related course
material. Tutorials are available only to general session registrants.
Space is limited - register early!

Early Registration Drawing!
Register early and you become eligible to win a Macintosh laptop! To
qualify for the drawing and to receive the discount rate, your registration
must be received by January 19, 1996. Registrations received after January
19 will not be eligible for the drawing or discount rates.

General Session Registration Fees
Early registration -- $100.00
Late registration -- $150.00

Tutorial Registration Fees (per session)
Early registration -- $50.00 each
Late registration -- $75.00 each

Full payment in U.S. dollars must accompany registration. Company and
personal check, VISA, Master Card, and American Express card are accepted.
All checks must be made payable to the Synopsys Users Group.

Cancellations/Refunds
A letter of cancellation must be received 7 days prior to the beginning of
the conference to qualify for a refund.



Housing/Travel

Lodging
SNUG attendees receive a special nightly rate of $110 single, $120 double,
$135 Concierge single, $145 Concierge double rate at the Red Lion Hotel San
Jose. Reservations must be made twenty-one (21) days prior to arrival and
should be guaranteed with a major credit card. Call (408) 453-4000 to make
your reservation; be sure to identify yourself as part of the Synopsys
Users Group to receive these discounted rates. Reservations made after
January 29, 1996 will be on a space and rate availability only.

Air Travel
Synopsys has negotiated an American Airlines discount for SNUG attendees.
This contract allows for travel as early as 2/16 returning as late as 2/26.
You will receive 5% off the lowest available fare or 10% off if the ticket
is purchased seven (7) days in advance. A Saturday night stay-over will
increase your savings. When you or your travel agent make reservations be
sure to give the American Airlines' group code STAR No. S 3326MD to receive
the discount. Castro Travel, Synopsys' contract agency, can assist you with
air travel arrangements. Please contact them at (415) 694-1788 or fax (415)
694-1791

Car Rental
Hertz has been appointed the official car rental company for SNUG '96. Cars
will be available at San Jose, San Francisco, and Oakland airports. Special
discounted rates range from $26.99/day with Saturday night keep for a Class
A Compact car to $41.99/day for a Class F Full-size 4-door car, and
$146.99/week to $186.99/week . All rates include unlimited mileage and are
guaranteed one week before through one week after the actual meeting dates,
subject to car availability.  Insurance is optional at $9/day at San Jose
airport. When you or your travel agent make reservations, call Hertz at
(800) 654-2240. Be sure to give the Hertz/SNUG ID number CV#20103 to obtain
the special rates.

===========================================================================
 Trapped trying to figure out a Synopsys bug?  Want to hear how 3881 other
 users dealt with it ?  Then join the E-Mail Synopsys Users Group (ESNUG)!
 
      !!!     "It's not a BUG,               jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                 (508) 429-4357
    (  >  )
     \ - /     - John Cooley, EDA & ASIC Design Consultant in Synopsys,
     _] [_         Verilog, VHDL and numerous Design Methodologies.

     Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222
   Legal Disclaimer: "As always, anything said here is only opinion."


Article: 2578
Subject: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
From: jcooley@world.std.com (John Cooley)
Date: Fri, 5 Jan 1996 05:41:40 GMT
Links: << >>  << T >>  << A >>

      !!!     "It's not a BUG,                        jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                              (508) 429-4357
    (  >  )
     \ - /       INDUSTRY GADFLY: Speedsim's Three Dark Clouds
     _] [_          
                      by John Cooley, EE Times Columnist

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222

  A few months back in my DAC review I wrote about SpeedSim, a small start-up
selling a very fast cycle based Verilog simulator as being under dark
clouds.  Because of all of the interest in cycle based simulators, to this
day I'm still getting pelted with e-mails asking me to explain SpeedSim's
clouds.  No, they're not having questionable finances or anything -- in fact,
they're backed by the multi-billion dollar Fidelity Investments with pockets
deep enough to see them through any minor cash flow problems.  Nor is
SpeedSim's product grossly flawed in any way that I could see from their
impressive demo.  As usual, the story is a little more complicated...

  It all began back in 1991 when an ex-publisher of the now defunct "VLSI
Design" magazine (Doug Fairbairn) and one of the founders of the ASIC house
VLSI Technology, Inc. (again Doug Fairbairn) and one of the founders of
Compass Design Automation (once again Doug Fairbairn) founded Redwood Design
Automation, Inc as its CEO.  For two years Doug's staff feverishly worked
away from prying eyes.  Then in 1993 Doug publically pitched that his new
company's product was getting 1000 times faster Verilog/VHDL simulation runs,
it was going to change the way design was done, and Redwood *was* the wave of
the EDA future.  Doug was even scheduled to give the keynote address at the
1994 DAC.  Why all the hoopla?  Because he had new approach in offering a
cycle based Verilog/VHDL simulator (albeit wrapped up in a funky object
oriented framework that most people didn't quite fully understand) which did
make for what appeared on the surface to be rather impressive demos.

  The two classic company-killers that Redwood then ran into were development
issues and the fact they couldn't find paying customers.  As a consequence,
Redwood, the "wave of the EDA future", ended up being sold at a bargain
basement price to Cadence the week before Doug gave his keynote address at
that 1994 DAC in San Diego.

  The one residual effect Redwood's splash made on the EDA buying and selling
communities was a sudden new interest in the extremely high performance cycle
based simulators could provide.  Hence, very quietly in Decemeber '93 in
Westford, Massachusetts, SpeedSim was born.  And in March at the recent
International Verilog Conference, SpeedSim finally delivered on Redwood's
promise by announcing a Verilog cycle based simulator available immediately
at $35,000 as a floating licence product.

  You may be thinking: "Hey, John, it looks like these guys have deep pockets
backing them financially and an actual working product.  Where's the dark
clouds???"  The catch is that SpeedSim wasn't the only one noticing Redwood's
technological impact.  The CEO of Synopsys, Aart De Geus, still smarting from
his failed attempt to buy Chronologic (and thus spoiling his opportunity to
offer his customers a very sexy high speed Verilog simulator which would have
gone rather nicely with his market dominant synthesis tools) openly said at
the Synopsys Users Group conference 3 days before SpeedSim's debute: "expect
something in a cycle based simulator from Synopsys later this year."  (Most
everyone suspects it will be offered in both Verilog and VHDL flavors.)
Along the same lines, the CEO of Cadence, Joe Costello, recently announced
at his conference in Japan that Cadence Berkeley Labs will be releasing
a cycled based simulator in Q4 of 95.  Joe claimed it's supposedly 50
times faster than "other cycle based simulators" (which is CEO-speak for
SpeedSim because they're the only one on the market) due to Cadence's
"breakthrough" Multivalued Decision Diagrams technology.  Not to left out,
ViewLogic's CEO, Alain Hanover, also annouced that *they* were working on
a cycle based simulator, too!

  Despite Joe's "breakthrough technology", SpeedSim's "dark clouds" are
neither technical nor financial; they're in having to compete against three
vast, walking, talking corporate propaganda machines which Synopsys, Cadence
and ViewLogic colloquially refer to as their "sales, marketing and
applications staffs."  EDA customers tend to buy $100,000 software packages
from EDA vendors who can satisfactorily answer every one of their own
technically involved questions, issues and benchmarks.  Having a well
deployed army of hustling on-site salesdroids to schmooze customers
one-on-one is a serious business advantage here.

  Although the 12 employee SpeedSim is literally outnumbered over 300 to 1,
it doesn't daunt them.  "I would have loved to have this market to myself but
it was inevitable that the big players would jump in.  It's easy for these
guys to make promises.  We're delivering real product today.  Benchmark us!"
replies Kevin Ladd, technical founder and chairman of SpeedSim's board.
(Kevin's value-add is that he worked on DEC's internal cycle based simulators
"presto" and "chango" for 10 years.)  "Our number one advantage is the
ability to handle a wide variety of design and clocking schemes because we
ran into them years ago while working on cycle based simulation at DEC.
Latch vs. flop designs, gated clocks, multi-clock schemes, asynchronous
logic, and gate level designs are just some of the gotchas.  There are plenty
more.  And this is where we excel."

  Ironically, SpeedSim's weakness can also be its strength.  By being small
they can readily adapt to customer requests, fix bugs quickly and there's
very few layers of bureaucracy in 12 employee companies.  As a customer you
can readily talk with the guy who wrote the software when things don't
work quite right.  (Just try this with Synopsys, Cadence or ViewLogic after
the sale is made -- especially if you're not a "big" customer like Sun
Microsystems, Silicon Graphics, HP or IBM!)

--------
          
John Cooley runs the grassroots E-mail Synopsys Users Group (ESNUG), is
president of the Users Society of Electronic Design Automation (USE/DA), and
makes his living as an independent contract ASIC/FPGA designer.  He loves
receiving e-mail from fellow engineers at "jcooley@world.std.com" or phone
(508) 429-4357.            [ Copyright 1995 CMP/EE Times Publications ]



Article: 2579
Subject: Need Re-programable VXI Module
From: Dan Blow <blow>
Date: 5 Jan 1996 18:06:38 GMT
Links: << >>  << T >>  << A >>
I have a need for a re-programable module to be used in the implementation of
VXI based test sets.  The module would need to accept program data from the VXI
interface and provide prewired addressing and data bus interfaces between the
module FPGA('s) and the VXI bus.  The remainder of the pins on the FPGA('s)
would be wired to connectors on the front of the module to be used in
transmiting to, or receiving data from the unit under test.  The module needs
to have about 128 I/O pins.

Does any one know of such a device, or would anyone be intrested in designing
and building a module of this type.  My current needs are for 3 to 5 modules.



Article: 2580
Subject: Xilinx Power Estimation
From: djevans@bnr.ca (David Evans)
Date: 5 Jan 1996 18:44:21 GMT
Links: << >>  << T >>  << A >>
I know I've seen this come up before in this group but (of course)
I was at the back of the class and not paying attention....Is anyone
aware of a program which will take an XNF + typical toggle rates
and spit out a ballpark power consumption number?

Thanks a lot
 

-- 
-------------------------------------------------------------------------
David J. Evans      | I'm a little pea             |  email::djevans@bnr.ca
H/W Design Engineer | I love the sky and the trees |  phone::esn393.6742
Magellan Passport   | I'm a teeny tiny--little ant |  fax > /dev/null
ATM Hardware        | checkin' out this and that   |  bnr.say != me.say 


Article: 2581
Subject: ** Reminder: USE/DA Lunch Meeting In Silicon Valley On Monday **
From: jcooley@world.std.com (John Cooley)
Date: Fri, 5 Jan 1996 22:01:39 GMT
Links: << >>  << T >>  << A >>

   Next Monday, Jan. 8th, for those who happen to be in Silicon Valley, we'll
be having an informal meeting of the User's Society of Electronic Design
Automation (USE/DA) over lunch at Synopsys on from 11:30 to 1:00.  (Synopsys
is located at 700 E. Middlefield Road off of 237 in Mountain View.)  Since 
this is a last minute reminder, if you want to join us, please RSVP to 
"karenb@synopsys.com" *before* 8:AM Jan. 8th so we can get an accurate 
headcount for sandwiches.

   USE/DA's goal is to make sure that the viewpoint of the day-to-day EDA 
using electronics design engineer is represented in places where the decisions
that effect us are being made.

   If you can't join us for lunch, subscribe to USE/DA's free monthly e-mail
newsletter at "useda-subscribe@netcom.com" or, if you're a web junkie, try
"http://www.useda.org/useda.html".

                     - John Cooley, President
                       User's Society for Electronic Design Automation

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer


Article: 2582
Subject: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
From: ram@shukra.Eng.Sun.COM (Renu Raman)
Date: 6 Jan 1996 02:33:40 GMT
Links: << >>  << T >>  << A >>
>  It all began back in 1991 when an ex-publisher of the now defunct "VLSI
>Design" magazine (Doug Fairbairn) and one of the founders of the ASIC house
>VLSI Technology, Inc. (again Doug Fairbairn) and one of the founders of
>Compass Design Automation (once again Doug Fairbairn) founded Redwood Design
>Automation, Inc as its CEO.  For two years Doug's staff feverishly worked
>away from prying eyes.  Then in 1993 Doug publically pitched that his new
>company's product was getting 1000 times faster Verilog/VHDL simulation runs,
>it was going to change the way design was done, and Redwood *was* the wave of
>the EDA future.  Doug was even scheduled to give the keynote address at the
>1994 DAC.  Why all the hoopla?  Because he had new approach in offering a
>cycle based Verilog/VHDL simulator (albeit wrapped up in a funky object
>oriented framework that most people didn't quite fully understand) which did
>make for what appeared on the surface to be rather impressive demos.
>
>  The two classic company-killers that Redwood then ran into were development
>issues and the fact they couldn't find paying customers.  As a consequence,
>Redwood, the "wave of the EDA future", ended up being sold at a bargain
>basement price to Cadence the week before Doug gave his keynote address at
>that 1994 DAC in San Diego.
>
>  The one residual effect Redwood's splash made on the EDA buying and selling
>communities was a sudden new interest in the extremely high performance cycle
>based simulators could provide.  Hence, very quietly in Decemeber '93 in
>Westford, Massachusetts, SpeedSim was born.  And in March at the recent
>International Verilog Conference, SpeedSim finally delivered on Redwood's
>promise by announcing a Verilog cycle based simulator available immediately
>at $35,000 as a floating licence product.

History may have been re-written here. I think Cycle Based Simulators (CBS)
are not a new idea and has been in the interest for most large scale
synchronous system design. It became more relevant to the commmercial
space, when gate densities crossed the 100K mark and which happened in
the early 1990s. Verilog - interpreted and compiled simulators were
OK until the knee of the simulation speed requirement hit the broader market.

>  Despite Joe's "breakthrough technology", SpeedSim's "dark clouds" are
>neither technical nor financial; they're in having to compete against three
>vast, walking, talking corporate propaganda machines which Synopsys, Cadence
>and ViewLogic colloquially refer to as their "sales, marketing and
>applications staffs."  EDA customers tend to buy $100,000 software packages
>from EDA vendors who can satisfactorily answer every one of their own
>technically involved questions, issues and benchmarks.  Having a well
>deployed army of hustling on-site salesdroids to schmooze customers
>one-on-one is a serious business advantage here.

True - but a company like Sun - which has a large EDA budget has over
the last 10 years consistently relied and enabled small companies
including 1-10 people startups doing key EDA tools as a way to get
critical EDA tools instead of deploying a large EDA development team inhouse.
This model has worked fairly well to the extent that we have on occasions
encouraged and enabled small companies - e.g. include Parsec which did
the Pearl timing analyzer later bought by cadence and numerours others.

And we continue to deploy this model eschewing large CAD development teams
like other microprocessor design teams have at IBM, INTEL, DEC. HP used
to have, which is now reducing, I believe.

I don't see this article of any relevance to comp.arch other than maybe
fast simulators are coming down the pike, which we all need. I do agree
speedsim is probably one among the cream of the crop.

Other CBS that I know are DEC (quoted here), IBM (many including Maxsim)
and NEWT at SGI.

>John Cooley runs the grassroots E-mail Synopsys Users Group (ESNUG), is
-- 
--------------------------------
   Renukanthan Raman				Internet:renu.raman@Eng.Sun.COM
   M/S USUN02-301, 2500 Garcia Avenue,          Tel :408-774-8299
   Sun Microsystems, Mt. View,  CA 94043


Article: 2583
Subject: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
From: jcooley@world.std.com (John Cooley)
Date: Sat, 6 Jan 1996 06:59:59 GMT
Links: << >>  << T >>  << A >>
John Cooley <jcooley@world.std.com> wrote:
>  The one residual effect Redwood's splash made on the EDA buying and selling
>communities was a sudden new interest in the extremely high performance cycle
>based simulators could provide.  Hence, very quietly in Decemeber '93 in
>Westford, Massachusetts, SpeedSim was born.  And in March at the recent
>International Verilog Conference, SpeedSim finally delivered on Redwood's
>promise by announcing a Verilog cycle based simulator available immediately
>at $35,000 as a floating licence product.

Renu Raman <ram@shukra.Eng.Sun.COM> wrote:
>History may have been re-written here. I think Cycle Based Simulators (CBS)
>are not a new idea and has been in the interest for most large scale
>synchronous system design. It became more relevant to the commmercial
>space, when gate densities crossed the 100K mark and which happened in
>the early 1990s. Verilog - interpreted and compiled simulators were
>OK until the knee of the simulation speed requirement hit the broader market.

Renu, I think you're missing the point of the whole article: I *wasn't*
claiming cycle-based simulators were a new idea (in fact I even later mentioned
how SpeedSim's origins came from years of work at DEC) but that cycle-based
simulators were new for the *commercial* EDA market.  Prior to Redwood, I
know of no other company that tried to commercially market a cycle-based
simulator -- all cycle based simulators were developed as in-house,
proprietary software used *soley* by the same computer manufacturer who 
created it.   Redwood's hoopla, IMHO, changed all this.


>True - but a company like Sun - which has a large EDA budget has over
>the last 10 years consistently relied and enabled small companies
>including 1-10 people startups doing key EDA tools as a way to get
>critical EDA tools instead of deploying a large EDA development team inhouse.
>This model has worked fairly well to the extent that we have on occasions
>encouraged and enabled small companies - e.g. include Parsec which did
>the Pearl timing analyzer later bought by cadence and numerours others.

As someone who's not employed at Sun, I'm glad that Sun does this.  It helps
advance the state of the art in EDA tools such that everyone (Sun, other
users, and the innovative EDA companies) benefits.  It encourages benefitial
R&D to happen instead of chummy sales accounts and more of the same-old,
same-old.  The only minor danger here is to view the large EDA companies as
being dinosaurs by definition.  I think it's better to reward specific
products & tools you like reguardless of who makes them (big company or
small) to get the maximum bang for your buying buck.  Check out Mentor.
Sure they have quite a collection of rather old tools -- but they also have
one of the better sets of test products available.  (OK, so they had to get
this by buying it back -- but at least they, big old MENTOR, were savvy
enough to add it as part of their own product offering.)

                                            - John Cooley

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer


Article: 2584
Subject: Re: [q][Reverse Engineering Protection]
From: jcooley@world.std.com (John Cooley)
Date: Sat, 6 Jan 1996 07:22:58 GMT
Links: << >>  << T >>  << A >>
John Cooley <jcooley@world.std.com> wrote:
>Jyri, one clever idea for protecting designs in chips I heard of was
>using Xilinx FPGA's that were programmed once at the factory with a
>small battery attached after programing.  (That is, the power-up
>program for the Xilinx part was NOT included in the PCB.)  What this
>did was make the circuit unreversable but still functional.

R. D. Davis <rdd@access1.digex.net> wrote:
>Such designs should only be used for top-secret military type
>equipment, never for equipment sold for commercial or consumer use.
>Anyone who designs such equipment for commercial or cosumer use is a
>creep and an idiot.  My reasoning is that after some number of years,
>someone who PAID for this equipment may wish to cotinue using it, and
>may want to try to repair it.  
>
>R. D. Davis  *  http://www.access.digex.net/~rdd    \Computer preservationist
>Home: +1 410 744-7964 * Eccentrics have more fun! :-)\Unwanted systems gladly
>Unconventional Computer Consulting & PERQ Software,   \disassembled, removed 
>divs. of Transpower Industries, Inc. +1 410 744-4900  \for free and preserved

R.D., I thought you were taking a bit of an unusual approach until I saw in
your sig that you were a Computer Preservationist.  I have a good friend at
M.I.T. who's also into the same hobby/lifestyle and he sports similar
opinions.  My counter arguement is that the company selling the product
usually doesn't have the economic luxary of letting their designs become
compromised.  Despite my design engineering bias, I clearly see that any
technological company's livlihood depends not on clever designs as much
as being able to capitalize on the few unique ideas incorporated in these
designs -- otherwise the some Pacific Rim company will get all the profits
of this research.  Let's see... I've heard that you can buy a complete
suite of Cadence and ViewLogic tools for $10.00 in China.  In Russia, OrCAD's
a very widely used tool yet I dare you to see *any* Russian sales listed in
OrCAD's Annual Report.  You may not win the reverse engineering war, but it's
critical to try to!
                                           - John Cooley

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer


Article: 2585
Subject: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
From: jcooley@world.std.com (John Cooley)
Date: Sat, 6 Jan 1996 23:40:50 GMT
Links: << >>  << T >>  << A >>
Renu Raman <ram@shukra.Eng.Sun.COM> wrote:
>I do agree speedsim is probably one among the cream of the crop.

I just wanted to clarify that I wasn't claiming that SpeedSim is the
best or the worst or even in between -- I was just commenting they were
the first viable commercial cycle-based simulator on the market.  (I
know it sounds nitpicking but I just don't want my name endorsing any
product without having done some serious technical due diligence on
my own.  I haven't really looked at, much less used, all of the cycle-based
simulators yet, so I'm very conspicously reserving making any judgements
on them until then.)
                                        - John Cooley

-----------------------------------------------------------------------------
  __))  "Glass ceilings? Name ANY goat farmer who's made it into management!"
 /_ oo  
  (_ \   Holliston Poor Farm                                   - John Cooley
%//  \"  Holliston, MA 01746-6222              part time Sheep & Goat Farmer
%%%  $   jcooley@world.std.com       full time contract ASIC & FPGA Designer


Article: 2586
Subject: Re: Career value: VHDL or Verilog?
From: Jan Decaluwe <jand@easics.be>
Date: Sun, 07 Jan 1996 18:45:36 +0100
Links: << >>  << T >>  << A >>
Ken Wood wrote:

> 
> Assembler <--> schematic capture: Gives the fastest & tightest 
> results for small, human-managable blocks. Least portable.
> 

The analogy is attractive & obvious but I don't believe it is fully
correct. A product like Synopsys VHDL/Verilog compiler may be similar 
to a C compiler in software design. However, what then about
Design Compiler? Shouldn't we view that as a tool that converts
"assembler" (possibly human-designed) into a better "assembler"? 
I don't know whether there are similar tools in software design,
but I do know that Design Compiler does an outstanding job which
would be difficult if not impossible to match by human designers.

Note also that the very option to partition the design into
"small, human-managable" blocks is usually very far from optimal.
I am never interested in the fastest or tightest sub-block, but
always in the fastest or tightest top design. That it would be
better to partition the design heavily into very small blocks
to achieve those goals is just one of these myths. The opposite
is true, within limits as always.

Apparently there is still a need to use assembler in software
design. However, I don't believe that there is still a real need
for schematic entry at the gate level in hardware design.

-- 
===================================================================
Jan Decaluwe              ===              Easics               ===
Design Manager            ===  VHDL-based ASIC design services  ===
E-mail: jand@easics.be       ===================================
Tel: +32-16-298 400
Fax: +32-16-298 319         Kapeldreef 60, B-3001 Leuven, BELGIUM


Article: 2587
Subject: Re: Need Re-programable VXI Module
From: ganley@world.std.com (Timothy P. Ganley)
Date: Mon, 8 Jan 1996 19:03:37 GMT
Links: << >>  << T >>  << A >>
Dan Blow <blow> wrote:

>I have a need for a re-programable module to be used in the implementation of
>VXI based test sets.  The module would need to accept program data from the VXI
>interface and provide prewired addressing and data bus interfaces between the
>module FPGA('s) and the VXI bus.  The remainder of the pins on the FPGA('s)
>would be wired to connectors on the front of the module to be used in
>transmiting to, or receiving data from the unit under test.  The module needs
>to have about 128 I/O pins.

>Does any one know of such a device, or would anyone be intrested in designing
>and building a module of this type.  My current needs are for 3 to 5 modules.


>From the preceding description and the December 21 posting I assume
that you are looking for a VXI Board with on-board connectors for
reprogrammable (FPGA based) modules.

I know of no vender that currently offers such a system.  I have
experience designing systems similar to this and may be interested in
building a module of this type.  Contact me so that your requirements
can be further asessed.

Tim Ganley
ganley@world.std.com



Article: 2588
Subject: Re: Career value: VHDL or Verilog?
From: biggs@qcktrn.com ( Tom Biggs )
Date: 9 Jan 1996 04:24:45 GMT
Links: << >>  << T >>  << A >>
In article cbr@sydney1.world.net, Ken Wood <ken@eda.com.au> writes:
> I agree with most of your comments, although I'd use a slightly different
> comparison when equating the hardware & software design models. I'd put:
> 
> 
> Assembler <--> schematic capture: Gives the fastest & tightest results for
> small, human-managable blocks. Least portable.
> 
> C <--> RTL VHDL or Verilog

The problem with this analogy is that assembly language, C, VHDL, and Verilog
are all 'word' based programming tools, whereas schematic capture is a visual
design tool. 

In fact, if you use hierarchical schematics it is possible to design at a
pretty high level with schematics. The flow control of a processor
drawn with multiplier, ALU, Mux, and memory blocks, etc, on a schematic is
much clearer than a lot of VHDL text. 

There are a number of design tools such as Escalade's that let you
design HDL code from visual block diagrams. So you could say that
the block diagrams are the high level approach and the HDL is the lower
level.

 As an aside, they say people either think in terms of images or words
 (There is an interesting experiment to this affect in the book "Surely
 You Must Be Joking Mr. Feynman" by the Nobel prize winning physicist),
 so the debate of which approach is better really depends on the person.
 There are visual software programming tools too. 
  
 In fact there are written languages based on phonetics (such as English), and 
 languages based on images (Chinese).  There are software menus that use words,
 others that use icons. But now I am really getting off the topic... ;)

     -tom





Article: 2589
Subject: Re: [q][Reverse Engineering Protection]
From: mojoteri@ix.netcom.com(Morris Jones)
Date: 9 Jan 1996 05:59:49 GMT
Links: << >>  << T >>  << A >>
In <DKr0IA.L0s@world.std.com> jcooley@world.std.com (John Cooley)
writes: 
>
>John Cooley <jcooley@world.std.com> wrote:
>>Jyri, one clever idea for protecting designs in chips I heard of was
>>using Xilinx FPGA's that were programmed once at the factory with a
>>small battery attached after programing.  (That is, the power-up
>>program for the Xilinx part was NOT included in the PCB.)  What this
>>did was make the circuit unreversable but still functional.
>
<snip>
Give Me a boring week with the E-beam prober, and it is easy to read!!!

Silicon is a pure substance, and any manufacturing done is easy to see.
The hardest to reverse are implant ROM's (Takes a sensitive hand on an
E-beam prober to see the threshold differences).  EPROMS, and RAMS can
easily be read with just a SEM and a little practice.  The so called
IBM reverse proof PS/2 chips full of black goop took less than a day to
deal with on a plasma etcher, and were easily reversed.

Most reversing is not done to obtain the design.  Good designers with
state of the art tools are much quicker at design.  It is done for
product documentation and to understand compatibility issues.

You really just have to keep the technology moving forward so that by
the time the other guy has reversed your product, it is obsolete. 
Otherwise, everyone will catch up with you.

my $.02

Mojo


Article: 2590
Subject: advanced program and registration for Async96
From: taubin@u-aizu.ac.jp (Alexander B. Taubin)
Date: 9 Jan 1996 06:06:01 GMT
Links: << >>  << T >>  << A >>
[Comp.parallel moderator: this post has a large number of cross-posts which
I will honor but will cut followups to a single group.  The post cuts
across other lines of moderation like fj.comp.announce. Email complaints to me.
--enm]


         CALL FOR PARTICIPATION
           AND ADVANCE PROGRAM



      SECOND INTERNATIONAL SYMPOSIUM
                ON ADVANCED RESEARCH
  IN ASYNCHRONOUS CIRCUITS AND SYSTEMS

                    March 18-21, 1996


   ______________________________________



              The University of Aizu
    Aizu-Wakamatsu, Fukushima, Japan



Sponsored By:

The IEEE Computer Society - VLSI-TC

The IEICE Technical Group on VLSI Design

The Telecommunications Advancement Foundation

In Cooperation With:
IFIP WG 10.5
The University of Aizu



Async'96__Organization

General Chair: Tosiyasu Kunii, The University of Aizu

Conference Co-chairs:
Takashi Nanya, Tokyo Institute of Technology
Alex Kondratyev, The University of Aizu

Program Co-chairs:
Luciano Lavagno, Politecnico di Torino
Alexander Taubin, The University of Aizu

Publication Chair: Takeshi Yoshimura, NEC

Publicity Chair: Fumiyasu Hirose, Fujitsu Laboratories Ltd

Finance Chair: Kazuaki Yamauchi, The University of Aizu

Local Arrangement: Yuko Kesen, The University of Aizu

Tutorial/CAD Booth: Michael Kishinevsky, The Univ. of Aizu

Industry Relations:
Tsuneo Ikedo, The University of Aizu
Masatoshi Sekine, Toshiba

US Industry/Academy:
Alan Davis, Erik Brunvand, University of Utah

European Representative:
Steve Furber, University of Manchester

Program Committee:
Kunihiro Asada (Japan)          Vyacheslav Marakhovsky (Japan)
Graham Birtwistle (UK)          Charles Molnar (USA)
Steven Burns (USA)              Steven Nowick (USA)
Tam-Anh Chu (USA)               Takuji Okamoto (Japan)
Jordi Cortadella (Spain)        Martin Rem (The Netherlands)
David Dill (USA)                Jens Sparso (Denmark)
Jo Ebergen (Canada)             Robert Sproull (USA)
Mark Greenstreet (Canada)       Pasupathy Subrahmanyam (USA)
Ran Ginosar (Israel)            Jan T. Udding (The Netherlands)
Ganesh Gopalakrishnan (USA)     Stephen Unger (USA)
Mark Josephs (UK)               Peter Vanbekbergen (USA)
Sadatoshi Kumagai (Japan)       Kees van Berkel (The Netherlands)
Bill Lin (Belgium)              Victor Varshavsky (Japan)
Alain Martin (USA)              Alex Yakovlev (UK)
                                Tomohiro Yoneda (Japan)



 General__Information


Climate: The weather in Aizu-Wakamatsu in March is vari-
able.  The average daytime temperature is around +7.5C
(45.5 F), but late snow is not unusual.  A winter coat is
recommended.

Conference language: The official language for the Con-
ference will be English.

Electricity supply:  Throughout Japan, mains electricity
is supplied at 100 volts 50/60 Hz AC. Most North American
connecting plugs can be used without adaptors.

Tipping:  Tipping is not common in Japan.  Taxi drivers
and waiters expect no tips and usually refuse to receive tips.

Transportation from the airport:  Narita Airport is lo-
cated East of Tokyo.  Take Narita Express train to Tokyo
train station (app.  2,900 yen).  Alternatively, take Keisei
Skyliner Express train (1,700 yen) to Ueno train station.
Change to Tohoku Shinkansen and get out in Koriyama (app.
7,000 yen for a non-reserved seat).  English announcements
are available on both trains.  Change to Viva Aizu train in
Platform 2 in Koriyama or to Aizu line in Platform 4 or 5
and get off in Aizu-Wakamatsu (app. 1,500 yen for Viva Aizu
and 1,090 for other trains). About 4.5 hours are required for
the whole trip.

Transportation from the airport - more scenic (and
cheaper) alternative:  Narita Airport to Ueno station in
Tokyo by Keisei line on the limited express train (tokyu)
(940 yen). Change to Tokyo subway following signs and take
Ginza line and stop at Asakusa station (140 yen).  Change
to Tobu line (with a transfer in Tajima to Aizu line) and
get off in Aizu-Wakamatsu (4,170 yen). About 6.5 hours are
required for the whole trip.

Recommended Hotels in Tokyo:
1.  Yushima Plaza Hotel.  Walking distance from Ueno
train station in Tokyo.  Prices in the range of 7,000 - 9,000
yen. Tel. +81-3-3831-2313 Fax. +81-3-3832-5768
2.   Fukushima  Kaikan  Hotel.  Walking distance from
Ueno. Same price range. Fax. +81-3-3834-6216.

FURTHER INFORMATION: World-Wide-Web access
information (including a sightseeing guide of Aizu) can be
found at URL:http://www.u-aizu.ac.jp/async96/.



    Accommodation
A number of rooms have been reserved at a special price
in the Aizu-Wakamatsu Washington Hotel.  Transportation
between the hotel and the conference site will be provided.
The hotel is within walking distance from the conference site.
To reserve your room, fill the form below and send it by fax/
mail.

    Food_Service

Registration fees include lunch on Monday, Tuesday, Wednes-
day and Thursday and the symposium banquet on Wednes-
day.  Additional tickets for the banquet may be purchased
on site for 6000 yen.

    Social_Events

On Monday March 18, starting from 8pm, there will be a
tour to "onsen" (hot springs) where participants can enjoy
the Japanese bath style. On Tuesday March 19, between 1.30
and 4pm there will be a bus excursion to historical places in
Aizu-Wakamatsu. These two events are free for participants.
    Aizu is also famous for its ski resorts.  On the last day,
March 21, an optional trip to the mountains will be orga-
nized.  Participants will stay for one additional night at a
hotel (March 21), and will be able to ski the next day and
then go by bus to the railway station.  The expected price
for the trip will be about 10000 yen including two meals and
lifts (ski rent is not included).

    Proceedings

Participants will receive a copy of the proceedings at the
symposium. Extra copies may also be purchased on site. Af-
ter the symposium, copies of the proceedings will be available
from IEEE Computer Society Press.

    Student_Attendees

Student registration at a reduced rate is available thanks to
a sponsorship from the Telecommunications Advancement
Foundation.Student attendees will receive a copy of the pro-
ceedings and will be entitled to the same food services and
social events as other attendees.

    Travel_grants

    A few travel grants will be available. Applications should
be sent to the Conference co-chair Alex Kondratyev (e-mail:
async96@u-aizu.ac.jp), no later than February 5, 1996




   Async'96__AT-A-GLANCE

___________________________________________________________________________
_    Sunday    _5:00 - 8:00pm   _ Early Registration                        
____March_17_________________________________________________________________
_   Monday   ____8:00_-_8:30am____Registration_____________________________ _
_   March 18  ___8:30_-_8:50am____Welcome_Notes____________________________
_             __8:50_-_12:40pm____Tutorials________________________________ _
_             ___________________________Lunch______________________________
_             __1:40_-_7:00pm_____Tutorials________________________________ _
____________________8:00pm________Tour_to_onsen______________________________
_   Tuesday   __9:00_-_10:30am____Session_1:_High-Speed_Design______________
_   March 19  ___________________________Break______________________________
_             __11:00_-_12:30pm___Session_2_:_Logic_Synthesis______________ _
_             ___________________________Lunch______________________________
_             __1:30_-_4:00pm_____Bus_tour_in_Aizu__________________________
_             __4:00_-_5:30pm_____Session_3:_Architectural_Synthesis_______  _
_             ___________________________Break______________________________
________________6:00_-_7:30pm_____Session_4:_Formal_Methods__________________
_  Wednesday  __9:00_-_10:30am____Session_5:_Novel_Techniques_______________
_   March 20  ___________________________Break______________________________
_             __11:00_-_12:00pm___Session_6_:_Design_Automation_____________
_             ___________________________Lunch______________________________
_             __1:00_-_4:20pm_____CAD-demo_and_Poster_Session______________
_             ___________________________Break______________________________
_             __4:50_-_6:20pm_____Session_7:_Low_Power_and_System_Design____
_             __6:20_-_7:00pm_____Embedded_Talk____________________________
________________7:30_-_10:30pm____Banquet____________________________________
_   Thursday  __9:00_-_10:30am____Session_8:_Logic_Optimization____________ _
_   March 21  ___________________________Break______________________________
_             __11:00_-_11:40pm___Embedded_Talk____________________________
_             __11:40_-_12:00pm___Awards_and_Closing________________________
_             ___________________________Lunch______________________________
____________________1:00pm________Ski_Tour__________________________________




Sunday,  March  17,  1996

Early Registration                      5:00pm - 8:00pm
(Washington Hotel Foyer)



Monday,  March  18,  1996

Registration                              8:00am - 8:30am
(Foyer of Lecture theater, The University of Aizu)

Welcome notes                          8:30am - 8:50am



Tutorials

(Lecture theater, The University of Aizu)


Future Trends in Microprocessor

Architecture Design

Time: 8:50 to 10:00

Presenter: Uri Weiser - Intel, Israel



An overview of VLSI technology and implementation trends,
will serve as a basis for extrapolation of future trends in
VLSI Microprocessors.  Microprocessor design, so far, has
employed microarchitecture features that were pioneered in
mainframes (e.g., superscalar, branch target buffer, caches,
superpipelining, out of order execution).  Past and current
generations of microprocessors have achieved performance
improvement via microarchitecture breakthroughs. The lec-
ture will present some potential future microarchitecture break-
throughs that will enable us to achieve future performance
goals. Future designs will use ultra high internal frequency of
operation to achieve high performance. This frequency trend
will force the use of asynchronous techniques.  Some poten-
tial high level asynchronous directions will be presented.




Silicon Single-Electron Transistors

Time: 10:20 to 11:30

Presenters:
Katsumi  Murase,  Yasuo  Takahashi  and  Akira  Fujiwara  -
NTT LSI Laboratories, Japan



The single-electron transistor is a device whose operation is
controlled by single-electrons. Because of its unique charac-
teristics and ultra-low power consumption, the single-electron
transistor can be a key device in future nanoelectronics and
will open up the possibility of innovative computer archi-
tecture. Until recently, however, operation of single-electron
transistors has mostly been limited to very low tempera-
tures because the feature device size has not been sufficiently
small.  To overcome this problem, we proposed a novel fab-
rication method based on silicon nanofabrication technology
and succeeded in developing silicon single-electron transis-
tors which showed single-electron-controlled characteristics
even at room temperature.
    In this tutorial talk, first the operation principle of single
electrons is explained in detail, and then the characteristics
of a single-electron transistor are described. After a discus-
sion about the problems of previous single-electron transis-
tors, the newly proposed silicon single-electron transistors
are presented.  Finally, an application of the silicon single-
electron transistor to a single-electron memory device is de-
scribed.


Nano and Quantum Devices.  Problems
of Logic and Asynchronous Design

Time: 11:30 to 12:40

Presenter:  Victor Varshavsky  - The University of Aizu,
Japan




Josephson Junction Device Technology

Time: 13:40 to 14:50

Presenter: Shuichi Tahara - NEC, Japan



Superconducting devices using Josephson junctions, with their
high intrinsic switching speed and low power dissipation, are
promising circuit elements for future ultrahigh performance
computer and communication applications.  Especially, the
power dissipation of superconductive LSI chips is 2 - 3 or-
ders of magnitude smaller than that of semiconductor LSI
chips.  Due to their low power dissipation characteristics,
many superconductive chips can be densely packed in a small
space.  As a result, media delay in the system using super-
conductive LSI chips can be decreased. Therefore, total per-
formance, such as throughput, of the system with supercon-
ductive LSI can be drastically improved in comparison with
that with semiconductor LSI.
    We will review the Josephson device technology and a
4Kbit RAM developed by us, in illustration of superconduc-
tive LSI. The RAM is characterized by 380ps access time
and 9.5mW power dissipation. We will also introduce a su-
per conductive ring-pipelined network as a new application
for superconductive LSI. The prototype chip has been de-
signed and estimated to operate at 10GHz.




VLSI Programming of Asynchronous

Circuits for Low Power

Time: 15:00 to 16:10

Presenter:
Kees van Berkel - Philips Research Labs, The Netherlands



"Asynchronous" does not imply "low power", but:
- - often allows the elimination of most clock power;
- - offers an automatic, instantaneous stand-by mode (leakage
power only), at arbitrary granularity in time and function;
- - offers more architectural options/freedom;
- - encourages distributed, localized control;
- - offers more freedom to adapt the supply voltage.
Low power consumption is becoming increasingly important
for portable, battery- powered consumer products, such as
personal audio, portable telephones, and games.
    At Philips Research we have developed a VLSI-program-
ming and compilation approach to the design of asynchronous
VLSI circuits.  This approach uses so-called handshake cir-
cuits as intermediate architecture. These notions will be in-
troduced by means of small examples. Our low-power claims
as well as various practical issues will be reviewed, based on
our experience with an audibly correct, fully asynchronous,
155k transistor DCC error corrector.


Low-Power Portable Design

Time: 16:30 to 17:40

Presenter:
Akira Matsuzawa - Matsushita Electric Co., Japan




Combining Commercial Synthesis

and Burst Mode

Time: 17:50 to 19:00

Presenter: Alan Davis - University of Utah, USA



The synthesis of high-performance asynchronous systems from
high level HDL descriptions that target asynchronous finite
state machines has a number of requirements. Some of these
are:  the ability to start from HDL descriptions, the ability
to obtain a collection of interacting asynchronous finite-state
machine controllers by decomposition, the synthesis of such
controllers,  as well as the ability to exploit the flexibility
offered by CMOS structures in the technology mapping pro-
cess.  At the University of Utah we are developing a high-
level synthesis tool, ACK, that supports these capabilities
and synthesizes descriptions given in a subset of Verilog into
CMOS circuits. This work is based on and extends existing
research in the area of burst mode synthesis (Davis, Coates,
Stevens, Dill, Nowick, Yun, Siegel).  The design framework
includes tools developed by us and integrates standard com-
mercial and public domain tools. A large number of bench-
mark examples have been synthesized and simulated using
ACK.



              Technical__Program


Tuesday,  March  19

9:00 - 10:30am: High-speed Design

    A System for Asynchronous High-speed Chip
      to Chip Communication
      P.T.Roine (Univ. of Oslo, Norway)
    Dynamic Logic in Four-Phase Micropipelines
      S. B. Furber, J. Liu (The Univ. of Manchester, UK)
    High-Performance Extended Burst-Mode Pipeline
      Circuits
      K.Y. Yun (UC San Diego, USA),
      P.A. Beerel (Univ. of Southern California, USA),
      J. Arceo (UC San Diego, USA)

10:30 - 11:00am: Break

11:00 - 12:30pm: Logic Synthesis

    An Efficient Algorithm for Deriving Logic Func-
      tions of Asynchronous Circuits
      T. Miyamoto, S. Kumagai (Osaka Univ., Japan)
    Complete state encoding based on the theory
      of regions
      J. Cortadella (Universitat Politecnica de Catalunya, Spain),
      M. Kishinevsky (The Univ. of Aizu, Japan),
      A. Kondratyev (The Univ. of Aizu, Japan),
      L. Lavagno (Politecnico di Torino, Italy),
      A. Yakovlev (Univ. of Newcastle upon Tyne, UK)
    General  Condition  for  the  Decomposition  of
      State Holding Elements
      S.M.Burns (Univ. of Washington, USA)

12:30 - 1:30pm: Lunch

1:30 - 4:00pm: Bus Tour in Aizu

4:00 - 5:30pm: Architectural Synthesis

    An Architecture for a Self-Timed Decou-
      pled Computer
      W. F. Richardson, E. Brunvand (Univ. of Utah, USA)
    Counterflow Pipeline-Based Dynamic Instruc-
      tion Scheduling
      T. Werner, V.Akella (Univ. of California, Davis, USA)
    Optimisation of Instruction Schedules for Micronet-
      based Asynchronous Processors
      D. K. Arvind, V. E. Rebello (The Univ. of Edinburgh, UK)

5:30 - 6:00pm: Break

6:00 - 7:30pm: Formal Methods
    Dynamic Hazards and Speed Independent De-
      lay Model
      N.Tabrizi, K.Eshraghian, M.J.Liebelt (Univ. of Adelaide, Aus-
      tralia)

    Some limitations to speed-independence in asyn-
      chronous circuits
      M. E. Bush, M. B. Josephs (South Bank Univ., UK)

    On the Correctness of the Sproull Conterflow
      Pipeline Processor
      P.G.Lucassen, J.T.Udding (Groningen Univ., The Netherlands)

           ______________________________________



Wednesday,  March  20

9:00 - 10:30am: Novel Techniques

    Single-Track Handshake Signaling with Appli-
      cation  to  Micropipelines  and  Handshake  Cir-
      cuits
      K. v.  Berkel, A. Bink (Philips Research Lab., The Nether-
      lands)

    Pulse-driven  dual-rail  logic  gate  family  based
      on rapid single flux quantum (RSFQ) devices
      for asynchronous circuits
      M.Maezawa, I.Kurasawa (Electrotechnical Lab., Japan),
      Y. Kameda, T. Nanya (Tokyo Inst. of Technology, Japan)

    Activity Monitoring Completion Detection (AMCD):
      A new single rail approach to achieve self-timing
      E. Grass, R.C.S. Morling, I. Kale (Univ. of Westminster, UK)

10:30 - 11:00am: Break

11:00 - 12:00pm: Design Automation
    Using partial orders for trace theoretic verifi-
      cation of asynchronous circuits
      T. Yoneda, T. Yoshikawa (Tokyo Inst. of Technology, Japan)

    Statechart  Methodology  for  the  Design,  Val-
      idation,  and  Synthesis  of  Large  Scale  Asyn-
      chronous Systems
      R. Kol, R. Ginosar, G. Samuel (Technion, Israel)

12:00 - 1:00pm: Lunch

1:00 - 4:20pm: CAD-demo and Poster Session

Those who would like to demonstrate software tools and/or
to make a poster please contact the Organizing Committee
(e-mail:  async96@u-aizu.ac.jp) no later than February 23,
1996.

4:20 - 4:50pm: Break

4:50 - 6:20pm: Low Power and System Design

    Energy and Entropy Measures for Low Power
      Design
      J. Tierno, R. Manohar, A. Martin (California Institute of Tech-
      nology, USA)

    Issues in the Design of a Low-power Asynchronous
      Audio FIR-filter bank
      L. S. Nielsen, J. Sparso (Technical Univ.  of Denmark, Den-
      mark)

    The AMULET2e Cache Systems
      J.D.Garside, S.Temple, R.Mehra (The Univ.  of Manchester,
      UK)

6:20 - 7:00pm: Embedded Talk

    Quasi-delay-insensitive Circuits are Turing Com-
      plete
      R. Manohar, A. J. Martin (California Institute of Technology,
      USA)

7:30 - 10:30pm: Banquet

           ______________________________________



Thursday,  March  21

9:00 - 10:30am: Logic Optimization

    Combining  Process  Algebras  and  Petri  Nets
      for  the  Specification  and  Synthesis  of  Asyn-
      chronous Circuits
      M.A. Pena, J. Cortadella (Universitat Politecnica de Catalunya,
      Spain)

    Control Resynthesis for Control-Dominated Asyn-
      chronous Design
      T. Kolks, S. Vercauteren, B. Lin (IMEC, Belgium)

    Optimizing average-case delay in technology map-
      ping of burst-mode circuits
      P.A. Beerel (Univ. of Southern California, USA),
      K.Y. Yun (UC San Diego, USA),
      W.C. Chou (Univ. of Southern California, USA)

10:30 - 11:00am: Break

11:00 - 11:40am: Embedded Talk

    Results on Amulet2
      S. B. Furber (The Univ. of Manchester, UK)

11:40 - 12:00pm: Awards and Closing

A Best Paper award will be given to the best technical paper
presented at Async'96.  The Best Paper will be selected by
the attendees during the symposium.

12:00 - 1:00pm: Lunch

1:00: Ski Tour




     Advance__Registration__Form


       Async96 Symposium, March 18-21, 1996
  The University of Aizu, Aizu-Wakamatsu, Japan


Please mail or fax registration form to:
Async96, Yamauchi Kazuaki
email: yamauchi@u-aizu.ac.jp, fax: +81-242-37-2531
University of Aizu, Aizu-Wakamatsu, Japan 965-80.
All advance registration must be postmarked no later than
February 23, 1996.
On-site Symposium payment must be made by cash
PLEASE TYPE OR PRINT CLEARLY
 Surname:
 Given Name
 Organization:
 Address:


 State:                          Post code:
 Country:
 Phone: (   )                    Fax: (   )
IEEE/ACM/IEICE Membership No:
 REGISTRATION FEES                  Before         After
                                    Feb. 23        Feb. 23
 IEEE/ACM/IEICE Members             34,500 Yen     41.500 Yen
 Non-members                        43,500 Yen     52,500 Yen
 Students                           10,000 Yen     12,000 Yen
Note: Registration fees are in Japanese Yen. They include
the conference attendance, the proceedings, the lunches, cof-
fee service and the banquet.
METHOD OF PAYMENT (check one)
   [ ]    Bank (Telegraphic) Transfer
          Bank Name: Fuji Bank, Aizu Branch (712)
          Address: Aizu-Wakamatsu City, Fukushima, 965 Japan
          Acct. No. : 1534630
          Acct. Name: ASYNC96 Jimukyoku Yamauchi Kazuaki
   [ ]    Credit Card (check one)
          [ ]  Master Card    [ ] Visa    [ ] Eurocard
     Card #:                          _____________________
     Card Holder Name:                ______________________
     Expiration Date: ____________    Signature:_____________
IMPORTANT: Credit card payment orders must not be
sent by e-mail.




HOTEL__RESERVATION__FORM


Async96 Symposium, March 18-21, 1996

    Aizu-Wakamatsu Washington Hotel

               Tel.  81-242-22-6111,

               Fax +81-242-24-7535)


    Print in black ink or type.  This form must be received
via mail or fax by March 3, 1996.
     Surname:
     Given Name:
     Organization:
     Address:


     State:                           Post code:
     Country:
     Phone: (   )
     Fax: (   )
     Signature:                       Date:
     I reserve as follows from:    ________________
                                   arrival date(mm/dd)
     to:                           ________________
                                   departure date(mm/dd)
     [] Single A      [] Single B           [] Deluxe Single
     6,480 Yen         6,840 Yen             7,110 Yen
     small             bigger than A         bigger than B
     []Twin room       [] Double room
     13,050 Yen        11,700 Yen
     (Two beds)        (One double bed)
    Prices are given in Japanese Yen per room and night in-
cluding tax and service fee not including breakfast (breakfast
charge is 1,133 yen).
Hotel Information: Western style hotel. 25 min. on foot
from conference site, 3 min.  from Aizu-Wakamatsu train
station.  Transportation between hotel and conference site
will be provided. Payment by credit card or cash only (Visa,
Master Card, AMEX, JCB, Diners Club are acceptable).
    Total payment must be made during check-in.
Return this form by mail to: Aizu-Wakamatsu
Washington Hotel, 201, Byakko Machi, Aizu-Wakamatsu,
Fukushima, Japan 965 or by fax at: +81-242-24-7535.



-- 
Kind regards

Alexander Taubin

THE UNIVERSITY OF AIZU                   phone   +81-242-37-2572 (office)        
Tsuruga, Ikki-machi, Aizu-Wakamatsu City fax     +81-242-37-2744         
Fukushima, 965-80 Japan                  e-mail  taubin@u-aizu.ac.jp     
---- <A HREF="http://www.u-aizu.ac.jp/~taubin/">------------------------



Article: 2591
Subject: Emulation for a wireless chip
From: eea80593@maddux.EE.NCTU.edu.tw (Chuang Hsien-Ho)
Date: 9 Jan 1996 09:07:23 GMT
Links: << >>  << T >>  << A >>
We have a project, "A Baseband Chip Set for Digital Cellular Phone", in
progress. We will soon finish the verilog coding. Now we want to prepare
for the emulation step. We have about tens of thousands of gates, targeting
on at least 6MHz.

Being a academic project, we might not able to afford a complete commercial
system. We plan to buy some RAM-based FPGAs(like XC4000 or ALTERA FLEX series),
maybe some FPICs(like Aptix).

Could you experienced persons give me some comments or suggestions? Or where
can I get the detail information of these vendors?  Thanks a lot.
--
===============================
Hsien-Ho Chuang    
eea80593@yankees.ee.nctu.edu.tw
===============================


Article: 2592
Subject: Re: [q][Reverse Engineering Protection]
From: fliptron@netcom.com (Philip Freidin)
Date: Tue, 9 Jan 1996 09:55:52 GMT
Links: << >>  << T >>  << A >>
In article <4ct08l$4b4@ixnews7.ix.netcom.com> mojoteri@ix.netcom.com(Morris Jones) writes:
>In <DKr0IA.L0s@world.std.com> jcooley@world.std.com (John Cooley)
>writes: 
>>
>>John Cooley <jcooley@world.std.com> wrote:
>>>Jyri, one clever idea for protecting designs in chips I heard of was
>>>using Xilinx FPGA's that were programmed once at the factory with a
>>>small battery attached after programing.  (That is, the power-up
>>>program for the Xilinx part was NOT included in the PCB.)  What this
>>>did was make the circuit unreversable but still functional.
>>
><snip>

Morris Jones writes his $.02 cents worth, and unfortunately, that is
pretty close to what it is worth  :-)

>Give Me a boring week with the E-beam prober, and it is easy to read!!!
>
> <snip  stuff about reverse engineering stuff with an E-beam prober, and
>  how even really tough stuff can be broken >
>
>my $.02
>
>Mojo

Unfortunately, what you missed is that the Xilinx chip is a RAM based,
volatile storage and configuration FPGA. The chip has the config loaded
into its configuration memory at the factory, and it is maintained
after shipping the system by battery backup. As soon as the battery is
disconnected (like when you take the chip over to the acid bath to etch
away the plastic so your E-beam prober can see the die) the chip will
lose its configuration, and revert to an unprogrammed Xilinx chip. As
I have explained about a month ago on this thread, if you are doing this
for security, one of the config bits you send into the chip is a bit that
disables readback of the bitstream.

To add to your entertainment, even if you figured out how to etch a plastic
package without loosing power for even a few nanoseconds, and then E-beamed
the device, what you would end up with is the Xilinx bitstream which is
in itself an "encrypted" version of the design, for which their is NO 
existing software tool that can decode the bitstream back into something
more useable to a human (to my knowledge, which on this topic is not 
minimal :-).

Of all the possible ways of implementing logic, I know of no system more
secure than battery backed up configuration in a RAM based FPGA. This
applies to products from Xilinx, Altera, Atmel/NatSemi/IBM, 
PMEL/Toshiba/Motorola, ATT.

Thats my $0.10 worth   :-)

	Philip Freidin



Article: 2593
Subject: Simulator for LATTICE pDS
From: schuelts@tick.informatik.uni-stuttgart.de (Tobias Schuele)
Date: 9 Jan 1996 12:48:10 GMT
Links: << >>  << T >>  << A >>

Hi!

I am using the pDS Software from LATTICE to develop designs for their CPLDs.
Since there is no simulator available from LATTICE I would like to know
who has experiences with 3d party simulators. Can anybody recommend some
products? Thank you very much in advance!

Best regards,
Tobias



Article: 2594
Subject: Re: [q][Reverse Engineering Protection]
From: graeme@bilby.digideas.com.au (Graeme Gill)
Date: 10 Jan 1996 10:33:37 +1100
Links: << >>  << T >>  << A >>
fliptron@netcom.com (Philip Freidin) writes:

>In article <4ct08l$4b4@ixnews7.ix.netcom.com> mojoteri@ix.netcom.com(Morris Jones) writes:

>>Give Me a boring week with the E-beam prober, and it is easy to read!!!
>>
>> <snip  stuff about reverse engineering stuff with an E-beam prober, and
>>  how even really tough stuff can be broken >
>>
>>my $.02
>>
>>Mojo

>To add to your entertainment, even if you figured out how to etch a plastic
>package without loosing power for even a few nanoseconds, and then E-beamed
>the device, what you would end up with is the Xilinx bitstream which is
>in itself an "encrypted" version of the design, for which their is NO 
>existing software tool that can decode the bitstream back into something
>more useable to a human (to my knowledge, which on this topic is not 
>minimal :-).

Hmm. I somehow doubt that the bitstream remains a bitstream once it's inside
the Xilinx part. By definition of the architecture, the bitstream ends up
as 1's and 0's in RAM cells that are hooked up to the configurable logic.

Figuring out the wiring of the configurable logic would be the big task,
made easier (I would imagine) by there being a fair degree of repetition
within the design, and the fact that you can do it with an un-programmed
part.

Of course, if your aim is to figure out the bitstream from the RAM cells
contents directly, then you would have to figure out the "decryption" logic
and be able to reverse it. But why bother  - if you have the logic
functions figured out, just compile them into a programming stream with
the usual tools.

	Graeme Gill.


Article: 2595
Subject: Re: Career value: VHDL or Verilog?
From: Ken Wood <ken@eda.com.au>
Date: Wed, 10 Jan 1996 11:40:50 +1100
Links: << >>  << T >>  << A >>
Tom Biggs wrote:
> 
> > Assembler <--> schematic capture: Gives the fastest & tightest results for
> > small, human-managable blocks. Least portable.
> >
> > C <--> RTL VHDL or Verilog
> 
> The problem with this analogy is that assembly language, C, VHDL, and Verilog
> are all 'word' based programming tools, whereas schematic capture is a visual
> design tool.
> 
> In fact, if you use hierarchical schematics it is possible to design at a
> pretty high level with schematics. The flow control of a processor
> drawn with multiplier, ALU, Mux, and memory blocks, etc, on a schematic is
> much clearer than a lot of VHDL text.
> 
> There are a number of design tools such as Escalade's that let you
> design HDL code from visual block diagrams. So you could say that
> the block diagrams are the high level approach and the HDL is the lower
> level.

I agree that these sort of graphical design entry tools are a different
beast
entirely - I'd also put them in the "beyond-HDL" category, rather than
lumped in with schematic capture. The key difference is that you're
using
graphics to describe a design in a technology-independent and relatively
architecture-independent way. With schematic capture, you end up
specifying
all the way down to the gates, even if much of the detail is hidden
inside
library elements.

Ken

-- 
Ken Wood  -  Mentor Technologies / EDA Solutions   email: ken@eda.com.au
Office: Sydney, Australia        Tel: 61-2-413 4600   Fax: 61-2-413 4622
Tech Support: support@eda.com.au        Other Enquiries: info@eda.com.au
Mentor Graphics: http://www.mentorg.com/   MT: ftp://ftp.eda.com.au/pub/


Article: 2596
Subject: Re: [q][Reverse Engineering Protection]
From: jlodman@alumnae.caltech.edu (Michael Lodman)
Date: 10 Jan 1996 01:38:41 GMT
Links: << >>  << T >>  << A >>
 In article <4ct08l$4b4@ixnews7.ix.netcom.com>,
Morris Jones <mojoteri@ix.netcom.com> wrote:
>Silicon is a pure substance, and any manufacturing done is easy to see.
>The hardest to reverse are implant ROM's (Takes a sensitive hand on an
>E-beam prober to see the threshold differences).  EPROMS, and RAMS can
>easily be read with just a SEM and a little practice.  The so called
>IBM reverse proof PS/2 chips full of black goop took less than a day to
>deal with on a plasma etcher, and were easily reversed.

I agree with your comments accept for RAM. Try keeping your battery intact
while plasma etching. The RAMS can be read, but only if there is something 
there to read, and a SEM could potentially flip a residual RAM charge if
the battery is disconnected.

ROMS, on the other hand, even implant ROMS, can be read with a micro-probe.

--
"There is a certain level of self-imposed ignorance that I have no desire 
to try and correct." - Chris Wolf (self-descriptive? you make the call!)


Article: 2597
Subject: Re: INDUSTRY GADFLY: SpeedSim's Three Dark Clouds
From: ramesh@hermes.zycad.com (Ramesh Narayanaswamy)
Date: 10 Jan 1996 01:56:50 GMT
Links: << >>  << T >>  << A >>

In article <DKqzFz.HKI@world.std.com>, jcooley@world.std.com (John Cooley) writes:
|> John Cooley <jcooley@world.std.com> wrote:
|> >  The one residual effect Redwood's splash made on the EDA buying and selling
|> >communities was a sudden new interest in the extremely high performance cycle
|> >based simulators could provide.  Hence, very quietly in Decemeber '93 in
|> >Westford, Massachusetts, SpeedSim was born.  And in March at the recent
|> >International Verilog Conference, SpeedSim finally delivered on Redwood's
|> >promise by announcing a Verilog cycle based simulator available immediately
|> >at $35,000 as a floating licence product.
|> 
|> Renu Raman <ram@shukra.Eng.Sun.COM> wrote:
|> >History may have been re-written here. I think Cycle Based Simulators (CBS)
|> >are not a new idea and has been in the interest for most large scale
|> >synchronous system design. It became more relevant to the commmercial
|> >space, when gate densities crossed the 100K mark and which happened in
|> >the early 1990s. Verilog - interpreted and compiled simulators were
|> >OK until the knee of the simulation speed requirement hit the broader market.
|> 
|> Renu, I think you're missing the point of the whole article: I *wasn't*
|> claiming cycle-based simulators were a new idea (in fact I even later mentioned
|> how SpeedSim's origins came from years of work at DEC) but that cycle-based
|> simulators were new for the *commercial* EDA market.  Prior to Redwood, I
|> know of no other company that tried to commercially market a cycle-based
|> simulator -- all cycle based simulators were developed as in-house,
|> proprietary software used *soley* by the same computer manufacturer who 
|> created it.   Redwood's hoopla, IMHO, changed all this.

	Beg to disagree.

	A cycle based simulator produced by Aida called SSIM was commercially
	marketed in the 1984-88 timeframe. It was an impressive simulator and
	the Apollo Computers group were a major customer of theirs. It was 
	called levelized compiled code in those days but it fits the extant
	definition of a cycle based simulator. 
	
	Levelized compiled code in this context is not be confused with
	compiled code or native compiled code as used with rtl simulators.
	it is most precise to call SSIM 
	a Cycle based, Eval Driven, Compiled Simulator. Maybe i best use
	the term 'Cycle based' to mean this class of simulator :-)


	The relevance of cycle based simulators is cyclic !

	Historically, the first simulators written by Sundaram Seshu and Freeman
	in 1962-65 were cycle based. Event driven simulators came along in
	1965-69 with Ernst Ulrich's work.

	The highest performance simulation method of the day depends upon 
	the relative speeds of processor and memory, and the amount of
	event activity in designs. When processors are much faster than memory 
	cycle based simulation which does much fewer memory operations as 
	compared to
	event driven tends to be faster. If the event activity is higher the
	the advantage of event driven evaluation is lower. Of late register
	operations are much much faster than memory operations, and event
	activity tends to be much higher due to denser faster logic.
	
	Thus at present cycle based simulation will be a faster technique than
	event driven simulation running on the same processor (assuming
	equally good or equally bad implementations ;-).



Article: 2598
Subject: Re: Need Re-programable VXI Module
From: roger@coelacanth.com (Roger Williams)
Date: 10 Jan 1996 06:32:33 GMT
Links: << >>  << T >>  << A >>
>>>>> Dan Blow <blow> writes:

  > I have a need for a re-programable module to be used in the
  > implementation of VXI based test sets...

It sounds as if this would be simple to do with a standard Interface
Technologies VXI Interface Module (or chip set) and a Xilinx FPGA.
We've done this on several of our own VXI boards (so that our
"circuitware" can be upgraded by our software drivers) -- it never
occured to us that a generic version could be a saleable product,
though...

(BTW, your "From:" header is messed up.)

-- 
Roger Williams            PGP key available from PGP public keyservers
Coelacanth Engineering        consulting & turnkey product development
Middleborough, MA           wireless * DSP-based instrumentation * ATE
tel +1 508 947-8049 * fax +1 508 947-9118 * http://www.coelacanth.com/


Article: 2599
Subject: Re: [q][Reverse Engineering Protection]
From: pkh@fantti.tky.hut.fi (Petri Havanto)
Date: 10 Jan 1996 09:50:36 GMT
Links: << >>  << T >>  << A >>
In article <4cuu0h$91u@bilby.digideas.com.au> graeme@bilby.digideas.com.au (Graeme Gill) writes:

<  stuff about  probing removed>

> >>Give Me a boring week with the E-beam prober, and it is easy to read!!!
> >>

Somehow it seems to me that 'easy' is not exactly the right word. I
mean, if it was, I suppose the Xilinx bitstream-decryption wold have
been cracked a long time ago. On the other hand, maybe it is, it would
hardly be something to publish loudly. Maybe it is reasonable to feel
a little bit paranoid about the security of the bitstreams as well...


All the best,
Petri




Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarApr2017

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search