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Messages from 3125

Article: 3125
Subject: Sun bpp bidirectional parallel port
From: wongtai@eecg.toronto.edu (David Wong)
Date: 8 Apr 96 19:13:03 GMT
Links: << >>  << T >>  << A >>
Hi,

As part of my thesis project, I have to interface to the Sun's
parallel port using Sun's bpp driver.

I have obtained the write timing protocol for the parallel port
from the IBM-PC Tech Ref Manual.  Unfortunately, it is did not
document the read timing for a bidirectional parallel port.
I have not been to successful in figuring it out by trial and
error.

It would be much appreciated if someone can provide the
specification for the read timing on a bidirectional port.



--

Dave.



Article: 3126
Subject: FPGA->ASIC conversion
From: bkelley@alb.asctmd.com (Brad Kelley)
Date: Mon, 8 Apr 1996 13:31:26
Links: << >>  << T >>  << A >>
I am currently doing a design in an Actel FPGA (Act1 or Act2) that I would 
like to convert to an ASIC to reduce cost, current consumption, package size, 
all the good reasons.  It's been a while since we last surveyed vendors, so 
we'll be out doing a current one.  Anyone done a conversion lately?  Problems, 
suggestions, lessons learned, vendor problems/successes, any tips would be 
appreciated.

Current project is low-volume (fixed order for 500 units, 1 FPGA/ASIC per), so 
zero NRE or low NRE is required.  Have some one-year old info that at least 
one vendor would convert for zero NRE with 500-piece order, so I think this 
might be possible even with small volume.


Article: 3127
Subject: Re: FPGA->ASIC conversion
From: Scott Guest BNR <cnc274@bnr.ca>
Date: Mon, 08 Apr 1996 17:14:00 -0400
Links: << >>  << T >>  << A >>
Brad Kelley wrote:
> 
> I am currently doing a design in an Actel FPGA (Act1 or Act2) that I would
> like to convert to an ASIC to reduce cost, current consumption, package size,
> all the good reasons.  It's been a while since we last surveyed vendors, so
> we'll be out doing a current one.  Anyone done a conversion lately?  Problems,
> suggestions, lessons learned, vendor problems/successes, any tips would be
> appreciated.
> 
> Current project is low-volume (fixed order for 500 units, 1 FPGA/ASIC per), so
> zero NRE or low NRE is required.  Have some one-year old info that at least
> one vendor would convert for zero NRE with 500-piece order, so I think this
> might be possible even with small volume.
Brad,

	I would ask Actel if they offer mask-programmed versions of 
their parts. Xilinx offers "Hardwire" and Altera offers mask-programmed
versions of their CDLPs and FPGAs. 

	Finding a conventional ASIC vendor who will not required an NRE
will be difficulty (though there may be some out there). AMI 
Semiconductor and Orbit Semiconductors (these two specialized in 
FPGA -> ASIC conversion) do require NRE.

Good luck,

-- 
--------------------------------------------------------------------------
Scott Guest - MSS      	       		  BNR, Inc.
SPM Development (3E86)                    35 Davis Drive
ph (919) 991-2215                         Research Triangle Park, NC
27709
ESN 6-294-2215                            E-mail: cnc274@bnr.ca
FAX (919) 991-2215
--------------------------------------------------------------------------


Article: 3128
Subject: Available Research Assistant positions
From: Abdelhak Zoubir <a.zoubir@qut.edu.au>
Date: Tue, 9 Apr 1996 00:19:02 GMT
Links: << >>  << T >>  << A >>


        Exciting opportunities for postgraduate studies


                                QUT
        Signal Processing Research Centre
                RESEARCH ASSISTANTS

The Signal Processing Research Centre (SPRC) is an international leader in
signal, speech and image processing, which offers postgraduate programs at
both doctoral and masters levels. Professor  Boualem Boashash is the Centre
Director. Ten academics, two postdoctoral fellows and over 20 postgraduate
students are currently active in the research projects initiated by the
SPRC.  The centre comprises three laboratories of which the Image Laboratory
houses the expertise in Robotics. 

RESEARCH ASSISTANT POSITIONS are available in the Robotics & Image
Processing Laboratory.
There may be an opportunity for doctoral students to work as casual tutors
or research assistants within the Centre.

        ROBOT VISION

The position is open to candidates especially wishing to undertake a
research higher degree in the area of Robotics until 31 December 1996.

Robotics is an expanding and exciting area.  Research projects are
undertaken using a mobile robot equipped with a manipulator (ANDROS 4x4
robot), with special emphasis being placed on applying robotics to the
service industry. Interested Electrical, Mechanical Engineering or
Information Technology graduates can contact Dr Norbert Harle, Assistant
Director, SPRC,  Tel: (07) 3864 2489, Fax (07) 3864 1516, e-mail:
n.harle@qut.edu.au

        OBJECT RECOGNITION

A research assistant is required to develop software and apply object
recognition algorithms to test images. The project is part of a study funded
by the U.S. Office of Naval Research. It involves development of algorithms
and software for detection and identification of objects from cluttered
acoustic images of underwater objects. The appointment will be for a period
of six months with the possibility of continuation as a Ph.D. scholarship
top-up if the candidate is successful in obtaining a postgraduate study
scholarship such as the APA. 

If you are an electrical engineering or Information technology graduate with
an interest in image processing and pattern recognition, please contact Dr.
V. Chandran, Tel: (07) 3864 2124, email: v.chandran@qut.edu.au. 

Salary range for the above positions:  $20 116 - $27 356

        IMAGE PROCESSING/VISION OPEN LEARNING FACILITY

Two part-time Research Assistant positions are available IMMEDIATELY.  Both
positions will involve working in a team to develop a multi-media image
processing course for the World Wide Web.  The first position requires a
strong background in signal processing and mathematics, plus C or C++
programming capabilities. 

The second position requires a graduate in information technology with
excellent knowledge of software integration and user graphical interfacing.
Advanced knowledge of HTML and experience in designing computer-based
educational software is an advantage.  

For both positions, PREFERENCE IS GIVEN TO CANDIDATES WHO WILL STUDY FOR A
PhD in one of a number of exciting research topics covering a wide range of
image processing and computer and robot vision projects.  The appointment
will be on a part-time or casual basis with an hourly rate of $12.1144 to
$16.1379 for a period of 8 months initially. If you are an Electrical
Engineering/Information Technology graduate and require further information,
please contact Dr Wageeh Boles, Lecturer, Tel (07) 3864 2866, email
w.boles@qut.edu.au.

Postal address for all the above is:  Signal Processing Research Centre,
Queensland University of Technology, GPO Box 2434, Brisbane,  Qld. 4001,
Australia.  Fax No. is + 61 7 3864 1516.


Article: 3129
Subject: Re: Q: Multiplier & Subtractor in Xilinx 5204 FPGA ?
From: Ray Andraka <randraka@ids.net>
Date: 9 Apr 1996 01:51:18 GMT
Links: << >>  << T >>  << A >>
p.taylor@ukonline.co.uk wrote:
>
> We are just getting to grips with PROCapture & XACT, and
> someone I work with needs to do the following :
> 1) An 8bit x 1 two`s-complement multiplier in 8 blocks (?).
> 2) A serial subtractor (two`s complement) with 2x 36bit
> input busses and a 36bit output bus.
> Any ideas ?  Thanks.

Get a copy of my paper describing a bit serial FIR filter from my 
website (http:\\www.ids.net\~randraka).  The paper discusses serial 
by parallel multipliers, which I think is what you are asking about,
as well as bit serial adders and twos complement.  It is written
around the Concurrent architecture which is the basis for Atmel's
AT6000 series and NSC's CLAy parts.  The logic is easy to implement
in Xilinx.  The 8 bit serial by parallel multiplier can be easily 
realized in 8 Xilinx cells.

 -Ray Andraka
 Chairman, the Andraka Consulting Group
 401/884-7930     Fax 401/884-7950
 mailto:randraka@ids.net
 http://www.ids.net/~randraka
 
 






Article: 3130
Subject: Re: Sun bpp bidirectional parallel port
From: milne@cv.com (Ewan D. Milne)
Date: 9 Apr 1996 03:16:21 GMT
Links: << >>  << T >>  << A >>
David Wong (wongtai@eecg.toronto.edu) wrote:
: As part of my thesis project, I have to interface to the Sun's
: parallel port using Sun's bpp driver.

: I have obtained the write timing protocol for the parallel port
: from the IBM-PC Tech Ref Manual.  Unfortunately, it is did not
: document the read timing for a bidirectional parallel port.
: I have not been to successful in figuring it out by trial and
: error.

I built my own FPGA demonstration board that hooks up to the
builtin parallel port on my Sparcstation 20.  Some Sparcstations
have a builtin parallel port, others do not and instead need an
Sbus card that provides this functionality.  Be aware that the
hardware implementation is slightly different.  In particular,
older revs of the SS10 motherboard don't work correctly but
unfortunately I don't remember what the exact problem was.
There is also a problem on both the SS10 and SS20 where some
peripheral devices can't drive the PE (paper empty) line low
enough and the driver won't transfer the data.

For information regarding parallel port driver implementation
on the Sparctation, consult the include file /usr/include/sys/bpp_io.h
It is supposedly possibly to adjust the timing of the STROBE
and ACK signals via an ioctl().  However the default settings
worked OK for me.

I had tremendous trouble getting the bpp driver software working.
Although there are ioctl() settings that are supposed to make the
bpp driver ignore the status of the ACK and BSY lines, I was not
able to get this to work properly.  I ended up having to add
gates to generate the signals to send back.

I was able to get data out from the parallel port to load the
Xilinx chip, but I gave up trying to get readback working through
the bpp driver.  The driver is really set up to interface to a
scanner.

Mail me if you want the source code for a program that loads
the Xilinx chip.  I think I have a rough schematic of the hardware
interface somewhere that I could FAX to you as well.

[Followups set to comp.sys.sun.hardware and comp.arch.fpga]

----------------------------------------------------------------
Ewan D. Milne / Computervision Corporation  (milne@petra.cv.com)


Article: 3131
Subject: VHDL conversion function from int to time ...?
From: vijayn@cdac.ernet.in (Vijay A Nebhrajani)
Date: Tue, 9 Apr 1996 08:19:57 GMT
Links: << >>  << T >>  << A >>
Hi, everybody!

Anyone know of a function on Synopsys to convert time to integer and vice versa?
How could such a function be written, if it were not available readymade? need help
VERY urgently.

Thanks in advance. Email direct to vijayn@cdac.ernet.in

-- vijay.




Article: 3132
Subject: Re: FPGA->ASIC conversion
From: Bob Elkind <eteam@aracnet.com>
Date: Tue, 09 Apr 1996 22:16:54 +0100
Links: << >>  << T >>  << A >>
Brad Kelley wrote:
>
> I am currently doing a design in an Actel FPGA (Act1 or Act2) that I would
> like to convert to an ASIC to reduce cost, current consumption, package size,
> all the good reasons.  It's been a while since we last surveyed vendors, so
> we'll be out doing a current one.  Anyone done a conversion lately?  Problems,
> suggestions, lessons learned, vendor problems/successes, any tips would be
> appreciated.
>
> Current project is low-volume (fixed order for 500 units, 1 FPGA/ASIC per), so
> zero NRE or low NRE is required.  Have some one-year old info that at least
> one vendor would convert for zero NRE with 500-piece order, so I think this
> might be possible even with small volume.

If you stand back, you may conclude that you will be paying for the NRE
costs; either through up-front charges, or through higher per-unit production
cost, or a combination of the two.

Masks cost money, and the ASIC vendor certainly hasn't forgotten that.

The real (rather than accounting magic) savings are probably found in
the following areas:

1.  Find a vendor who has a genuinely lower cost of doing business than
the others.  Sometimes this implies finding a vendor with its own captive
fab facility, their own mask shop, etc.

Sometimes this implies finding a vendor that does high volume in orders
similar to yours, and benefits from a production process optimised for the
type of business you represent.  For example, some ASIC vendors have fab
lines geared specifically for low-volume, quick-response business.  The
phone company probable wouldn't get the best deal there, but you and I
might be better off than we might be at a big, production volume intensive
vendor.

2.  Find a vendor that requires as little time/effort on your part as possible.
This saves you NRE costs that you would otherwise bear in terms of development 
time and effort.

Example:  Xilinx' Hardwire program, last time I looked, was *not* cheap...
but they had one thing going for them.  They guarantee (with a few obvious
exceptions) that the ASICs they deliver meet or exceed the performance of
you debugged and verified FPGA "program".  If you are happy with an existing
Xilinx FPGA design, you needn't develop any test vectors (for production test)
or simulations (for design translation verification).  This is a real savings
to you.

Example 2:  The "interface" to the vendor saves you time/effort.  They accept
a netlist/vector/database format that you just happen to generate, without
additional translation or verification (or risk).

Finally, if you're part of a bigger company, sometimes a new vendor will
make you a heckuva deal to get their foot in the door, to prove their
worth to the company at large.  In these cases, you'll get a better
deal than your order would otherwise merit.

Hope this helps...

Bob Elkind

**************************************************************************
Bob Elkind                email:eteam@aracnet.com             CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************


Article: 3133
Subject: Re: Sun bpp bidirectional parallel port
From: eric@goonsquad.spies.com (Eric Smith)
Date: 10 Apr 1996 02:13:04 GMT
Links: << >>  << T >>  << A >>
In article <1996Apr8.151303.14860@jarvis.cs.toronto.edu> wongtai@eecg.toronto.edu (David Wong) writes:
> It would be much appreciated if someone can provide the
> specification for the read timing on a bidirectional port.

IEEE 1284

Don't know if the Sun bidirectional ports are compliant, though, as
this is a fairly new sepc.

Eric


Article: 3134
Subject: Re: Sun bpp bidirectional parallel port
From: m_thompson@ids.net (Michael Thompson)
Date: 10 Apr 1996 12:47:00 GMT
Links: << >>  << T >>  << A >>
In article <1996Apr8.151303.14860@jarvis.cs.toronto.edu>, 
wongtai@eecg.toronto.edu says...
>
>Hi,
>
>As part of my thesis project, I have to interface to the Sun's
>parallel port using Sun's bpp driver.
>
>I have obtained the write timing protocol for the parallel port
>from the IBM-PC Tech Ref Manual.  Unfortunately, it is did not
>document the read timing for a bidirectional parallel port.
<snip>

Get a copy of the IEEE-1284 Bi-Directional Parallel Port standard.

-- 
Michael Thompson     E-Mail     m_thompson@ids.net
Schroff, Inc.        Phone      401-732-3770
Warwick, RI 02886    FAX        401-739-7599



Article: 3135
Subject: Re: FPGA->ASIC conversion
From: greg_peek@ccm.jf.intel.com (Greg Peek)
Date: Wed, 10 Apr 1996 19:36:30 GMT
Links: << >>  << T >>  << A >>
Scott Guest BNR <cnc274@bnr.ca> wrote:

>Brad Kelley wrote:
>> 
>> I am currently doing a design in an Actel FPGA (Act1 or Act2) that I would
>> like to convert to an ASIC to reduce cost, current consumption, package size,
>> all the good reasons.  It's been a while since we last surveyed vendors, so
>> we'll be out doing a current one.  Anyone done a conversion lately?  Problems,
>> suggestions, lessons learned, vendor problems/successes, any tips would be
>> appreciated.
>> 
>> Current project is low-volume (fixed order for 500 units, 1 FPGA/ASIC per), so
>> zero NRE or low NRE is required.  Have some one-year old info that at least
>> one vendor would convert for zero NRE with 500-piece order, so I think this
>> might be possible even with small volume.
>Brad,

>	I would ask Actel if they offer mask-programmed versions of 
>their parts. Xilinx offers "Hardwire" and Altera offers mask-programmed
>versions of their CDLPs and FPGAs. 

Actel does offer  a "Hardwire" conversion for their parts, which I am
considering using for the first time. If anyone has done a hardwire
conversion with Actel, I would be very interested in hearing your
opinions/horror stories.

 I am afraid the NRE is very high for any of the FPGA vendors doing
the conversion for you, higher than a normal gate array NRE.  Also,
they all also tend to require fairly large commitments on quantity (ie
10K+) before they will accept your design into their conversion
programs.  So that may not be practical for your 500-piece needs.  

I'd suggest squeezing your design into the smallest, slowest, cheapest
device that it will fit.  Be sure to check Xilinx.  Although I
personally don't care much for their architecture, they do have some
relatively low-cost programmable parts.  Or go with your zero-NRE
vendor (who is it?).



Greg Peek                     |  The opinions expressed are
greg_peek@ccm.jf.intel.com    |  my own, who else would claim them?



Article: 3136
Subject: FREE Book: "Top Verilog Problems & How To Solve Them."
From: Jake Kelly <jake@tactics.com>
Date: Wed, 10 Apr 1996 13:48:55 -0700
Links: << >>  << T >>  << A >>
We are writing a new guide for Verilog designers called "Top Verilog Problems & How To 
Solve Them." The book will be available later this year.

Here's the fun part: we will give a FREE copy of the book anyone who contributes a 
problem/solution or useful story. It's simple:

1. Send me an email with the problem you encountered, and how you solved it. You can 
also send an interesting Verilog anecdote.

2. Tell me whether you want attribution ("contributed by Joe Shmoe at XYZ Co.") or not. 
We're happy to make it anonymous if you want. 

3. Be sure to include the address where you want us to send your FREE book.

Examples:

"One of the most difficult problems I have had to solve is modeling an ABC circuit. The 
challenge is the timing... Here's what we did..."

"We once spent three days trying to figure out why Verilog couldn't handle a relatively 
simple design..."

That's it! Please send me email if you have any questions. Please do not respond to the 
list. 

Thanks!

Jake Kelly
TACTICS
phone +1 408-298-2200
email jake@tactics.com


Article: 3137
Subject: Re: Help: logic design on a PC
From: Bob Elkind <eteam@aracnet.com>
Date: Thu, 11 Apr 1996 02:18:06 +0100
Links: << >>  << T >>  << A >>
Alberto C Moreira wrote:
> 
> I'm looking for an HDL or VHDL implementation that runs on a PC platform,
> preferably on Win95. I need to design and simulate the implementation of
> a few parallel algorithms. Can anybody point me to a package that I can
> obtain without resorting to a second mortgage ? Thanks...
> 
> Alberto

Alberto,

If you try a web search on keyword "VHDL", you will find a treasure
trove of info.

PC-based VHDL tools I've seen so far:

ViewLogic  (oops, this is in the 2nd mortgage category :-) )

Accolade   I don't know how much this puppy costs, but they have a
           free downloadable (demo) version on their web page, it
           looks real slick, and it runs under NT.  The demo SW (I believe)
           will compile and simulate a limited number of lines of code.
             see www.acc-eda.com

Veriwell   Freeware version *Verilogs* compiler that compile up to 1K lines
           of code.  Written by Wellsprings Solutions.  DOS and Win version.
            email to:  info@wellspring.com
            Telephone:   1-508-865-7271 between 9am-5pm EST
            BBS/Fax:  1-508 865-1113

I hope this helps!

Bob Elkind

**************************************************************************
Bob Elkind                email:eteam@aracnet.com             CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************


Article: 3138
Subject: PDW'96 Final Program
From: robins@.cs.Virginia.EDU (Gabriel Robins)
Date: Thu, 11 Apr 1996 06:49:06 GMT
Links: << >>  << T >>  << A >>

Dear Colleagues,

Below is the final program for the 1996 ACM/SIGDA Physical Design Workshop,
which is taking place next week in Reston, Virginia.

This year's program will emphasize deep-submicron and high-performance
issues, and will also feature a special track on micro electromechanical
systems (MEMS), chaired by Ken Gabriel of ARPA and Kris Pister of UCLA.  
The Keynote address will be delivered by Professor C. L. Liu of the
University of Illinois at Urbana-Champaign.

PDW'96 is co-sponsored the U.S. National Science Foundation; for more
information, please see:

      http://www.cs.virginia.edu/~pdw96/

Thanks,

Gabe

======================================================
Name:           Prof. Gabriel Robins
                General Chair, PDW'96
U.S. Mail:      Department of Computer Science
                Thornton Hall
                University of Virginia
                Charlottesville, VA 22903-2442
Phone:          (804) 982-2207
FAX:            (804) 982-2214
E-mail:         robins@cs.virginia.edu
WWW:            http://www.cs.virginia.edu/~robins/
======================================================

=============================================================================

                           FINAl PROGRAM

               Fifth ACM/SIGDA Physical Design Workshop
 April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA

                  http://www.cs.virginia.edu/~pdw96/


The ACM/SIGDA Physical Design Workshop (PDW'96) provides a relaxed
atmosphere for exchange of ideas and promotes research in critical
subareas of physical design for VLSI systems.

This year's workshop emphasizes deep-submicron and high-performance
issues, and also provides a special focus on opportunities in CAD for
micro electromechanical systems (MEMS).  There are four outstanding
panel sessions:

 (1) future needs and directions for deep-submicron physical design,

 (2) physical design needs for MEMS,

 (3) manufacturing and yield issues in physical design, and 

 (4) critical disconnects in design views, data modeling, and back-end
     flows (e.g., for physical verification).

There are also many outstanding technical paper sessions.
Free-flowing discussion will be promoted through the limited workshop
attendance, the poster session and the "open commentary" mechanism in
each technical session, as well as a concluding open problems session.
During the workshop, a benchmarks competition will occur in the areas
of netlist partitioning and performance-driven cell placement.

=============================================================================
                           SUNDAY, APRIL 14
=============================================================================

6:00pm-8:30pm: Registration
  (the registration desk will also be open 8:00am-5:00pm on Monday
  and 8:00am-12:00pm on Tuesday)

7:00pm-8:30pm: Reception (refreshments provided)

=============================================================================
                           MONDAY, APRIL 15
=============================================================================

8:30am-8:40am: Welcome

8:40am-10:00am: Session 1, Timing-Driven Interconnect Resynthesis

  Session Chair: E. S. Kuh (UC Berkeley)

  Interconnect Layout Optimization by Simultaneous Steiner Tree
  Construction and Buffer Insertion, T. Okamoto and J. Cong (UC Los Angeles)

  Simultaneous Routing and Buffer Insertion for High Performance
  Interconnect, J. Lillis, C.-K. Cheng and T.-T. Y. Lin (UC San Diego)

  Timing Optimization by Redundancy Addition/Removal, L. A. Entrena, E. Olias
  and J. Uceda (U. Carlos III of Madrid and U. Politecnica of Madrid) 

  Open Commentary - Moderators: D. D. Hill (Synopsys),
                                P. Suaris (Interconnectix)

10:00am-10:20am: Break (refreshments provided)

10:20am-12:00pm: Session 2, Interconnect Optimization

  Session Chair: C. L. Liu (U. Illinois Urbana-Champaign)

  Optimal Wire-Sizing Formula Under the Elmore Delay Model, 
  C.-P. Chen, Y.-P. Chen and D. F. Wong (U. Texas Austin)

  Reducing Coupled Noise During Routing, A. Vittal and M. Marek-Sadowska 
  (UC Santa Barbara) 

  Simultaneous Transistor and Interconnect Sizing Using General
  Dominance Property, J. Cong and L. He (UC Los Angeles)

  Hierarchical Clock-Network Optimization, D. Lehther, S. Pullela, 
  D. Blaauw and S. Ganguly (Somerset Design Center, Motorola) 

  Open Commentary - Moderators: D. D. Hill (Synopsys),
                                M. Lorenzetti (Mentor)

12:00pm-2:00pm: Lunch

  Workshop Keynote Address: Prof. C. L. Liu, U. Illinois Urbana-Champaign
  Algorithmic Aspects of Physical Design of VLSI Circuits

2:00pm-2:45pm: Session 3, A Tutorial Overview of MEMS

  Speaker: K. J. Gabriel (ARPA)

2:45pm-3:00pm: Break

3:00pm-4:15pm: Session 4, Physical Design for MEMS

  Session Chair: K. J. Gabriel (ARPA)

  Physical Design for Surface Micromachined MEMS, G. K. Fedder and
  T. Mukherjee (Carnegie-Mellon U.)

  Consolidated Micromechanical Element Library, R. Mahadevan and
  A. Cowen (MCNC)

  Synthesis and Simulation for MEMS Design, E. C. Berg, N. R. Lo,
  J. N. Simon, H. J. Lee and K. S. J. Pister (UC Los Angeles)

4:15pm-4:30pm: Break (refreshments provided)

4:30pm-6:00pm: Session 5, Panel: Physical Design Needs for MEMS

  Moderator: K. S. J. Pister (UC Los Angeles)

  Panelists include:
    S. F. Bart (Analog Devices)
    G. K. Fedder (Carnegie-Mellon U.)
    K. J. Gabriel (ARPA)
    I. Getreu (Analogy)
    R. Grafton (NSF)
    R. Harr (ARPA)
    R. Mahadevan (MCNC)
    J. E. Tanner (Tanner Research)

6:00pm-8:00pm: Dinner

8:00pm-9:30pm: Session 6, Panel: Deep-Submicron Physical Design:
                          Future Needs and Directions

  Moderator: N. Mokhoff (Managing Editor, EE Times)

  Panelists include:
    T. C. Lee (President/CEO, Neo Paradigm Labs)
    L. Scheffer (Architect, Cadence) 
    W. Vercruysse (UltraSPARC III CAD Manager, Sun) 
    M. Wiesel  (Design Manager, Intel) 
    T. Yin (VP R&D, Avant! Corporation) 

=============================================================================
                          TUESDAY, APRIL 16
=============================================================================

8:30am-9:50am: Session 7, Partitioning

  Session chair: D. F. Wong (U. Texas Austin)

  VLSI Circuit Partitioning by Cluster-Removal Using Iterative Improvement 
  Techniques, S. Dutt and W. Deng (U. Minnesota and LSI Logic)

  A Hybrid Multilevel/Genetic Approach for Circuit Partitioning,
  C. J. Alpert, L. Hagen and A. B. Kahng (UC Los Angeles and Cadence)

  Min-Cut Replication for Delay Reduction, J. Hwang and A. El Gamal
  (Xilinx and Stanford U.)

  Open Commentary - Moderators: J. Frankle (Xilinx),
				G. Zimmermann (U. Kaiserslautern)

9:30am-10:10am: Break refreshments provided)

10:10am-11:50am: Session 8, Topics in Hierarchical Design

  Session Chair: M. Sarrafzedah (Northwestern U.)

  Two-Dimensional Datapath Regularity Extraction, R. X. T. Nijssen and 
  J. A. G. Jess (TU Eindhoven)

  Hierarchical Net Length Estimation, W. Hebgen and G. Zimmermann 
  (U. Kaiserslautern)

  Exploring the Design Space for Building-Block Placements Considering
  Area, Aspect Ratio, Path Delay and Routing Congestion,  H. Esbensen and 
  E. S. Kuh (UC Berkeley)

  Genetic Simulated Annealing and Application to Non-Slicing Floorplan
  Design, S. Koakutsu, M. Kang and W. W.-M. Dai (Chiba U. and UC Santa Cruz) 

  Open Commentary - Moderators: L. Scheffer (Cadence),
				T. Yin (Avant! Corporation)

11:50pm-1:30pm: Lunch

1:30pm-3:00pm: Session 9, Poster Session

  Physical Layout for Three-Dimensional FPGAs, M. J. Alexander, J. P.
  Cohoon, J. L. Colflesh, J. Karro, E. L. Peters and G. Robins (U. of Virginia)

  Efficient Area Minimization for Dynamic CMOS Circuits, B. Basaran
  and R. A. Rutenbar (Carnegie-Mellon U.)

  A Fast Technique for Timing-Driven Placement Re-engineering,
  M. Hossain, B. Thumma and S. Ashtaputre (Compass Design Automation)

  Over-the-Cell Routing with Vertical Floating Pins, I. Peters, P. Molitor
  and M. Weber (U. Halle and Deuretzbacher Research GmbH)

  Congestion- Balanced Placement for FPGAs, Y. Sun, R. Gupta and C. L. Liu 
  (Altera and U. Illinois Urbana-Champaign)

  Fanout Problems in FPGA, K.-H. Tsai, M. Marek-Sadowska and S. Kaptanoglu
  (UC Santa Barbara and Actel)

  Performance-Driven Layout Synthesis: Optimal Pairing & Chaining
  A. J. Velasco, X. Marin, J. Reira, R. Peset and J. Carrabina
  (U. Autonoma de Barcelona and Philips Research Labs Eindhoven)

  Clock-Delayed Domino for Adder and Random Logic Design, G. Yee and 
  C. Sechen (U. Washington)

3:00pm-4:00pm: Session 10, Manufacturing/Yield Issues I

  Session Chair: Eby G. Friedman (U. Rochester)

  Layout Design for Yield and Reliability, K. P. Wang, M. Marek-Sadowska 
  and W. Maly (UC Santa Barbara and Carnegie-Mellon U.)

  Yield Optimization in Physical Design, V. K. R. Chiluvuri (Motorola) 
  (invited survey paper)

4:00pm-4:15pm: Break

4:15pm-5:45pm: Session 11, Panel: Manufacturing/Yield Issues II

  Moderator: L. G. Jones (Motorola)

  Panelists include:
    V. K. R. Chiluvuri (Motorola)
    I. Koren (U. Massachusetts Amherst)
    J. Burns (IBM Watson Research Center)
    W. Maly (Carnegie-Mellon U.)

5:45pm-7:30pm: Dinner

7:30pm-8:00pm: Session 12a, Design Views in Routing

  Session Chair: B. T. Preas (Xerox PARC)

  A Gridless Multi-Layer Channel Router Based on Combined Constraint Graph
  and Tile Expansion Approach, H.-P. Tseng and C. Sechen (U. Washington)

  A Multi-Layer Chip-Level Global Router, L.-C. E. Liu and C. Sechen
  (U. Washington)

8:00pm-9:30pm: Session 12b, Panel: Design Views, Data Modeling and Flows: 
                                   Critical Disconnects

  Moderator: A. B. Kahng (UC Los Angeles)

  Panelists include:
    W. W.-M. Dai (UC Santa Cruz and Ultima Interconnect Technology, Inc.)
    L. G. Jones (Motorola)
    D. Lapotin (IBM Austin Research Center)
    E. Nequist (VP R&D, Cooper & Chyan)
    R. Rohrer (Fellow, Avant! Corporation)
    C. Palesko (VP, Savantage)

=============================================================================
                         WEDNESDAY, APRIL 17
=============================================================================

8:30am-9:50am: Session 13, Performance-Driven Design

  Session Chair: M. Marek-Sadowska (UC Santa Barbara)

  A Graph-Based Delay Budgeting Algorithm for Large Scale Timing-Driven
  Placement Problems, G. E. Tellez, D. A. Knol and M. Sarrafzadeh 
  (Northwestern U.)

  Reduced Sensitivity  of Clock Skew Scheduling to Technology Variations,
  J. L. Neves and E. G. Friedman (U. Rochester) 

  Multi-Layer Pin Assignment for Macro Cell Circuits, L.-C. E. Liu and
  C. Sechen (U. Washington)

  Open Commentary - Moderator: J. Cong (UC Los Angeles)

9:50pm-10:10pm: Break (refreshments provided)

10:10am-11:30am: Session 14, Topics in Layout

  Session Chair: D. D. Hill (Synopsis)

  Constraint Relaxation in Graph-Based Compaction, S.-K. Dong, P. Pan,
  C. Y. Lo and C. L. Liu (Silicon Graphics, Clarkson U., Lucent Technologies, 
  U. Illinois)

  An O(n) Algorithm for Transistor Stacking with Performance Constraints,
  B. Basaran and R. A. Rutenbar (Carnegie-Mellon U.)

  Efficient Standard Cell Generation When Diffusion Strapping is Required,
  B. Guan and C. Sechen (Silicon Graphics and U. Washington)

  Open Commentary - Moderator: D. D. Hill (Synopsys),
			       E. G. Friedman (U. Rochester)

11:30am-12:00pm: Session 15, Open Problems

  Moderators: A. B. Kahng (UC Los Angeles), B. T. Preas (Xerox PARC)

12:00pm-2:00pm: Lunch (and benchmark competition results)

2:00pm: Workshop adjourns

=============================================================================
                       TRAVEL AND ACCOMODATIONS
=============================================================================

PDW '96 is being held at the Sheraton Reston in Reston, Virginia, near
Washington, D.C.  The hotel is minutes from Dulles International
Airport (IAD), and 24-hour courtesy shuttles are available from the
airport to the hotel.  The area is also served by Washington National
Airport (DCA), about 20 miles away, and Baltimore-Washington
International Airport (BWI), about 50 miles away.

The Sheraton Reston is located at:
  11810 Sunrise Valley Drive
  Reston, Virginia 22091
  phone: 703-620-9000
  fax: 703-860-1594
  reservations: 800-392-ROOM

*** Please make your room reservation directly with the Reston ***
*** Sheraton hotel at the phone number above.                  ***

Room prices are $95 per night for single occupancy, and $105 per night
for double occupancy.

Driving directions from Dulles Airport: take the Washington Dulles
Access and Toll Road (route 267) to the Reston Parkway Exit (3).  Turn
right at the light after paying toll.  Take the next left onto Sunrise
Valley Drive, and continue for a couple blocks to the Sheraton (on
your left).

The Washington D.C. evening weather tends to be chilly in April, so
warm dress is suggested for the outdoors.

=============================================================================
                     SIGHTSEEING AND ATTRACTIONS
=============================================================================

The Nation's Capitol offers much in the way of sightseeing.  The most
popular destinations are located in downtown Washington D.C.,
surrounding several square miles of park area known as the "National
Mall."  There is no charge to visit the National Memorials located on
the Mall, which include the Washington Monument, where you may ascend
555 feet to an observation post; the Lincoln Memorial, whose design
adorns the back of the US penny; the Jefferson Memorial, which
includes a 19-foot bronze statue of Thomas Jefferson; and the Vietnam
Memorial, a long wall of black Indian granite dedicated in 1982.

The Smithsonian Institution (telephone (202) 357-2700) operates a
number of superb museums that flank the National Mall, including:

  Freer Gallery of Art (Asian and 19th and 20th-century American art)
  Hirshhorn Museum and Sculpture Garden (modern and contemporary art)
  National Air and Space Museum (history of aviation and space exploration)
  National Museum of African Art (collection and study of African art)
  National Museum of American Art (paintings, graphics, and photography)
  National Museum of American History (technology and culture in America)
  National Museum of Natural History (history of the natural world)
  National Portrait Gallery (portraits of distinguished Americans)
  National Postal Museum (history of postal communication and philately)
  Sackler Gallery of Asian art (from ancient to present)

Other attractions and tours around the D.C. area include (please call
the numbers below for schedules):

  Arlington National Cemetary (703) 697-2131
  Bureau of Engraving and Printing (202) 622-2000
  Congressional buildings (202) 225-6827
  FBI Headquarters (202) 324-3447
  Library of Congress (202) 707-5000
  National Aquarium (202) 482-2825
  National Archives (202) 501-5000
  National Zoological Park (202) 673-4821
  The Pentagon (703) 695-1776
  Supreme Court (202) 479-3030
  Treasury Department (202) 622-2000
  The White House (202) 456-7041

There are a number of reasonably priced eating places on the Mall; the
East Wing of National Gallery and the Air and Space Museums offer good
food and a place to sit down after sightseeing.  Provisions will be
made for low-cost transportation to and from the Mall and downtown
Washington D.C., so bring your camera and strolling shoes and enjoy
our Nation's Capital!

=============================================================================
WORKSHOP ORGANIZATION
=============================================================================

General Chair: 

  G. Robins (U. of Virginia)

Technical Program Committee:

  C. K. Cheng (UC San Diego)
  J. P. Cohoon (U. of Virginia)
  J. Cong (UC Los Angeles)
  A. Domic (Cadence)
  J. Frankle (Xilinx)
  E. Friedman (Rochester)
  D. Hill (Synopsys)
  L. Jones (Motorola)
  A. B. Kahng (UC Los Angeles, Chair)
  Y.-L. Lin (Tsing Hua)
  K. Pister (UC Los Angeles)
  M. Marek-Sadowska (UC Santa Barbara)
  C. Sechen (Washington)
  R.-S. Tsay (Avant!)
  G. Zimmermann (Kaiserslautern)

Steering Committee:

  M. Lorenzetti (Mentor Graphics)
  B. Preas (Xerox PARC)

Keynote Address:

  C. L. Liu (Illinois)

Benchmarks Co-Chairs:

  F. Brglez (NCSU)
  W. Swartz (TimberWolf Systems)

Local Arrangements Chair:

  M. J. Alexander (U. of Virginia)

Treasurer:

  S. B. Souvannavong (HIMA)

Publicity Chair:

  J. L. Ganley (Cadence)

Sponsors:

  ACM / SIGDA
  U.S. National Science Foundation
  Avant! Corporation

=============================================================================
                        WORKSHOP REGISTRATION
=============================================================================

               Fifth ACM/SIGDA Physical Design Workshop
 April 15-17, 1996 - The Sheraton Reston Hotel, Reston, Virginia USA

Name: _______________________________________________________________

Company/University: _________________________________________________

Title: ______________________________________________________________

Address: ____________________________________________________________

City: _________________________________________ State: ______________

Phone: ____________________________ Email: __________________________


                Registration Fees
              (Includes All Meals)

ACM Members         __ $440
Non-ACM             __ $540
Students            __ $250

         ACM Membership Number: _____________________________

         Dietary restrictions, if any: ______________________

         Special needs: _____________________________________

The registration fee includes the workshop proceedings and all meals
(i.e., 3 breakfasts, 3 lunches, and 2 dinners), refreshments during
breaks, and a reception on Sunday evening.  The total number of
attendees is limited (registrations will be returned if the workshop
is oversubscribed).

*** Note: Hotel reservations must be made directly with the Sheraton ***
*** Call (703) 620-9000 to make a room reservation at the Sheraton.  ***

The only acceptable forms of payment are checks (personal, company,
and certified/bank checks) in US funds drawn on a US bank and made
payable to "Physical Design Workshop 1996" (credit cards will not be
accepted).  Payment must accompany your registration. No FAX or Email
registrations will be processed.

Please mail your payment (checks only) along with this registration form to:

  Sally Souvannavong, Treasurer
  1996 ACM/SIGDA Physical Design Workshop
  Department of Computer Science
  Thornton Hall
  University of Virginia
  Charlottesville, VA 22903-2442 USA

  Phone: (804) 982-2200
  Email: pdw96@cs.virginia.edu

You may also register on-site (we still have room for a few more attendees).

=============================================================================



Article: 3139
Subject: Xact and Viewlogic or Foundation Software Series?
From: sim0215@iperbole.bologna.it (Gabriele Bucci)
Date: Thu, 11 Apr 1996 11:55:07 GMT
Links: << >>  << T >>  << A >>
Xilinx Xact and Viewlogic or Xilinx Foundation Software Series?

I have to choose a Xilinx development tools for PC.
A salesman show me two Windows based schematic capture:
the well known Viewlogic, and Foudation Series; for [non 
Windows based :) ] xact.
Foudation series is cheep (compared with Viewlogic 
PRO series for Windows), and at first glance look 
more convenient (with VHDL and ABEL included!).
Does anyone have experience on both the system and 
help me in this choice?   
Your suggestion will be welcome and MORE appreciate.

Gabriele Bucci.



Article: 3140
Subject: Re: Help: logic design on a PC
From: Rune Baeverrud <r@acte.no>
Date: Thu, 11 Apr 1996 17:08:30 +0200
Links: << >>  << T >>  << A >>
Alberto C Moreira wrote:
> 
> I'm looking for an HDL or VHDL implementation that runs on a PC platform,
> preferably on Win95. I need to design and simulate the implementation of
> a few parallel algorithms. Can anybody point me to a package that I can
> obtain without resorting to a second mortgage ? Thanks...
> 
> Alberto

Check out Cypress if you want VHDL. They are just releasing a new 
version of Warp2 - a Win 95 compatible package with full VHDL support.
I guess you have to pay around US$100 or so for the package.

_-_rune_-_


Article: 3141
Subject: 8051-type macrocell available
From: icdcbob@netcom.com (Robert F. Calderwood)
Date: Thu, 11 Apr 1996 15:52:45 GMT
Links: << >>  << T >>  << A >>
The physical design of our 8051-type macrocell has just been
completed. This new offering complements our structured gate-level
netlist for the popular microcontroller. Licenses are available starting
at US$2995 for a single use. More detalis can be obtained at
http://universe.digex.net/~icdc/uc51macr.html
or reply to this post.
-- 
__________________________________________________________________________
 _   ____      __  ____    ____
| | |  __|    / / |  _ \  |  __|    Integrated Circuit Design Concepts
| | | |      / /  | | | | | |      12502 Carmel Way, Santa Ana CA 92705
| | | |__   / /   | |_| | | |__   Voice (714) 633-0455 Fax (714) 838-7705
|_| |____| /_/    |____/  |____|     http://universe.digex.net/~icdc/
__________________________________________________________________________


Article: 3142
Subject: Re: Help: logic design on a PC
From: Alberto C Moreira <alberto@moreira.mv.com>
Date: Fri, 12 Apr 1996 02:07:07 GMT
Links: << >>  << T >>  << A >>
Alex, thanks for your help!    _alberto_




Article: 3143
Subject: Re: Help: logic design on a PC
From: Alberto C Moreira <alberto@moreira.mv.com>
Date: Fri, 12 Apr 1996 02:08:31 GMT
Links: << >>  << T >>  << A >>
Bob, thanks a lot for the info; it was warmly appreciated!

Alberto



Article: 3144
Subject: ACTEL design with Synopsys
From: b1052 <b1052@scn.de>
Date: Fri, 12 Apr 1996 12:55:35 +0200
Links: << >>  << T >>  << A >>
Hi,
when synthesizing a VHDL design with Synopsys Design Compiler into an
act3 lib and transfering it to the Designer software from Actel I get
errors because non-clock pins use a clock net. The reason is that Design
Compiler puts "complex" cells on clock nets; the also used inverters are
not flagged with errors.
Has somebody an idea how I can avoid this?

TIA
  Guido
-- 
Guido Kinast           Siemens AG,  AUT E721             Fuerth, Germany
b1052@scn.de          http://www.scn.de/~b1052          +49 911 750 2720


Article: 3145
Subject: Re: VHDL conversion function from int to time ...?
From: William Billowitch <wdb@vhdl.com>
Date: Fri, 12 Apr 1996 08:31:34 -0400
Links: << >>  << T >>  << A >>
Our Std_IOpak handles the conversions you require. Please
check the web site.

-- 
Sincerely,

----------------------------------------------------------
---
William Billowitch                   e-mail: wdb@vhdl.com
The VHDL Technology Group            Web:    
http://www.vhdl.com  
100 Brodhead Road, Suite 140         Phone : 610-882-3130
Bethlehem, PA 18017                  Fax   : 610-882-3133


Article: 3146
Subject: Re: VHDL conversion function from int to time ...?
From: mench@mercury.interpath.com (Paul J Menchini - Menchini and Associates)
Date: 12 Apr 1996 23:11:17 GMT
Links: << >>  << T >>  << A >>
Vijay A Nebhrajani (vijayn@cdac.ernet.in) wrote:
: Anyone know of a function on Synopsys to convert time to integer and vice versa?
: How could such a function be written, if it were not available readymade?

package Conversions is

    function cvTime (Int: Integer; ScaleFactor: Time := ns) return Time;
    function cvInt  (Tim: Time   ; ScaleFactor: Time := ns) return Integer;

end Conversions;

package body Conversions is

    function cvTime (Int: Integer; ScaleFactor: Time := ns) return Time is
    begin
	return Int * ScaleFactor;
    end cvTime;

    function cvInt  (Tim: Time   ; ScaleFactor: Time := ns) return Integer is
    begin
	return Int / ScaleFactor;
    end cvInt;

end Conversions;

Hope this helps,

Paul

--
Paul Menchini         | email: mench@mench.com | WWW: http://www.mench.com/
Menchini & Associates | voice: 919-990-9506    | "Se tu sarai solo,
2 Davis Dr./POB 13036 | pager: 800-306-8494    |  tu sarai tutto tuo."
RTP, NC  27709-3036   | fax:   919-990-9507    |	-- Leonardo Da Vinci


Article: 3147
Subject: Re: ACTEL design with Synopsys
From: rons@inow.com
Date: 14 Apr 1996 02:24:01 GMT
Links: << >>  << T >>  << A >>
In <316E36A7.2781E494@scn.de>, b1052 <b1052@scn.de> writes:
>Hi,
>when synthesizing a VHDL design with Synopsys Design Compiler into an
>act3 lib and transfering it to the Designer software from Actel I get
>errors because non-clock pins use a clock net. The reason is that Design
>Compiler puts "complex" cells on clock nets; the also used inverters are
>not flagged with errors.
>Has somebody an idea how I can avoid this?
>
>TIA
>  Guido
>-- 
>Guido Kinast           Siemens AG,  AUT E721             Fuerth, Germany
>b1052@scn.de          http://www.scn.de/~b1052          +49 911 750 2720

Synopsys attempts to reserve a 'clock pad' for any signal that terminates
at some point in a 'clock' node, no matter what the logic path.

To prevent the 'clock pad' selection, add the following in the script for
each pad that you DON'T want to reserve a 'clock pad'.

       set_pad_type -no_clock <pad instance name>

rons@inow.com


Article: 3148
Subject: Crosspoint Solutions
From: Charles Gardiner <"100421,3461"@compuserve.com>
Date: Sun, 14 Apr 1996 01:24:37 -0700
Links: << >>  << T >>  << A >>
Does anyone know if Crosspoint Solutions Inc., a FPGA manufacturer based 
in milpitas CA, have a page on the WWW?

Thanks in advance,

Charles


Article: 3149
Subject: One Week to Boston
From: sbaker@best.com
Date: 15 Apr 1996 03:25:02 GMT
Links: << >>  << T >>  << A >>


ONE WEEK TO BOSTON

This is a note to remind all that PLDConí96, the PLD design conference for system designers 
begins in Boston (Burlington Marriott, actually) next Monday.

The Conference will be repeated in Dallas on May 20, 21 (Grand Kapinsky Hotel)

Iím pointing this out because we have had a little trouble with our faxback support 
for inquiries and registration and I want all to know that if you have any questions or want to register, 
to contact my office: 
-- sbaker@best.com, 
-- 408-356--5119 
-- fax 408-356-9018.

This year we have an outstanding tutorial-oriented 2-day program (independent expert lecturers) with tracks on:
-- the latest design techniques,
-- FPGAs for gate array users
-- reconfigurable computing
-- introduction to HDLs.

cordially,
Stan Baker








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