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Messages from 6075

Article: 6075
Subject: Wanted - Industry Experts to Write for Engineering Magazine
From: Brian Lloyd Bishop <blbishop@pacbell.net>
Date: Wed, 09 Apr 1997 22:09:04 -0700
Links: << >>  << T >>  << A >>
Personal Engineering and Instrumentation News is a magazine read by over
50,000 engineers each month. We are looking for an engineer using
PC-based board layout or FPGA design packages to write an article every
other month for our magazine. The article can be a product review, a
tutorial or even an editorial. We pay for each article, but you have to
contact us to find out how much. Hey, we=92ve got to give you an incentiv=
e
to call!

Writing articles is a great way to get your name out in the field as an
expert. Many companies have incentives for employees to publish, so
check with your management to see if this might be a great deal for you. =


We don=92t require any previous publishing experience. All that we ask is=

that you have an interest in writing and respect the deadlines that our
production schedule impose.

If you are interested, please send a list of six or so proposed topics
to:

BLBPersEng@aol.com or call (916) 758-7600
-- =

Brian L Bishop
BLBPersEng@aol.com
Personal Engineering and Instrumentation News
(916) 758-7600 FAX (916) 758-7677
Article: 6076
Subject: Download Xilinx Fpga
From: Andreas Wassatsch <wa11@e-technik.uni-rostock.de>
Date: Thu, 10 Apr 1997 08:16:50 +0200
Links: << >>  << T >>  << A >>
last year wrote Ewan D. Milne (milne@cv.com is now unknown) in this
newsgroup, that he has a solution to download xilinx fpga's via the
parallel port of a sun.

has anyone the documentation for this ?

has anyone a other solution to download a xilinx fpga (xc4xxx) from a
sun without the need of the xchecker cable ?


-- =

#  Andreas Wassatsch                           Tel: +49 (0)381 498 3533
#  University Rostock                          Fax: +49 (0)381 498 1126
#  Department of Electrical Engineering
#  Institute of Applied Microelectronics and Computer Science
#  Richard-Wagner-Str. 31
#  18119 Rostock-Warnem=FCnde        email: wa11@e-technik.uni-rostock.de=

#  Germany            WWW: http://www-md.e-technik.uni-rostock.de/~wass
Article: 6077
Subject: Crosspoint Solutions FPGA???
From: Markus.Wannemacher@FernUni-Hagen.De (Markus Wannemacher)
Date: 10 Apr 1997 08:50:26 GMT
Links: << >>  << T >>  << A >>

I'm trying to get informations about the FPGAs from
Crosspoint Solutions: CP20K and CP100K.

The email adress mike@xpoint.com in not valid (xpoint.com:
Non existent host/domain).

The phone number 408 324.0200 is connected to a voice box,
but the box is full.

There is no response to fax to 408 324.0123 and letters to 
the company in Milpitas,CA.

Does anyone know if the company is still existing, if they
are producing or planning to produce FPGAs?
Or are they already bought by Xilinx?

Markus Wannemacher

----
Markus Wannemacher, FernUniverit"at Hagen, Lehrgebiet Informationstechnik
D-58084 Hagen, Germany     E-Mail: Markus.Wannemacher@FernUni-Hagen.De
phone +49 2331 987 4547    WWW:    http://www.fernuni-hagen.de/IT/wm.html
fax   +49 2331 987 375     talk:   wm@tokyo.fernuni-hagen.de   

Article: 6078
Subject: Cadence dfII Layout Plotter: which type are the best solution ?
From: Andreas Wassatsch <wa11@e-technik.uni-rostock.de>
Date: Thu, 10 Apr 1997 12:21:36 +0200
Links: << >>  << T >>  << A >>
for the preparation of a decision, which type of plotter we need, i'm
looking for comments and experiences of the use of plotters together
with the Cadence dfII Framework ! Which configuration of the
plotter is advisable ?

also an special question to the HP DesignJet 755CM: is the internal 68MB
RAM of the plotter large enough to plot on A0 a medium chip layout with
postscript? if not, who about the HP/GL plot ?

-- =

#  Andreas Wassatsch                           Tel: +49 (0)381 498 3533
#  University Rostock                          Fax: +49 (0)381 498 1126
#  Department of Electrical Engineering
#  Institute of Applied Microelectronics and Computer Science
#  Richard-Wagner-Str. 31
#  18119 Rostock-Warnem=FCnde        email: wa11@e-technik.uni-rostock.de=

#  Germany            WWW: http://www-md.e-technik.uni-rostock.de/~wass
Article: 6079
Subject: Re: Pentium Pro Worth it for Altera Max Plus? (subject drifting to P+R speeds)
From: Steve Wiseman <steve@sj.co.uk>
Date: Thu, 10 Apr 1997 12:27:29 +0100
Links: << >>  << T >>  << A >>
Dave Grace wrote:

> It is one thing to place & route a design quickly that only needs to run
> at 10 MHz. What about 40 or 50 MHz? Are you putting any timing
> constraints on the design. Marketing from both Altera and anybody else
> will tell you that the P&R tools are fast, but how "really" how fast are
> they when they are constrained with timing!
> 
> I am sure that all of us are curious!

That's for a design running with 2 unsynchronised clocks, both at 32MHz,
each covering roughly 1/2 the device. The boundaries between the halves
are simple and carefully designed to not collapse under clock-stop /
clock-slip conditions. The Altera tools _seem_ to slow down less under
timing constraints than the Xilinx ones, certainly on a rule set as
simple as 'it all goes at 32MHz'. Perhaps if I could isolate bits of the
circuit that run slower (extremely non-trivial, given the VHDL source),
I could get far better performance, but, as yet, I don't need to. 

There are sections of the code that I know run at 1/5 of the clock
speed, but it's hard to explain that to the toolset, given that the node
names change randomly per compile. Any hints? 

(An aside, if one buys 'serious' FPGA tools, does this kind of
functionality start happening? At what price level? It's something I'd
like, but I don't know if my customers will favour the trade for more
expensive tools against cheaper devices.)

Steve
Article: 6080
Subject: Re: viewoffice <--> viewoffice compatibility
From: chan_isd@accesscom.com (Scott Evans)
Date: Thu, 10 Apr 97 14:50:17 GMT
Links: << >>  << T >>  << A >>
In article <01bc3b05$0c8a5980$6e0db780@Rich>, "Rich K." <rich.katz@gsfc.nasa.gov> wrote:
This is the way the restricted license works.  Any files created using an 
unrestricted license can only be read by an unrestricted license no matter 
what library you have used.  Any files created using a restricted license can 
be read by any unrestricted and also a similar restricted license.  

If you have a mixed environment it will cause you less grief to upgrade all 
seats to unrestricted but it will cost you $'s so you have a time vs. money 
trade-off to make.  Viewlogic is supposed to give you credit for any 
restricted system you have bought to help defray some of the $'s, be sure to 
ask them about this.

As some posters pointed out, you can create the needed keys by saving a 
schematic with the restricted key and placing that into your file, this is 
quite painful though.

>this is correct.  however, it's odd that i can't read actel files generated
>on (viewlogic) viewoffice 7.2 in viewoffice 7.2 on an actel-sold actel
>development station which is perfectly capable of working with actel
>designs, and uses IDENTICAL software, and was bought and sold and licensed
>to work on actel designs.
>
>apparently, the implication is that if you have a number of seats, say some
>'full' viewlogic seats, which are capable of doing actels, and some
>actel-only seats, which are capable of doing actels, you can not work on
>the same actel design together and the cheap sets must be upgraded to have
>capability to do non-actel stuff (which is not needed) or the expensive
>seats must be downgraded to be cheap sets (which is not desired since we
>want to do other things some of the time with a small number of the seats).
>
>i am continuing to attempt to resolve this with viewlogic, so far it looks
>like the viewoffice (actel design) <--> viewoffice (actel design)
>compatibility problem is solved by sending  $; i am attempting now to find
>out how many digits is required and the value of the leading digit.  a
>previous poster has asked that i post the answer and i will, as soon as i
>have one, as many of us may run into the same problem.
>
>thanks for the help,
>
>rk
>
>p.s. yes, the viewlogic purchased seat can read stuff from the actel
>purchased seat; it's going the other way that it's a problem.
>
>-------------------------------------------------------------
>
>Steven K. Knapp <optmagic@ix.netcom.com> wrote in article
><01bc3acc$e7e03060$b6bfb8cd@default>...
>> I think this may be due to the licensing of the Actel product.  The copy
>> bought from VIEWlogic is probably unrestricted and should be able to read
>> files originally created by the Actel seats.  However, the Actel seats
>will
>> not be able to read designs initially created on the VIEWlogic seats.  It
>> all has to do with the keying saved in the files.
>> -- 
>> Steven Knapp
>> E-mail:  optmagic@ix.netcom.com
>> Programmable Logic Jump Station:  http://www.netcom.com/~optmagic
>> 
>> Rich K. <rich.katz@gsfc.nasa.gov> wrote in article
>> <01bc3938$7b4989a0$6e0db780@Rich>...
>> | hi,
>> | 
>> | the subject may seem silly but it is not.  previously, i had posted a
>> | question about viewoffice <--> viewoffice file compatibility.  i have
>run
>> | some tests and found that for a viewoffice system derived from a pro
>> series
>> | license (bought from actel) and a viewoffice system derived from
>workview
>> | plus (bought from viewlogic) could not exchange schematic files
>> | representing an actel fpga design.
>> | 
>> | i have e-mailed viewlogic a bunch of times on this, sent license files,
>> | asked what restrictions and capabilities there are for each of the
>> | licenses, and the answer i have received to solve this problem is
>between
>> | the square brackets, two lines below this one:
>> | 
>> |     []
>> | 
>> | so, do any experienced viewlogic
>> | users/customers/fae's/critics/supporters/abusers/whateverers have any
>> | ideas?  i now have 3 viewlogic seats networked together (pc's derived
>> from
>> | workview plus) and two dormant actel-bought/derived viewlogic licenses
>> and
>> | need to activate them as we have 1 or 2 new designers joining.  what do
>i
>> | do?  i don't mind paying the required maintenance fees and all but i
>need
>> | to have each of the designers' systems being compatible with one
>another.
>> 
>> | having all of the seats being viewlogic and the same revision seemed
>> | initially to be a good idea.
>> | 
>> | has anyone tried this before?  did my pc have a bad hair day?
>> | 
>> | any thoughts or advice?
>> | 
>> | thanks,
>> | 
>> | rk
>> | 
>> 
Article: 6081
Subject: Re: Download Xilinx Fpga
From: milne@hi.com (Ewan D. Milne)
Date: 10 Apr 1997 14:58:39 GMT
Links: << >>  << T >>  << A >>
Andreas Wassatsch (wa11@e-technik.uni-rostock.de) wrote:
: last year wrote Ewan D. Milne (milne@cv.com is now unknown) in this
: newsgroup, that he has a solution to download xilinx fpga's via the
: parallel port of a sun.

: has anyone the documentation for this ?

: has anyone a other solution to download a xilinx fpga (xc4xxx) from a
: sun without the need of the xchecker cable ?

I've changed jobs recently (now at Hitachi Computer Products).
I still have the test board and the rough schematics along with the
notes about the parallel interface.  I'll have to get the program that
downloads the bitstream off my backup tapes, which might take a while.
I'm not using a Sun workstation at the moment, so I can't use it myself.

Send me some mail (see the mail address above -- you have to remove
the [remove] part) if you want the stuff and I'll try to get it to you.

Ewan
Article: 6082
Subject: Re: prep benchmarks for FPGAs
From: jbuck@synopsys.com (Joe Buck)
Date: 10 Apr 1997 17:03:41 GMT
Links: << >>  << T >>  << A >>

peter@xilinx.com (Peter Alfke) writes:
[ Good article on why PREP benchmarks are useless, followed by... ]
>They definitely destroyed any respect I might still have had for the
>technical integrity of Marketing on Orchard Parkway.

Let he who is without a marketing department cast the first stone.

Seriously, let's stick to facts around here and hold off on shots at
competitors; it just makes you look like a shill.  Explaining why the PREP
benchmarks are of no value was a service.  Leave it at that.



-- 
-- Joe Buck	http://www.synopsys.com/pubs/research/people/jbuck.html

Help stamp out Internet spam: see http://www.vix.com/spam/
Article: 6083
Subject: Re: Chip Temperature (was:Re: Sole source)
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 10 Apr 1997 10:38:22 -0700
Links: << >>  << T >>  << A >>
In article <01bc4504$281546c0$f881b6c7@default>, "Steven K. Knapp"
<optmagic@ix.netcom.com> wrote:

> Any impurity added to water increases the boiling point and decreases the
> freezing point.  This is one of the reasons that you add anti-freeze to
> your car's radiator.
> -- 
Isn' it wonderful what you can learn in this newsgroup, even about boiling spit.

Peter Alfke
Article: 6084
Subject: Re: PCI and DRAM control - Xilinx 4000 -Verilog
From: Jim McManus <jamesm@xilinx.com>
Date: Thu, 10 Apr 1997 12:41:40 -0700
Links: << >>  << T >>  << A >>
Austin Franklin wrote:
> The four words quickly PCI Xilinx and Verilog don't go well in the 
> same paragraph.

Actually, we can now use those four words in one sentence. Xilinx does
PCI in Verilog at 33MHz, as instantiated black box. Target or Master. 
We have an app note, that explains how and the design files are 
available today. Sure, it's still not pure Verilog code. But it does 
the job and allows you to do the rest of your design in Verilog (or 
VHDL if desired).

To get a copy of the app note see:
http://www.xilinx.com/products/logicore/logicore.htm


Jim

------------------------------------------------------------------------
 / 7\'7 Jim McManus                       mailto:jim.mcmanus@xilinx.com 
 \ \ `  Xilinx PCI Applications Engineer  1-800-255-7778 (toll-free)    
 / /    2100 Logic Drive                  1-408-879-4729 Fax            
 \_\/.\ San Jose, California 95124                                      
        http://www.xilinx.com/products/logicore/lounge/pci/pci.htm      
------------------------------------------------------------------------
Article: 6085
Subject: Re: comp.arch.fpga archiv dead?
From: jmarnold@potomac.znet.com (Jeffrey M. Arnold)
Date: 10 Apr 1997 13:57:23 -0700
Links: << >>  << T >>  << A >>

In article <5igfp4$nvs@ilex.FernUni-Hagen.de>,
Markus Wannemacher <Markus.Wannemacher@FernUni-Hagen.De> wrote:
>It seams, that the comp.arch.fpga archiv at
>  
>  http://www.super.org:8000/FPGA/
>
>has stopped recording new articles in August 1996.
>
>Does anyone know if there are any plans to
>bring the archiv back to live?

I was the maintainer of the archives and the majordomo reflector until
I left IDA/CCS in February 1996.  The archiver remained on autopilot
until a major system upgrade did it in several months later.  I've
been unsuccessful at finding someone else to take it over.  Any
volunteers?

-jeff

>
>Are there any other archives of this newsgroup?
>
>Markus Wannemacher
>


-- 
Jeffrey M. Arnold		jma@super.org or jmarnold@znet.com
10686 Mira Lago Terrace		Tel: 619-547-9257
San Diego, CA 92131		Fax: 619-547-9010
USA
Article: 6086
Subject: Re: viewoffice <--> viewoffice compatibility
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 10 Apr 1997 21:09:31 GMT
Links: << >>  << T >>  << A >>
hi,

i have been following up with viewlogic and viewlogic basically agrees with
what is said below.  they told me that they would credit the purchase price
of the original seat towards an upgrade and are currently running a special
where they will upgrade a seat for $3K.  Also, are ViewSim upgrades
included too?  The other tools?  price of upgrades such as unlimited
simulation gates?  I am trying to find that out.

it is still confusing why a seat restricted to actel can't read actel
designs.  this, apparently, was a design decision made by viewlogic.  and
creates the following situation: suppose your group has two actel-only (or
whatever) seats.  you upgrade one to unrestricted so you can do gate arrays
from vender Q.  Now, you have two incompatible seats in your group which
will not talk to each other for joint actel designs.  So by *upgrading* one
seat, you have diminished the power of your design 'system'.  And with
bigger FPGAs, multiple designers for a chip will become more common; we're
doing that now.  

Personally, i think the unrestricted seats should be able to generate files
for the crippled seats, perhaps in a 'save as' dialog.  One would think
that an unrestricted seat could do whatever you want it to do - and
degrading system design capability isn't really desirable.  while you state
that "it will cause you less grief to upgrade all seats to unrestricted but
it will cost you $'s" i still don't see the rationale of the viewlogic
licensing design and why we should have to pay more money to do actel
designs on an 'actel-only' seat.  removing the restriction but keeping
actel-only stations actel-only will not violate what we thought the license
was (i.e., actel-only) and don't see where any unintended use of the system
would occurr (i.e., using an actel-only system to design xilinx's, for
instance).  viewlogic has made the distinction that the seat really isn't
an actel-only seat, but an actel-only & crippled seat, although they say
the third partys don't communicate this well (and it took a while to get
this distinction from viewlogic as well, as you can tell from my earlier
posts).  from a security point of view, the 'save as' may be difficult to
implement in general.  but for fpga's, the libraries could be coded so the
system will refuse to save xilinx libraries using an actel signature.

rk

--------------------------------

Scott Evans <chan_isd@accesscom.com> wrote in article
<5iiui5$i4r$1@toasted.accesscom.com>...
> This is the way the restricted license works.  Any files created using an

> unrestricted license can only be read by an unrestricted license no
matter 
> what library you have used.  Any files created using a restricted license
can 
> be read by any unrestricted and also a similar restricted license.  
> 
> If you have a mixed environment it will cause you less grief to upgrade
all 
> seats to unrestricted but it will cost you $'s so you have a time vs.
money 
> trade-off to make.  Viewlogic is supposed to give you credit for any 
> restricted system you have bought to help defray some of the $'s, be sure
to 
> ask them about this.
> 
> As some posters pointed out, you can create the needed keys by saving a 
> schematic with the restricted key and placing that into your file, this
is 
> quite painful though.
> 

Article: 6087
Subject: Re: About the usage of Altera maxplus2
From: yqrkcszwoo@pacifier.com (St.Peter)
Date: 11 Apr 1997 07:18:21 GMT
Links: << >>  << T >>  << A >>
Lee Jae-Hyuck (starry@kumi2.lge.co.kr) wrote:
: Hello! I am using maxplus2 for EPM9560rc304 altera fpga chip. I'd like
: to make all non-used pins into
: high impedence state, but I cannot find any options in maxplus2. My
: maxplus2 version is 7.0.
: plesase tell me. thanks in advance.

Why would you want to make them so?   Why don't just make them NC
in your circuit?

---
Reply-To: and From: fields have been altered to avoid spam.

Article: 6088
Subject: Re: Pentium Pro Worth it for Altera Max Plus?
From: yqrkcszwoo@pacifier.com (St.Peter)
Date: 11 Apr 1997 07:27:20 GMT
Links: << >>  << T >>  << A >>
Dave Grace (dgwing@xilinx.com) wrote:

: at 10 MHz. What about 40 or 50 MHz? Are you putting any timing
: constraints on the design. Marketing from both Altera and anybody else
: will tell you that the P&R tools are fast, but how "really" how fast are
: they when they are constrained with timing!

Actually, with a 65% filled 10K100 my compilation time is usually 
between 1 and 1.5 hour, more if there are some unplaced pins in 
the fitter.   Putting too many constraints on the timing is not 
a very good idea with their toolset, IMHO.   A couple of maybe OK, 
but at some point, it really degrades performance for various 
reasons.    

---
Reply-To: and From: fields have been altered to avoid spam.

Article: 6089
Subject: Re: prep benchmarks for FPGAs
From: eteam@aracnet.com (bob elkind)
Date: Fri, 11 Apr 1997 15:11:30 +0100
Links: << >>  << T >>  << A >>
Owweee!  I seem to have inoccuously touched a sensitive nerve,
here.  Do you think!?

I appreciate the comments about bogus benchmarks, marketing hype,
unrealistic gate counts, etc.

I have a very simple motive for seeking PREP benchmark data
on a limited set of synthesis tools and SRAM-based FPGAs.
Here it is:  I've been developing a synthesis library for a
client, and I would like some comparison figures for assessing
how well the library works, and how well the synthesis engine
works, relative to other products and libraries and FPGAs, etc.

This is purely for my own benefit, as a relative figure of merit
with entirely arbitrary units.  Unless we've really done a
fantastic, super job, I doubt that the measurements I take
will show up in the middle of EE Times declaring how company
XYZ's whizzy products really suck (compared to company ABC, of
course!).

And I don't mind if someone from company NNN is excited about
their newest whizbang, and they want to tell me about it.
I would be very dissapointed if they *weren't* excited, be they
engineer or marketing types (you can usually tell which by the
sneakers they wear).

Having said that, anyone have some PREP synthesis benchmark
data for SRAM based FPGAs that they want to send my way?
It will be much appreciated!

-- Bob Elkind

Ron Wilson said...
> Joe Buck wrote:
> > peter@xilinx.com (Peter Alfke) writes:
> > >They definitely destroyed any respect I might still have had for the
> > >technical integrity of Marketing on Orchard Parkway.

> > Let he who is without a marketing department cast the first stone.
> > 
> > Seriously, let's stick to facts around here and hold off on shots at
> > competitors; it just makes you look like a shill.  Explaining why the PREP
> > benchmarks are of no value was a service.  Leave it at that.

> I'm afraid the vested interest here runs deeper than you might imagine.
> IMHO, what Peter was reciting was not "why PREP didn't work" but
> Xininx's constructed excuse for trying to undermine PREP. In fact, the
> PREP benchmarks--if you actually used them as intended, rather than
> swallowing the marketeers' interpretations--did a very credible job of
> predicting the performance and capacity of a particular PLD on a
> particular kind of circuit. That is the main reason that some vendors
> opposed them so vehemently, even after helping to design them.

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 6090
Subject: Re: About the usage of Altera maxplus2
From: Rolf.Blom@uab.ericsson.se (Rolf Blom)
Date: 11 Apr 1997 15:44:01 GMT
Links: << >>  << T >>  << A >>
In article <5ikojt$r9$2@news.pacifier.com>, yqrkcszwoo@pacifier.com (St.Peter) writes:
>Lee Jae-Hyuck (starry@kumi2.lge.co.kr) wrote:
>: Hello! I am using maxplus2 for EPM9560rc304 altera fpga chip. I'd like
>: to make all non-used pins into
>: high impedence state, but I cannot find any options in maxplus2. My
>: maxplus2 version is 7.0.
>: plesase tell me. thanks in advance.
>
>Why would you want to make them so?   Why don't just make them NC
>in your circuit?
>

Possibly because having them NC seem to make the pins outputs.
Not sure if it's a feature of maxplus2 or the cpld itself.

It has happened on a couple of designs with this chip.
Now we just connect unused pins to wide-input OR-gates
to make them inputs, and the chip gets much cooler.

/Rolf

Article: 6091
Subject: Cisco's SIBU is looking for ASIC and Systems Engineers
From: lshevock@diablo.cisco.com (CISCO SYSTEMS)
Date: 11 Apr 1997 15:44:10 GMT
Links: << >>  << T >>  << A >>
I am with Human Resources for the Small Internetworks Business Unit
(formerly Grand Junction) at Cisco Systems.  We develop switches, routers,
and hubs that focus on small and medium-sized companies.  Revenue-wise we
are the fastest growing Business Unit at Cisco Systems with 30+% growth
over the last five quarters.  

We are currently looking for senior and intermediate ASIC Engineers
(digital) as well as senior and intermediate Systems Engineers (embedded
CPU, FPGA) to join our team.  We are located in San Jose, California.

If you, or anyone you know is interested, please contact me or send me
your resume.  I will be happy to talk with you further about the
positions.

To send your resume:
fax:  408-527-3831 or
email:  lshevock@cisco.com
No agencies please

-- 
To send your resume:
fax:  527-0180 or
email:  lshevock@cisco.com
No agencies please
Article: 6092
Subject: Re: Sole source
From: jim granville <Jim.Granville@xtra.co.nz>
Date: Fri, 11 Apr 1997 09:25:12 -0700
Links: << >>  << T >>  << A >>
Tom Burgess wrote:
> 
> Peter Alfke wrote:
> >
> > I will soon publish here a way to use one of the input protection diodes
> > to measure chip temperature more exactly.
> > Cool! Would LOVE to see this. Curious if ground bounce creates
> measurement problems (by shifting average ground) and if so would
> it help to do a differential measurement using a nearby zero-level
> output as a reference. The chips needing temperature measurement
> will be typically (always) embedded in noisy digital environments.
> But the accuracy requirements are not high.
> 
>         regards, tom
It's a good idea, and you should be able to simply use a OHMS meter, to
measure the forward mV
of the substrate CLAMP diode - probably a TRI_STATED OUT node would be
best.
This will integrate out any AC ground noise.

Use of OHMS allows you to scale the measurement current - on the DIODE
range most meters use
1mA, but you can inject 100uA and less, using OHMS ( it still reads mV
).

As you are injecting a substrate current, I would suggest as low a level
as possible
- very funny things can happen with lateral die currents :-)

Then use the Silicon Vf temco of 2,2 mV / degrees C, and you will get
die edge temperatures.

- jim

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Article: 6093
Subject: Re: comp.arch.fpga archiv dead?
From: rauletta@erebor.cudenver.edu (Richard J. Auletta)
Date: 11 Apr 1997 17:07:16 GMT
Links: << >>  << T >>  << A >>
Jeffrey M. Arnold (jmarnold@potomac.znet.com) wrote:
: In article <5igfp4$nvs@ilex.FernUni-Hagen.de>,
: Markus Wannemacher <Markus.Wannemacher@FernUni-Hagen.De> wrote:
: >It seams, that the comp.arch.fpga archiv at
: >  
: >  http://www.super.org:8000/FPGA/
: >
: >has stopped recording new articles in August 1996.
: >
: >Does anyone know if there are any plans to
: >bring the archiv back to live?

You can try www.dejanews.com - while I'm not sure if it archives all
USENET newsgroups, I can find many of the recent postings to comp.arch.fpga
and they do go back to 1995. Altavista and other search engines also
support USENET searches.

-Rich Auletta

Article: 6094
Subject: Re: prep benchmarks for FPGAs
From: Ron Wilson <rwilson@eet.cmp.com>
Date: Fri, 11 Apr 1997 10:13:39 -0700
Links: << >>  << T >>  << A >>
Joe Buck wrote:
> 
> peter@xilinx.com (Peter Alfke) writes:
> [ Good article on why PREP benchmarks are useless, followed by... ]
> >They definitely destroyed any respect I might still have had for the
> >technical integrity of Marketing on Orchard Parkway.
> 
> Let he who is without a marketing department cast the first stone.
> 
> Seriously, let's stick to facts around here and hold off on shots at
> competitors; it just makes you look like a shill.  Explaining why the PREP
> benchmarks are of no value was a service.  Leave it at that.
> 
> --
> -- Joe Buck     http://www.synopsys.com/pubs/research/people/jbuck.html
> 
> Help stamp out Internet spam: see http://www.vix.com/spam/

I'm afraid the vested interest here runs deeper than you might imagine.
IMHO, what Peter was reciting was not "why PREP didn't work" but
Xininx's constructed excuse for trying to undermine PREP. In fact, the
PREP benchmarks--if you actually used them as intended, rather than
swallowing the marketeers' interpretations--did a very credible job of
predicting the performance and capacity of a particular PLD on a
particular kind of circuit. That is the main reason that some vendors
opposed them so vehemently, even after helping to design them.
There are no benchmarks that will deliver up a scalar measure of virtue
for a PLD, any more than there are for a CPU. But I think the major
players in the industry have a lot to answer for in destroying a very
usable tool set, not because it had limitations, but because it sort of
worked. The same sort of resistance, by the way, is standing between
users and a good tool for evaluating PLD synthesis. That's another area
where some people do not want to hear the answers.
ron wilson
Article: 6095
Subject: Cisco, getting tired of SPAM
From: david holmes <highgate@best.com>
Date: 11 Apr 1997 17:31:00 GMT
Links: << >>  << T >>  << A >>
The title says it all.
Article: 6096
Subject: Re: Sole source
From: Tom Burgess <tburgess@drao.nrc.ca>
Date: Fri, 11 Apr 1997 11:26:37 -0700
Links: << >>  << T >>  << A >>
jim granville wrote:
> 
<excerpt:>

> As you are injecting a substrate current, I would suggest as low a level
> as possible
> - very funny things can happen with lateral die currents :-)
> 
> Then use the Silicon Vf temco of 2,2 mV / degrees C, and you will get
> die edge temperatures.
> 
> - jim

Good points. Since I don't know the detailed structure of the input
protection circuitry, I am assuming that there may be other temperature
dependent things going on - like series resistance, leakage, etc. so
that device calibration will be required for accurate readings.

Another concern is of stray RF getting rectified by the diode and
messing
up the measurement. Some filtering will probably be needed. The only
thing left to do is try it and see.

As for the temperature at which spit boils, I have not yet seen anyone
post experimental results. There could be all sorts of things in spit
that would affect the boiling temp. Hmm. I've got a temperature
controlled soldering station handy - maybe I'll try it right now
(and hope that I don't have to explain what I'm doing to the boss).

	regards, tom
Article: 6097
Subject: H.O.T. Works Class Announcement
From: VCC <info@vcc.com>
Date: Fri, 11 Apr 1997 19:15:51 GMT
Links: << >>  << T >>  << A >>

Virtual Computer Corp. announces two additional H.O.T. Works Classes.

            April 29-30  Woodland Hills (LA), California
            Sept. 4-5  Imperial College, London, England

These two-day class will cover the new Xilinx RPU -XC6200,
it's use within the H.O.T. Works Development System, and
the various software tools which come with the system. The
class includes the H.O.T. Works PCI-XC6200 Development Board
and all the software needed to implement a design. See our
website for more details. Take the class, get the knowledge and
go home with the complete development system.

For more information & registration--http://www.vcc.com/vcct1.html
Article: 6098
Subject: Seeking PALASM/ABEL/CUPL/?
From: s@cotts.cluon.com
Date: 11 Apr 1997 14:01:23 -0700
Links: << >>  << T >>  << A >>

I'm working on a simple project, and I am using some GAL22V10s or
similar for all my combinatorial logic.  However, right now, I have to
send PALASM source to a friend with a PC who compiles it and emails me
back the JEDEC files.  

In days past, it was easy to get vendors to give you programming
software for many platforms, but now it seems that nobody is
supporting anything but Windows!  Help!

I can eat the following binary formats: (in order of preference)

Far Prefered:
	SPARC Binary under SunOS 4.1.x

Acceptable:
	VAX/VMS under VMS 5.2 or VMS 4.6


=============================================================================
		  Scott Statton - s@cotts.cluon.com
	  swap the at and the first dot for the real address
=============================================================================
Article: 6099
Subject: Re: fpga technologies and Iddq testing
From: "Rich K." <rich.katz@gsfc.nasa.gov>
Date: 11 Apr 1997 21:36:39 GMT
Links: << >>  << T >>  << A >>
hi,  

hopefully this will explain what we're after.  if you need more info,
please e-mail me directly since this is an fpga news group and we'd be
getting more into test stuff.

iddq testing measures device quiescient current over a variety of internal
states.  for a properly constructed 'cmos' device with no defects, the
current will be extremely small.  many defects, such as bridging faults, 
will manifest themselves as an increase in device supply current and be
sensitive to device state.  by applying appropriate vectors and measuring
the supply current, many defects can be easily detected.  it has been shown
that this type of testing complements typical vector testing in testing
devices and improves fault detection.  one of the key advantages of iddq
testing is that there is no need to propagate values to the output. 
another advantage is in locating the fault in ic's.  for instance, i have
used iddq analysis coupled with an emmission microscope to quickly track
down faults to a resolution of about 1 um (partially blown antifuse, btw).

the above is true for 'cmos' devices.  this is often violated for fpga's. 
for instance structures such as charge pumps consume power - since this
current drain is independent of state, iddq testing may still be
successfully performed by looking for delta currents.  the same is true for
on-board oscillators if they cannot be disabled.  other problems w/ iddq
testing are when internal tri-state data busses are used with pullup
resistors and the bus is active, for example - then the device supply
current will be state dependent.

now, for sram-based devices, w/ out pumping, as you mention below, the
output of the pass transistor will be lower than Vcc.  so, my question is -
what is this voltage relative to Vcc and what is its affect (or is it
effect)?  if it's approximately 1 threshold drop below vcc, the p-channel
fet in the following input stage may be ON just a little bit and some
current may flow from Vcc -> through p-channel -> through n-channel (which
is on hard) -> to GND.  And with perhaps tens of thousands of the gates on
a chip, even a small current per input stage can make for appreciable
state-dependent device currents.

what i am interested in is the current per input stage to see if iddq
testing makes sense for these types of devices.  i have used this type of
testing for devices from several manufacturers (i.e., Actel, Quicklogic,
Chip Express).

thanks for any info,

rk

------------------------------------------------------------------

Peter Alfke <peter@xilinx.com> wrote in article
<peter-0904971830460001@appsmac-1.xilinx.com>...
> In article <01bc4441$0a89d760$6e0db780@Rich>, "Rich K."
> <rich.katz@gsfc.nasa.gov> wrote:
> 
> > Hi,
> > 
> > Iddq testing has been shown to be a good technique for detecting faults
in
> > many types of circuits, including FPGAs.
> 
>  If I undersstand you right, you want to measure the difference in
> cross-current ( I would not call it leakage current ) between
> a) an inverter that is driven with a "full High signal, =Vcc, versus 
> b) an inverter where the input signal goes through a pass transistor. 
> 
> Without gate pumping, the output of the pass transistor is unavoidably
> lower than Vcc, but I think the difference in current through the
inverter
> or gate will be too tiny to be measurable outside the physics lab. And
> with tens of thousands of gates on the same chip, what are you really
> measuring ?
> Just curious.
> 
> Peter Alfke, Xilinx Applications
> 


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