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Messages from 3150

Article: 3150
Subject: Re: One Week to Boston
From: sbaker@best.com
Date: 15 Apr 1996 03:33:56 GMT
Links: << >>  << T >>  << A >>
>   sbaker@best.com writes:

I apologize for not identifying myself as program chairman for the PLDCon'96 in the referenced message.

Stan Baker
>  
>  
>
>  
>  
>  
>  
>>>>





Article: 3151
Subject: Re: FPGA->ASIC conversion
From: ais@pact.srf.ac.uk (Anthony Stansfield)
Date: Mon, 15 Apr 1996 09:13:27 GMT
Links: << >>  << T >>  << A >>
Bob Elkind (eteam@aracnet.com) wrote:
: Brad Kelley wrote:
: >
: > I am currently doing a design in an Actel FPGA (Act1 or Act2) that I would
: > like to convert to an ASIC to reduce cost, current consumption, package size,
: > all the good reasons.  It's been a while since we last surveyed vendors, so
: > we'll be out doing a current one.  Anyone done a conversion lately?  Problems,
: > suggestions, lessons learned, vendor problems/successes, any tips would be
: > appreciated.
: >
: > Current project is low-volume (fixed order for 500 units, 1 FPGA/ASIC per), so
: > zero NRE or low NRE is required.  Have some one-year old info that at least
: > one vendor would convert for zero NRE with 500-piece order, so I think this
: > might be possible even with small volume.

: If you stand back, you may conclude that you will be paying for the NRE
: costs; either through up-front charges, or through higher per-unit production
: cost, or a combination of the two.

: Masks cost money, and the ASIC vendor certainly hasn't forgotten that.

: The real (rather than accounting magic) savings are probably found in
: the following areas:

: 1.  Find a vendor who has a genuinely lower cost of doing business than
: the others.  Sometimes this implies finding a vendor with its own captive
: fab facility, their own mask shop, etc.
(snip)

: 2. Find a vendor that requires as little time/effort on your part as possible.
: This saves you NRE costs that you would otherwise bear in terms of development 
: time and effort.


There is a third way that a low-volume asic route can save money - by putting
two or more designs on the same mask set and sharing the cost between the
customers. This is the method used by some of the university prototyping
services for instance. It's not as simple as "shared between 2 customers
= half the cost", but it is possible to reduce the overall cost. You have
to juggle factors like:

1) The fab probably has a minimum and maximum mask size that it can use.
   So, if one customers requirements don't reach the minimum size there is
   a benefit from combining with another customer.
2) Mask cost is area dependent - the bigger the mask the more it costs. If
   you put two designs on the same mask set then the masks will be bigger
   and therefore more expensive.
2a) There is a constant element in the mask size - test transistors and
   alignment structures that have to be present on all designs. If 2
   designs are put on the same masks then they can share these common
   elements, so that the size of the composite mask is less that the sum
   of the sizes of the separate ones.
3) The fab cycle time is probably optimised for processing a minimum
   number of wafers to a particular design at a time. Suppose this is
   20 wafers. If a customer comes along and wants 500 units of a design
   that you estimate will yield 50 die per wafer then there's a problem
   - 50 * 20 = 1000. If there are two such customers though then they can
   share the same production run, each getting 25 die per wafer, but still
   using the fab at its most efficient loading.

Anthony Stansfield
ais@pact.srf.ac.uk


Article: 3152
Subject: Actel ACT1 Slow Rise Time
From: clifford@bb.iu.net (Greg Clifford)
Date: 15 Apr 1996 14:07:47 GMT
Links: << >>  << T >>  << A >>
During a recent test of one of our customers systems, we had a failure at
upper temperatures.  After some debug with the Probe, the part seems to have
slow rise times, producing delays on the order of 4-5x what a good part
exhibits.  Has anyone else experienced any symptons like these?  I have 
verified that the same design works properly on a different card and have
verified Vcc and ground continuity to the part.  Device is an ACT1020 2.0u
intended for a space application.


Article: 3153
Subject: MAX+plusII LPMs, Synthesis Options & AHDL Design Style
From: klindwor@tech17.informatik.uni-hamburg.de (Andre Klindworth)
Date: 15 Apr 1996 14:55:53 GMT
Links: << >>  << T >>  << A >>

Hello, world!

This posting seeks feedback on the library of parametrized modules (LPM),
AHDL design style and logic synthesis options within MAX+plusII version 6.01.
It addresses an audience with some deeper insight in AHDL / MAX+plusII.

Within a larger design project, I had to design a 16-bit binary up-/down
counter with synchronous and asynchronous reset for an Altera MAX-7000 CPLD.
Looking at the internal structure of the MAX7000 CPLDs, it was easy to do
an optimal hand mapping of the desired function. The new value to be stored 
for a single counter bit in a LCs flipflop can completely be determined with
the LCs logic resources according to:

  c[i] = c[i] XOR (    sync_reset & c[i]
                    # !sync_reset &  incr & c[i-1] & c[i-2] & ... & c[0]
                    # !sync_reset & !incr & decr & !c[i-1] & ... & !c[0] );

or when using an explicit enable and a signal selecting the count direction:

  c[i] = c[i] XOR (    sync_reset & c[i]
                    # !sync_reset & enable &  dir_up &  c[i-1] & ... &  c[0]
                    # !sync_reset & enable & !dir_up & !c[i-1] & ... & !c[0] );


The question arouse: "How do I tell MAX+plusII to generate these logic functions?"

Since we just got our hands on MAX+plusII version 6.01, I decided to give
a try to the new LPM-modules and instantiated an 8-bit LPM_COUNTER with the
following source code:

  FUNCTION LPM_COUNTER (data[LPM_WIDTH-1..0], clock, clk_en, cnt_en, 
                        updown, sclr, sset, sconst, sload, aclr, aset, aconst, aload)
                  WITH (LPM_WIDTH, LPM_REPRESENTATION, LPM_MODULUS, LPM_AVALUE, LPM_SVALUE)
               RETURNS (q[LPM_WIDTH-1..0]);

  SUBDESIGN cnt8_lpm (
    /reset, clk, sync_reset, enable, incr: INPUT;
    value[7..0]: OUTPUT; 
  )
  VARIABLE counter: LPM_COUNTER WITH (LPM_WIDTH = 8);
  BEGIN
    counter.(clock, cnt_en, updown, sclr, aclr) = (clk, enable, dir_up, sync_reset, /reset);
    value[] = counter.q[];
  END;
  
The results were disappointing: 17 LCs in a EPM7032 !
So I tried some different synthesis styles: FAST, NORMAL, WYSIWYG.
The results changed, but were still far from the optimum value: 8 LCs.
What are the LPMs good for, when such a simple design as a counter
is synthesized with such an overhead?

"Ok, it's not that simple with the LPMs. Then let's turn back to good old AHDL high
level constructs."
Next, I tried the following straightforward source code:

  SUBDESIGN cnt8 (
    /reset, clk, sync_reset, incr, decr: INPUT;
    value[7..0]: OUTPUT;
  )
  VARIABLE c[7..0]: DFF;
   BEGIN
    c[].(clrn, clk) = (/reset, clk);
    IF sync_reset THEN c[] = 0;
    ELSIF incr    THEN c[] = c[] +1;
    ELSIF decr    THEN c[] = c[] -1;
    ELSE               c[] = c[];
    END IF;
    value[] = c[];
  END;

The results, as reported in the .rpt file, where quite good: 8 LCs as expected,
but - what the heck? - 4 sharable expanders? What are those used for. So I took
a closer look to the report file and found the following equation for bit 5:

   value5  = TFFE( _EQ006, GLOBAL( clk), GLOBAL( /reset),  VCC,  VCC);
    _EQ006 =  decr & !incr & !sync_reset & !value0 & !value1 & !value2 & 
               !value3 & !value4 & !value5
           #  incr & !sync_reset &  value0 &  value1 &  value2 &  value3 & 
                value4 & !value5
           #  decr & !incr & !value0 & !value1 & !value2 & !value3 & !value4 & 
                value5
           #  incr &  value0 &  value1 &  value2 &  value3 &  value4 &  value5
           #  sync_reset &  value5;

The last term I had expected. But what has happened to other terms?
The second, forth and fifth term can obviously combined giving

           # !sync_reset & incr & value0 & ... & value4

and the first, third and fifth together yield

           # !sync_reset & !incr & decr & !value0 & ... !value4 .

For the higher order bits (bits 6 and 7), DFFEs and sharable expanders
(for value0 & ... & value5  and  !value0 & ... & !value5) were used.
Then I guessed: "Ok, maybe I have to use some other synthesis options to make
the compiler to produce the optimum result."
So I tried FAST, NORMAL, WYSIWYG, switching of this and that advanced option,
turning XOR synthesis on and off, but I didn't arrive at the optimal design.
I finally typed in the logic equation for each bit and compiled with WYSIWYG -
and got the optimum design at last. This hand-made counter is reported to run 
at 62 MHz and uses 8 LCs (16 LCs for the 16-bit version).

Finally I tried the old-style macrofunction 8COUNT and this also result
in an 8 LCs mapping with no expanders.


That's the end of this (lengthy) story (thanks for following to this point).

My points are:

o  Has anybody allready made some experiences with the new LPMs? Is my
   experience typical or am I doing anything wrong with using the module?

o  Can someone explain what is happening to the AHDL description? What synthesis
   options (if any) are responsible for the inefficiencies in the mapping?
   Why does the compiler fail to reduce the logic in _EQ006 above?

o  What "rule" makes MAX+plusII to change from TFFEs to DFFEs for the two
   most significant counter bits?

Any ideas, comments and design style suggestions appreciated.

Andre'.
-- 
---------------------------------------------------------------------------
Andre' Klindworth                       Universitaet Hamburg, FB Informatik
klindwor@informatik.uni-hamburg.de      Vogt-Koelln-Str.30, D-22527 Hamburg
http://tech-www.informatik.uni-hamburg.de/Personal/klindwor/Klindworth.html


Article: 3154
Subject: Re: VHDL conversion function from int to time ...?
From: wolfgsng.ecker@zfe.siemens.de (Wolfgang Ecker)
Date: 15 Apr 1996 15:09:10 GMT
Links: << >>  << T >>  << A >>
Hi Vijay,

the VHDL predefined Attributes 'VAL and 'POS should work:

variable t : time;
variable i : integer;


t := TIME'VAL(i);
i := TIME'POS(t);



Wolfgang





Article: 3155
Subject: Re: VHDL conversion function from int to time ...?
From: andrew@warp6.bri.hp.com (Andrew Hana)
Date: Mon, 15 Apr 1996 15:57:47 GMT
Links: << >>  << T >>  << A >>
Vijay A Nebhrajani (vijayn@cdac.ernet.in) wrote:
: Hi, everybody!

: Anyone know of a function on Synopsys to convert time to integer and vice versa?
: How could such a function be written, if it were not available readymade? need help
: VERY urgently.

: Thanks in advance. Email direct to vijayn@cdac.ernet.in

: -- vijay.


How about:


    signal_of_type_time    <= signal_of_type_integer * 1 ns;
  
    signal_of_type_integer <= signal_of_type_time    / 1 ns;


Note that the space between `1' and `ns' is important!!

Andrew


Article: 3156
Subject: test, please ignore
From: rmcole@lfs.loral.com (Robb Cole)
Date: 15 Apr 1996 19:29:03 GMT
Links: << >>  << T >>  << A >>
My news reader program does not include the posting header info. 
I am trying to fix it.  Please let me know if there is a better place to 
do this..

Robb Cole

e-mail rmcole@lfs.loral.com



Article: 3157
Subject: Testing again
From: rmcole@lfs.loral.com (Robb Cole)
Date: 15 Apr 1996 19:30:42 GMT
Links: << >>  << T >>  << A >>
I promise.. this is the last one.

Robb Cole

MS 0302
Loral Federal Systems-Owego
1801 State Route 17C
Owego, NY 13827-3994

Voice 607-751-3708
Fax   607-751-6732
e-mail rmcole@lfs.loral.com



Article: 3158
Subject: What's the lowest-priced FPGA?
From: gf0570 <fang@signus.utah.edu>
Date: 15 Apr 1996 23:52:59 GMT
Links: << >>  << T >>  << A >>
Hi,
    What is the lowest-priced FPGA? I've used XC4003 for some project 
before but they are very expensive. Now I'm working on a new project 
which is very cost-sensitive. We need to select a programable logic 
device with very low cost and relatively high gate and I/O counts.

    What are costs for XC2000 family parts?

    Thanks in advance for any information.

-GF-



Article: 3159
Subject: Re: ACTEL design with Synopsys
From: bobarker@ix.netcom.com(Robert Barker )
Date: 16 Apr 1996 03:15:54 GMT
Links: << >>  << T >>  << A >>
Yes, use Exemplar Logic Galileo. They syntheisze the complex I/Os
contained in the ACT3 family. They even do design rule checks to be
sure the designer doesn't overuse the clock resources. MTC and Logic
Innovations are the Exemplar representatives in Muenchen.

Also contact Exemplar at info@exemplar.com


In <316E36A7.2781E494@scn.de> b1052 <b1052@scn.de> writes: 
>
>Hi,
>when synthesizing a VHDL design with Synopsys Design Compiler into an
>act3 lib and transfering it to the Designer software from Actel I get
>errors because non-clock pins use a clock net. The reason is that
Design
>Compiler puts "complex" cells on clock nets; the also used inverters
are
>not flagged with errors.
>Has somebody an idea how I can avoid this?
>
>TIA
>  Guido
>-- 
>Guido Kinast           Siemens AG,  AUT E721             Fuerth,
Germany
>b1052@scn.de          http://www.scn.de/~b1052          +49 911 750
2720



Article: 3160
Subject: Re: What's the lowest-priced FPGA?
From: Andy Gulliver <andy.gulliver@crossprod.co.uk>
Date: Tue, 16 Apr 1996 15:17:01 +0100
Links: << >>  << T >>  << A >>
gf0570 wrote:
> 
> Hi,
>     What is the lowest-priced FPGA? I've used XC4003 for some project
> before but they are very expensive. Now I'm working on a new project
> which is very cost-sensitive. We need to select a programable logic
> device with very low cost and relatively high gate and I/O counts.
> 
>     What are costs for XC2000 family parts?
> 
>     Thanks in advance for any information.
> 
> -GF-

The XC2000 series are a bit basic - especially if you're using 4000 
series now and need similar density devices.  A better bet would be the 
XC5000 series.  Your distributor should be able to get data - or check 
out http://www.xilinx.com

-- 
Regards

AndyG
------------------------------------------------------------------------
**  Terry Pratchett's 'Wyrd Sisters' on stage in Leeds - April 25-27  **
check out http://ourworld.compuserve.com/homepages/Whitkirk for details,
or e-mail 73064.1273@compuserve.com

------------------------------------------------------------------------


Article: 3161
Subject: Re: Actel ACT1 Slow Rise Time
From: ees1ht@ee.surrey.ac.uk (Hans)
Date: 17 Apr 1996 09:33:08 GMT
Links: << >>  << T >>  << A >>
In article <4ktl7j$akc@cc.iu.net>, clifford@bb.iu.net says...
>
>During a recent test of one of our customers systems, we had a failure at
>upper temperatures.  After some debug with the Probe, the part seems to 
have
>slow rise times, producing delays on the order of 4-5x what a good part
>exhibits.  Has anyone else experienced any symptons like these?  I have 
>verified that the same design works properly on a different card and have
>verified Vcc and ground continuity to the part.  Device is an ACT1020 2.0u
>intended for a space application.

Interesting,
We used a number of ACT1020A on our previous satellite, they all worked 
fine. I assume you are aware that the 2.0 A version is being discontinued. 
If you have the money available you can get a (real?) Rad-Hard version from 
Loral. I belief they make the A1225 and A1280 using Silicon on Insulator. 
RAD-PACK is an another company who makes rad-hard Actel (and others) FPGA's. 
They take a standard commercial die and re-packing it using there patented 
RAD-PACK package. There prices are quite reasonable, you also don't have to 
order 10000 as a minimum :-)

Regards,
Hans  
Surrey Satellite Technology Ltd.




Article: 3162
Subject: Germany: FPGA/CPLD Developers Forum
From: Uwe Kremmin <uwe.kremmin@amd.com>
Date: Wed, 17 Apr 1996 15:42:10 +0100
Links: << >>  << T >>  << A >>
If you are interested in programmable logic hardware or software and are in Germany on May 15th,
check out the PLD Developers Forum in Munich. Hosted by an electronics magazine 
(Design&Elektronik)this will be one of the biggest (if not THE biggest) PLD event in Germany 
in 96. In contrast to last year presentations will not be by manufactures, but by independent 
presenters. Should take out the hype.
For more information: http://www.magnamedia.de/d&e/forum/logik.html

Uwe Kremmin
AMD


Article: 3163
Subject: Looking for FPGA Boards taking Xilinx 4000 series FPGA
From: "S.C.Lim" <elscl@lboro.ac.uk>
Date: Wed, 17 Apr 1996 15:30:35 GMT
Links: << >>  << T >>  << A >>
Hi,

Our research group is looking into purchasing circuits boards that will
take one to a few Xilinx 4020 FPGA chips. These Boards are to be used
for circuit verifications by downloading design using Xilinx's Xact
cable. If the board contains multiple chips, they should all be able to
be programmed using a single xact cable link.

If you have such kind of boards avaliable for sale or know anybody who
supplies them, please mail me at  S.C.Lim@lboro.uc.uk.

Regards
Ryan Lim Seow Chuan
============================================================
Seow-Chuan Lim (Ryan)                    1010010001010011101
Research Student                         1                 1
Loughborough University                  0 DIGITAL SYSTEMS 0  
Ashby Road, Loughborough. LE11 3TU. U.K. 1    LABORATORY   0
Tel: 0-1509-228104                       0                 1
email S.C.Lim@Lboro.ac.uk                1001001001011100111
============================================================


Article: 3164
Subject: Germany: FPGA/CPLD Developers Forum
From: Uwe Kremmin <uwe.kremmin@amd.com>
Date: Wed, 17 Apr 1996 16:48:11 +0100
Links: << >>  << T >>  << A >>
If you are interested in programmable logic hardware or software and are in Germany on May 15th,
check out the PLD Developers Forum in Munich. Hosted by an electronics magazine 
(Design&Elektronik)this will be one of the biggest (if not THE biggest) PLD event in Germany in 
96. In contrast to last year presentations will not be by manufactures, but by independent 
presenters. Should take out the hype.
For more information: http://www.magnamedia.de/d&e/forum/logik.html

Uwe Kremmin
AMD


Article: 3165
Subject: Power consumption of Xilinx device
From: "Rolf V. =?iso-8859-1?Q?=D8stergaard" <rolf@login.dknet.dk>?=
Date: Wed, 17 Apr 1996 16:09:03 -0100
Links: << >>  << T >>  << A >>
For a given design, what can be done to reduce the power consumption of
a Xilinx 3020 device? I think in terms of special routing, unused nets
etc.

Anyone got any ideas on how much I could expect to reduce the power
consumption using "after-design" techniques only? 10%, or?

- Rolf


Article: 3166
Subject: AMD-MACH-devices with PSPICE
From: Kaj Norman Nielsen <knn@inet.ats.dk>
Date: 17 Apr 1996 19:52:23 GMT
Links: << >>  << T >>  << A >>
I'm about to do my first expieriencies working with PSPICE (PLSYN) as the 
programming tool on a MACH445-device.
   1. Is this the right newsgroup for me (any othe sugestions)
   2. Is anyone here that will know what to watch out for.

I have limmited expierience with PLD's.

       All the best From   Kaj Norman Nielsen



Article: 3167
Subject: Re: What's the lowest-priced FPGA?
From: peter@xilinx.com (Peter Alfke)
Date: 17 Apr 1996 21:14:23 GMT
Links: << >>  << T >>  << A >>
In article <4kungr$k6n@news.cc.utah.edu>, gf0570 <fang@signus.utah.edu> wrote:

> Hi,
>     What is the lowest-priced FPGA? I've used XC4003 for some project 
> before

You were not specific regarding pin-count and speed, and I will not quote
prices, that's done by our local salesforce,.Nevertheless, here are the
Xilinx devices that you might want to look at, in descending price order,
starting from the XC40003. 
Remember, package, speed, and quantity affect the price significantly.

XC4003, XC5204, XC3042A, XC3030A, XC5202, XC3020A, XC2018, XC2064.

The XC2000 series is a bit old, the XC3000A and especially the XC5200
families offer better value, IMHO.

Peter Alfke, Xilinx Applications


Article: 3168
Subject: Re: ACTEL design with Synopsys
From: mcgett@xilinx.com (Ed McGettigan)
Date: 17 Apr 1996 21:50:05 GMT
Links: << >>  << T >>  << A >>
In article <316E36A7.2781E494@scn.de>, b1052  <b1052@scn.de> wrote:
>Hi,
>when synthesizing a VHDL design with Synopsys Design Compiler into an
>act3 lib and transfering it to the Designer software from Actel I get
>errors because non-clock pins use a clock net. The reason is that Design
>Compiler puts "complex" cells on clock nets; the also used inverters are
>not flagged with errors.
>Has somebody an idea how I can avoid this?
>
>TIA
>  Guido
 
The easiest way to avoid this problem is to not use Actel, and to use
the Xilinx XC8100 instead.  :-) :-) :-) The XC8100 architecture allows 
the high drive nets to be used for any pin connection (clock, reset, 
combinatorial, etc...) unlike the Actel families that require that these 
nets be connected to clock and reset inputs only.
 
Here are my suggestions to get around this problem in the Actel families:
 
  1) If the clock net must be combined with combinatorial logic
 
     Split the clock net into two signals, 1 that drives the clock pins
     and another that goes to the combinatorial logic. Use an internal
     clock buffer as the source on the clock drive.  You will need to
     instantiate this in your VHDL 
 
  2) If the clock net only goes to clocks and resets but you still get this problem 
 
     Check your compile script and remember to apply a dont_use attribute
     to the clock buffers after inserting pads  on your clock pins and
     before inserting on your regular IO. This will prevent Synopsys from
     adding the nifty high drive input buffers were they're not wanted.
 
     Example:
 
     set_port_is_pad {clk reset}
     set_pad_type -exact CLKBUF {clk reset}
     remove_attribute act3/CLKBUF dont_use
     insert_pads  
     set_port_is_pad .
     remove_attribute {clk reset} port_is_pad
     set_dont_use act3/CLKBUF
     set_dont_touch act3/CLKBUF
     insert_pads
 
     
Regards, 
 
Ed 

-- 
+----------------------------------------------------------------------+
|Edward McGettigan  | Xilinx Inc.  "The Programmable Logic Company" sm | 
|mcgett@xilinx.com  | XC8100 FPGA Applications Engineer (408)879-4772  |
+----------------------------------------------------------------------+


Article: 3169
Subject: high gate count FPGA for small volumn production?
From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN)
Date: Thu, 18 Apr 1996 09:22:55 +800
Links: << >>  << T >>  << A >>
Dear friends,

people always talk about "prototyping ASIC" with FPGA(s).  But at least
in my case, due to the uncertainty of market, ASIC solution is not
possible at the moment.  I have to find FPGA device whose gate count
is about 20000 (at real utilization) and whose price is relative
low to make the final product competitive.

Because of the internal architecture of my design, I could not
partition it into more than two FPGAs efficiently.  Of course,
I believe that the higher integration, the lower cost.  It is lucky
that I design it in VHDL so that I have the freedom in choosing
FPGAs.

Don't tell me Altera's Flex10K-50.  Its high price and its sole huge
PGA package (more than 390 pins) stops me.  I have tried Actel's
DX32140 but its gate count is not enough either.  They told me
that Actel's backend tool does not support DX32200 yet.  I have
also tried the Xilinx's XC5200.  But the result remained the same.
I do not care for the operating speed of the final chip, as long
as the chip can hold my design.

It is really tough.  After the search, I got a strong feeling that
the gap (performance and size) between FPGA and ASIC is becoming
larger and larger.  FPGAs seem can only find market position for
"Glue logic integration" and "peripheral function for supporting ASIC".

What else FPGA vendors can I tried?

Regards,

Felix K.C. CHEN
-- 
---------------------------------
Felix, Kuan-chih CHEN ( a )
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw

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Article: 3170
Subject: Re: high gate count FPGA for small volumn production?
From: Bob Elkind <eteam@aracnet.com>
Date: Thu, 18 Apr 1996 06:35:00 +0100
Links: << >>  << T >>  << A >>
Felix K.C. CHEN wrote:
 
> I have to find FPGA device whose gate count
> is about 20000 (at real utilization) and whose price is relative
> low to make the final product competitive.
> 
> Don't tell me Altera's Flex10K-50.  Its high price and its sole huge
> PGA package (more than 390 pins) stops me.  I have tried Actel's
> DX32140 but its gate count is not enough either.  They told me
> that Actel's backend tool does not support DX32200 yet.  I have
> also tried the Xilinx's XC5200.  But the result remained the same.
> I do not care for the operating speed of the final chip, as long
> as the chip can hold my design.
>
> What else FPGA vendors can I tried?

Felix,

Xilinx  4028EX (28K gates, enhanced routing resources, promises
                100% gate utilisation)

ATT/Lucent 2C26, 2C40  (26K, 40K gates respectively.)

The Xilinx device is brand-spanking new, and I'm sure Xilinx will
push the gate count higher on successive devices.

The 2Cxx parts are in production, and they are generally regarded
as a good choice (reliable toolset, utilisation factor, etc.).
Their end-user cost is quite reasonable, also.
I don't know much about VHDL support for these puppies, though.

I've heard 2nd hand that the Quicklogic family has excellent VHDL
support, but I think you'll bump against gate count limits in that
family.  Can someone clarify this notion?

Good Luck,

Bob Elkind

**************************************************************************
Bob Elkind                email:eteam@aracnet.com             CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************


Article: 3171
Subject: Re: Power consumption of Xilinx device
From: Bob Elkind <eteam@aracnet.com>
Date: Thu, 18 Apr 1996 06:42:34 +0100
Links: << >>  << T >>  << A >>
Rolf V. wrote:

> For a given design, what can be done to reduce the power consumption of
> a Xilinx 3020 device? I think in terms of special routing, unused nets
> etc.
> 
> Anyone got any ideas on how much I could expect to reduce the power
> consumption using "after-design" techniques only? 10%, or?-- 

Suggestions:

1.  Reduce the clock rate
2.  Use the 3100a family (5V), they are smaller geometry and lower power.
3.  Use the 3100L family (3.3V).
4.  If die temperature is the root concern, rather than current
    consumption, then try a different package with better thermal
    characteristics (e.g. the metal quad flatpak).  Or try a heat sink
    on a non-plastic package.

There are some design hacking techniques that will theoretically 
reduce power consumption, but they are very time-intensive, and you
won't get dramatic results (short of complete design re-structuring).

Bob Elkind

**************************************************************************
Bob Elkind                email:eteam@aracnet.com             CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************


Article: 3172
Subject: Problems with XBLOX
From: hbratko@sbox.tu-graz.ac.at (Harald Bratko)
Date: 18 Apr 1996 09:50:01 GMT
Links: << >>  << T >>  << A >>

-- 
Harald Bratko alias hbratko@sbox.tu-graz.ac.at


Article: 3173
Subject: Re: high gate count FPGA for small volumn production?
From: ees1ht@ee.surrey.ac.uk (Hans)
Date: 18 Apr 1996 12:36:03 GMT
Links: << >>  << T >>  << A >>
In article <4l45ct$7q6@news.cis.nctu.edu.tw>, flxchen@diig.dlink.com.tw 
says...
>
snip
>
>What else FPGA vendors can I tried?
>
>Regards,
>
>Felix K.C. CHEN

You might want to have a look at AT&T's 40000 gates ATT2C40. 

http://www.att.com/press/0295/950227.mea.html

Hans.



Article: 3174
Subject: PLD-Forum der Design & Elektronik
From: eiblmayra@aol.com (EiblmayrA)
Date: 18 Apr 1996 09:35:19 -0400
Links: << >>  << T >>  << A >>
If you are interested in programmable logic hardware or software and are
in Germany on May 15th,
check out the PLD Developers Forum in Munich. Hosted by an electronics
magazine (Design&Elektronik)this will be one of the biggest (if not THE
biggest) PLD event in Germany in 96. In contrast to last year
presentations
will not be by manufactures, but by independent presenters. Should take
out the hype.
For more information: http://www.magnamedia.de/d&e/forum/logik.html

Uwe Kremmin
AMD




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