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Messages from 3275

Article: 3275
Subject: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
From: psi@io.NoSubdomain.NoDomain (Peter Sinander)
Date: 8 May 1996 16:21:03 GMT
Links: << >>  << T >>  << A >>
In article <318faf7f.561663@news.dial.pipex.com>, peter@kksystems.com writes:
 
|> I am working on an ASIC, and I need a hardware implementation of the
|> standard CCITT CRC algorithm: x^16+x^12+x^5+1 as used in floppy disk
|> controllers.

And for CCSDS Packet Telecommand and Packet Telemetry for spcaecraft communication.
The code below has been used for one flight design, but as usual no guarantees
that it works.


Good luck, 

Peter Sinander                                  psi@ws.estec.esa.nl
Microelectronics and Technology section (WSM)   http://www.estec.esa.nl/wsmwww
European Space Agency                           Phone: +31-71-565 33 67
European Space Research & Technology Centre     Fax:   +31-71-565 42 95


-------------------------------------------------------------------------------
-- CRCGen(RTL)
--
-- File name : crcgensyn.vhdl
-- Purpose   : Generates CRC for serial outputs
--           : Polynom is x16 + x12 + x5 + 1
--           : To be synthesized by Synopsys VHDL compiler
-- Library   : SynVCM
-- Author(s) : Peter Sinander, ESTEC WSM
-- Copyright : European Space Agency (ESA) 1992. My be reproduced in
--             whole or part with full reference to the source. Any other
--             reproduction requires prior written permission of ESA.
-------------------------------------------------------------------------------
-- Version   Author  Date         Changes
--
-- 1.0       PSI      1 Jun 1992  First try
-------------------------------------------------------------------------------
 
-- USE Work.SynDef.ALL;   Probably not needed for this design unit
 
 
ENTITY CRCGen IS
   PORT (Clk:       IN  Bit;              -- System clock
         Reset_N:   IN  Bit;              -- Master async reset
         iSyncMark: IN  Bit;              -- Init CRC register when '1'
         OutputCRC: IN  Bit;              -- Output CRC when '1'
         DataOut:   IN  Bit;              -- Data to be CRCed
 
         CRCOut:    OUT Bit);             -- CRC output
END CRCGen;
 
-------------------------------------------------------------------------------
 
ARCHITECTURE RTL OF CRCGen IS
   SIGNAL GateA:  Bit;
   SIGNAL Shift4: Bit_Vector(0 TO 3);
   SIGNAL Shift5: Bit_Vector(0 TO 4);
   SIGNAL Shift7: Bit_Vector(0 TO 6);
BEGIN
 
   -- XORs last bit of CRC reg with data, is zero when CRC output
   GateA <= DataOut XOR Shift4(0) WHEN OutputCRC = '0' ELSE '0';
 
  -----------------------------------------------------------------------------
 
   -- 16 bit CRC shift register with XORs to implement the CRC polynomial,
   -- x16 + x12 + x5 + 1
   Shft5: PROCESS(Clk, Reset_N)                   -- First 5 bits of CRC reg
   BEGIN
      IF Reset_N = '0' THEN                       -- Master async reset
         Shift5 <= "00000";
      ELSIF Clk'Event AND Clk = '0' THEN
         IF iSyncMark = '1' THEN
            Shift5 <= CRCInit(11 TO 15);          -- Init CRC register
         ELSE
            Shift5 <= Shift5(1 TO 4) & GateA;     -- Shift in XORed bit
         END IF;
      END IF;
   END PROCESS Shft5;
 
 
   Shft7: PROCESS(Clk, Reset_N)                   -- Next 7 bits of CRC reg
   BEGIN
      IF Reset_N = '0' THEN                       -- Master async reset
         Shift7 <= "0000000";
 
      ELSIF Clk'Event AND Clk = '0' THEN
         IF iSyncMark = '1' THEN
            Shift7 <= CRCInit(4 TO 10);           -- Init CRC register
 t        ELSE
            -- Shift in XORed bit
            Shift7 <= Shift7(1 TO 6) & (Shift5(0) XOR GateA);
         END IF;
      END IF;
   END PROCESS Shft7;
 
 
   Shft4: PROCESS(Clk, Reset_N)                   -- Last 4 bits of CRC reg
   BEGIN
      IF Reset_N = '0' THEN                       -- Master async reset
         Shift4 <= "0000";
      ELSIF Clk'Event AND Clk = '0' THEN
         IF iSyncMark = '1' THEN
            Shift4 <= CRCInit(0 TO 3);            -- Init CRC register
         ELSE
            -- Shift in XORed bit
            Shift4 <= Shift4(1 TO 3) & (Shift7(0) XOR GateA);
         END IF;
      END IF;
   END PROCESS Shft4;
 
 
   -- Output last bit of CRC register
   CRCOut <= Shift4(0);
 
END RTL;
 




-- 

Peter Sinander                                  psi@wd.estec.esa.nl
Microelectronics and Technology section (WSM)   http://www.estec.esa.nl/wsmwww
European Space Agency                           Phone: +31-71-565 33 67
European Space Research & Technology Centre     Fax:   +31-71-565 42 95

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> N.B. New phone & fax number


Article: 3276
Subject: Re: Is XC7336 the least expensive CPLD?
From: peter@xilinx.com (Peter Alfke)
Date: 8 May 1996 17:07:43 GMT
Links: << >>  << T >>  << A >>
In article <4mon6i$bko@news.cc.utah.edu>, gf0570 <fang@signus.utah.edu> wrote:

> Hi,
>     Is XC7336 the cheapest CPLD ?

There is also an XC7318, obviously cheaper.

You won't get price quotes on the net. Contact a distributor, you can
usually find their phone numbers in the data book ( page 10-6 in the
Xilinx data book )

Peter Alfke, Xilinx Applications


Article: 3277
Subject: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
From: mbutts@netcom.com (Mike Butts)
Date: Wed, 8 May 1996 18:16:06 GMT
Links: << >>  << T >>  << A >>
(I didn't read your schematic, sorry.)
Yes, CRC can drive you crazy!  Did me recently, I admit.  Much
depends on whether you are receiving/sending the data least-significant-
bit first, or MSB first.  

If MSB first, you are in luck.  Go read Ross Williams' "A Painless
Guide to CRC Error Detection Algorithms", which you can get off the net:
ftp://ftp.adelaide.edu.au/pub/rocksoft/crc_v3.txt

If LSB first, you still use a shift-register and XORs, but it's
weirder.  The only reference I know is an old DEC publication,
"Technical Aspects of Data Communication", by John McNamara, pages
148-158.

Failing these, go through any data communications text you can find.
Good luck.

   --Mike

-- 
Mike Butts, Portland, Oregon   mbutts@netcom.com



Article: 3278
Subject: Re: Implementation of a ROM
From: ft63@dial.pipex.com (Peter)
Date: Wed, 08 May 1996 19:28:25 GMT
Links: << >>  << T >>  << A >>

I would try to approach this differently: how is the ROM content
derived? From some boolean equation set?

In the past, I have used the facility in CUPL (a PLD compiler which
can accept truth table input) to convert a truth table (i.e. a ROM)
into a set of equations. Unless the truth table is pretty well random,
implementing the equations (which the compiler will minimise anyway)
should be more efficient.

But I have never done it with anything as big as 256x8.

Peter.


Article: 3279
Subject: Re: Implementation of a ROM
From: peter@xilinx.com (Peter Alfke)
Date: 8 May 1996 20:19:56 GMT
Links: << >>  << T >>  << A >>
In article <Dr2pus.F2I@news.uwindsor.ca>, safiri@engn.uwindsor.ca wrote:

> I am trying to implement a design consist of a 256*8 size ROM on a
Xilinx FPGA.

Any 256 x 8 ROM with arbitrary content fits into 64 CLBs ( each one as a
32 x 1 ROM ) plus eight 8-to-1 multiplexers which can be implemented by
3-state buffers driving horizontal Longlines. So all you need are eight
1-of-8 decoders, which fit into four CLBs.
So the answer is: 68 CLBs plus 64 TBUFs,  i.e. 35% of an XC4005/XC4005E,
or 48% of an XC3042 or XC3142, depending on your speed requirements.
The content of the ROM is irrelevant.
If the ROM content is highly biased, there may be more efficient
implementations, but I don't think it's worth to explore that.

Peter Alfke, Xilinx Applications


Article: 3280
Subject: Re: Is XC7336 the least expensive CPLD?
From: peter@xilinx.com (Peter Alfke)
Date: 8 May 1996 22:15:33 GMT
Links: << >>  << T >>  << A >>
In article <4mon6i$bko@news.cc.utah.edu>, gf0570 <fang@signus.utah.edu> wrote:

> Hi,
>     Is XC7336 the cheapest CPLD one can find in the CPLD marcket?

XC7318 is half the size, and therefore cheaper. For prices, contact the
appropriate distributor. You find their names and phone numbers in any
data book, page 10-6 in the Xilinx data book.

Peter Alfke, Xilinx Applications


Article: 3281
Subject: Re: FPGA leaders - Who are they? Xilinx, Altera, Actel?
From: Michael Holley <holley@data-io.com>
Date: Wed, 8 May 1996 22:28:22 GMT
Links: << >>  << T >>  << A >>
f.j.koons wrote:
> 
> My two cents worth:
> 
> "FPGA - The field-programmable gate array (FPGA)
>  was developed as a programmable alternative to
>  the masked gate array, another popular semicustom
>  ASIC device. An FPGA uses a channeled programmable
>  interconnect matrix to join blocks of configurable
>  logic. Unlike the CPLD, an FPGA's electrical
>  characteristics are not fixed, so qualities
>  such as line length and number of fuses are not
>  known until routing. Although this makes for some
>  unpredictability of timing, the trade-off is the
>  FPGA's increased logic complexity and flexibility."
> 
Many designers could care less about the definition of FPGA
or CPLD. They just want a few thousand gates of logic in a
84 pin plcc package. The Altera 7000 family and ATT/Xilinx
3000 family are about the same for most applications. 

A few years ago when a new patent lawsuit was announced
every week I came up with this FPGA/CLPD definition. If the
semiconductor vendor is being sued by Xilinx the device is
an FPGA, if they are being sued by AMD it is a CPLD.

Michael Holley


Article: 3282
Subject: Re: FPGA for Space Application
From: dwayne.j.padgett@jpl.nasa.gov (Dwayne J. Padgett)
Date: Wed, 08 May 1996 17:00:30 -0700
Links: << >>  << T >>  << A >>
In article <DqoA70.35D@news.dlr.de>, venus@sunnyboy.ws.ba.dlr.de wrote:

> Hallo,
> 
> I am looking for FPGA (5000 .. 20000 gates) for a apace application. 
> I know the Actel/Loral 1280.

The 1280 was rad tested by JPL.  Results should be posted in the RADATA archive.
http://www.jpl.nasa.gov and manuver thru menus.


Article: 3283
Subject: Re: What EPLD system to buy ?
From: jwest@pgh.nauticom.net (Jim West)
Date: Thu, 9 May 1996 02:14:07 GMT
Links: << >>  << T >>  << A >>
Steve Dewey <Steve@s-dewey.demon.co.uk> wrote:


>  
>  Hi
> 
> I posted this to sci.electronics, and was told that this group might be a 
> better place.
>  
> I work for a small electronics group. In the past we have produced some 
> large pieces of equipment with _lots_ of TTL logic. Much of this can now
> be incorporated into a single FPGA.
Yup. Think of the money you can save....

> We are interested in aquiring a basic programable logic capability, 
> and I have been charged with investigating the market and coming up 
> with some suggestions for about 2000 U.K. Pounds (about U.S.$3000) total cost.
> Our development system will be P.C. based
You may want to plan on spending a bit more now, especially if you
want to migrate to the larger parts later (without buying more later).
Maybe a lot more. It sounds like you may be in the 5-10K range.
> 
> However I have only a theoretical knowledge of the steps required to turn
> a paper conceptual design based on 74 series TTL parts to a working single 
> device, eg GAL22V10, let alone the issues that need to be addressed when 
> attempting to implement larger designs.  
>  
> Ideally we would be able to start with simple parts, such as generic 16V8,
> and as we gain confidence move up to the much larger parts, eg Xylinx, without
> having to learn a new set of design tools.
>  
> So my questions are :
>  
> 1.      What seperate bits do I need ? I have identified the following:
>                 Schematic Capture Editor
>                 Logic Compiler
>                 Functional Simulator
>                 Device Programmer
>         Is there anything else ?
You got the biggies.If you are going to be using larger parts, make
sure you go for full simulation, not just functional. Note that the
programmer can be vendor supplied or third party. Data I/O is the
biggie here, but you could easly blow your whole budget on just the
programmer. SRAM based FPGA's will allow you to get by with a cheaper
EPROM programmer.
>  
> 2.      Who supplies all this ? Is it possible to use third party software
>         and equipment, to avoid being locked in to a single manufacturer ?
Major soul searching time here.  We just went through what you are
doing. Decided on Altera. Relativly big company (stable) and they
cover just about the whole spectrum of devices (simple pld to large
FPGA). The software is very good too. So far the support is good.
>  
> 3.      What experience do people have of the major silicon vendors,
>         eg Altera, Lattice, Xylinx, and others ?
>  
> 4.      We expect to be required to be able to service equipment using this 
>         technology in 10 years time. Which suppliers are most likely to be in 
>         a position to supply spares over this timescale ?
You might have a chance with the simple parts that are currenly
multiple sources. But 10 years sounds a bit hopefull for this
technology, especially the larger parts. The technology is very vendor
specific.  Your best bet migh be to go with one of the bigger vendors
and hope.
>  
> I would really like to hear from users of this technology, because otherwise 
> I have to rely totally on what the salespeople have to say. In particular 
> I would like to hear from users of the Orcad PLD tool, or the MINC system.
Decide if you really need a general purpose schematic capture tool
integrated with the logic design tool. For simpler stuff, it might not
be too important.  Also, the 3rd party companies seem to be geared to
people doing larger, more complex design using a hardware definition
languare (eg - VHDL). This is harder to learn, but offers more power
for larger designs and a degree of vendor independence. The third
party tools tend to cost more. Sometimes lots more. This might be
overkill if you are going to start off with smaller parts and be using
schematic capture for design entry.
>  
> Please post here or email me at Steve@s-dewey.demon.co.uk
>          
>  -- 
>  Steve Dewey
>  Too boring to have a witty or interesting sig file.
>  
> 




Article: 3284
Subject: Xilinx Mapping & Placing in HDL
From: kurt@emphasys.de (Volker Kurt Kamp)
Date: Thu, 09 May 1996 11:05:09 +0200
Links: << >>  << T >>  << A >>
Hi,

I'am designing Xilinx FPGAs with mixed mode entry: Schematic entry and
ABEL, using the Synario-System. In the schematic entry system, it is
possible to use CLBMAP and TIMESPECS. But with ABEL it is not.

Is there a workaround ?
What HDL compilers can compile these constrains into the xnf-file ?

Thanks in advance,
Kurt.

 -------------------------------------------------------------------
 ****   *  =========== = = = =       Volker Kurt Kamp
 **  *           =                   (kurt@bintec.de) 
 ****   *  ***   =   ==    ===       BinTec Commmunications GmbH
 **  *  *  *  *  =  ====  =          Alt-Moabit 94  D-10559 Berlin
 **  *  *  *  *  =  =     =          Voice: (+49)30 / 399 88-3
 ****   *  *  *  =   ==    ===       FAX:   (+49)30 / 392 28 36 
 -------------------------------------------------------------------
  C O M M U N I C A T I O N S              
 -------------------------------------------------------------------


Article: 3285
Subject: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
From: pegu@dolphinics.no (Petter Gustad)
Date: 09 May 1996 12:24:30 +0200
Links: << >>  << T >>  << A >>
In article <318faf7f.561663@news.dial.pipex.com> peter@kksystems.com
writes:

>Hi All,
>
>I am working on an ASIC, and I need a hardware implementation of the
>standard CCITT CRC algorithm: x^16+x^12+x^5+1 as used in floppy disk
>controllers.
>
>There are lots of software versions of this, mostly table-driven, but
>none are in the form comprising a 16-bit shift reg, with some XOR
>gates around it, which I know are all that is necessary. I have access
>only to 1 bit of the data at any time, whereas all the s/ware
>implementations load in at least 1 byte at a time.

The serial definition of CCITT CRC-16 is:

c15 = c0 xor d
c14 = c15
c13 = c14
c12 = c13
c11 = c12
c10 = c11 xor c0 xor d
c9 = c10
c8 = c9
c7 = c8
c6 = c7
c5 = c6
c4 = c5
c3 = c4 xor c0 xor d
c2 = c3
c1 = c2
c0 = c1

Where d is your single bit input.

>Attached is a zipfile containing a postscript file of my present
>circuit. (I hope no-one objects to this "binary" post; it is only 6k.)
>This very nearly works, but only if the input data is all zeroes! So
>there must be something wrong with the way I am feeding in the input
>data. Note that my init of 0xe295 (instead of 0xffff) is deliberate.

I can't see the enclosed file (I'm using GNUS under emacs).

Best regards
Petter
-- 
________________________________________________________________________
Petter Gustad                             http://www.dolphinICS.no/~pegu



Article: 3286
Subject: Re: On FPGAs as PC coprocessors [rererepost]
From: wolf@aur.alcatel.com (William J. Wolf)
Date: 9 May 1996 12:41:23 GMT
Links: << >>  << T >>  << A >>
Interesting perspective Jan.  After reading this, I wonder 
whether a vendor should spend resources to provide generic 
mixed ASIC/FPGA capabilities instead of offering a specific 
FPGA coprocessor.  The PC world just moves too fast.  Plus, 
third parties could really extend the success of ASIC/FPGA 
coprocessors by tayloring them to various systems/busses.

If any vendor does pursue this idea, I would appreciate 
a free spin. :-)

Cheers.

---
- Bill Wolf, Raleigh NC
- My opinions, NOT my employer's




Article: 3287
Subject: FPGA'97 Call For Papers
From: hauck@eecs.nwu.edu (Scott A. Hauck)
Date: Thu, 09 May 1996 11:45:06 -0500
Links: << >>  << T >>  << A >>
FPGA'97: Call for Papers

1997 ACM/SIGDA Fifth International Symposium on 
Field-Programmable Gate Arrays

Sponsored by ACM SIGDA, with support from Altera, Xilinx, and Actel 

Monterey Beach Hotel, Monterey, California
February 9-11, 1997
(Web page: http://www.ece.nwu.edu/~hauck/fpga97)

The annual ACM/SIGDA International Symposium on Field-Programmable Gate Arrays 
is the premier conference for presentation of advances in all areas 
related to the FPGA technology.  The topics of interest of this symposium 
include, but are not limited to: 

o Advances in FPGA architectures, including design of programmable logic blocks,
    programmable interconnects, programmable I/Os, and development of new 
    FPGAs and field-configurable memories.
 
o New CAD algorithms and tools for FPGAs,  including new algorithms for 
    sequential and combinational logic optimization, technology mapping, 
    partitioning, placement, routing, and development of new FPGA synthesis or 
    layout systems.
 
o Novel applications of FPGAs, including rapid prototyping, logic emulation,
    reconfigurable custom computing, and dynamically reconfigurable 
    applications.
 
o Advances in field-programmable technology, including new process 
    and fabrication technologies, and field-programmable analog arrays.

Authors should submit 20 copies of their original work by September 27, 1996.
Each submission should include an 100-250 words abstract, and is limited 
in length to 12 pages (including figures and tables, minimum point size 10).  
Notification of acceptance will be sent by November 18, 1996. 
A proceedings of accepted paper will be published by ACM. 
Authors must assign copyright of their accepted papers to ACM as a condition 
of publication. Final versions of accepted papers will be limited 
to seven pages, and must be submitted by December 6, 1996. 
All submissions should include the e.mail addresses of the authors, as all
correspondence with authors will be done via e.mail.

Submissions should be sent to:

Prof. Jason Cong 
FPGA'97 Program Chair
UCLA Computer Science Department 
4711 Boelter Hall
Los Angeles, CA 90095
Phone: (310) 206-2775,  Fax: (310) 825-2273, E.mail:  fpga97@cs.ucla.edu

Organizing Committee:

General Chair:    Carl Ebeling, University of Washington
Program Chair:    Jason Cong, UCLA
Publicity Chair:  Scott Hauck, Northwestern University
Finance Chair:    Jonathan Rose, University of Toronto
Local Chair:      Pak Chan, UC Santa Cruz 

Program Committee:

Michael Butts           Quickturn
Pak Chan                UCSC
Jason Cong              UCLA
Carl Ebeling            U. Washington 
Masahiro Fujita         Fujitsu Labs 
Scott Hauck             Northwestern Univ.
Dwight Hill             Synopsys
Brad Hutchings          BYU
Sinan Kaptanoglu        Actel
David Lewis             U. Toronto
Jonathan Rose           U. Toronto
Richard Rudell          Synopsys
Rob Rutenbar            CMU
Gabriele Saucier        Imag
Martine Schlag          UCSC
Tim Southgate           Altera
Steve Trimberger        Xilinx
Martin Wong             UT Austin
Nam-Sung Woo            Lucent Technologies
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
|               Scott A. Hauck, Assistant Professor                         |
|  Dept. of EECS                       Voice: (847) 467-1849                |
|  Northwestern University             FAX: (847) 467-4144                  |
|  2145 Sheridan Road                  Email: hauck@eecs.nwu.edu            |
|  Evanston, IL  60208                 WWW: http://www.eecs.nwu.edu/~hauck  |
+-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+


Article: 3288
Subject: Re: Please help with CRC hardware implementation - crcgen.zip (0/1)
From: Bob Elkind <eteam@aracnet.com>
Date: Thu, 09 May 1996 17:46:42 +0100
Links: << >>  << T >>  << A >>
peter@kksystems.com wrote:
>  
> I am working on an ASIC, and I need a hardware implementation of the
> standard CCITT CRC algorithm: x^16+x^12+x^5+1 as used in floppy disk
> controllers. 
Try this...

the + means exclusive OR gate, the boxes with numbers in
them are the 16 bits of the CCITT-CRC.

  DIN --------> +  -----------|
                ^             |
                |             |
             ======           |
             =  0 =           |
             ======           |
             =  1 =           |
             ======           |
             =  2 =           |
             ======           |
             =  3 =           |
             ======           |
                ^             |
                |             |
                + <-----------|
                ^             |
                |             |
             ======           |
             =  4 =           |
             ======           |
             =  5 =           |
             ======           |
             =  6 =           |
             ======           |
             =  7 =           |
             ======           |
             =  8 =           |
             ======           |
             =  9 =           |
             ======           |
             = 10 =           |
             ======           |
                ^             |
                |             |
                + <-----------|
                ^             |
                |             |
             ======           |
             = 11 =           |
             ======           |
             = 12 =           |
             ======           |
             = 13 =           |
             ======           |
             = 14 =           |
             ======           |
             = 15 =           |
             ======           |
                ^             |
                |             |
                --------------|

-- 
**************************************************************************
Bob Elkind                email:eteam@aracnet.com             CIS:72022,21
7118 SW Lee Road                         part-time fax number:503.357.9001
Gaston, OR 97119                     cell:503.709.1985   home:503.359.4903
******** Video processing, R&D, ASIC, FPGA design consulting *************


Article: 3289
Subject: Reposting of: FPGA for SPACE/RADIATION applications
From: rgreene@netaxs.com (Richard M. Greene)
Date: Thu, 09 May 96 16:53:26 GMT
Links: << >>  << T >>  << A >>
This is a reposting for benefit of those who didn't catch the initial posting.

We have just completed the preliminary design evaluation and specifications 
for a RAD-HARD FPGA suitable for military,  space, and radiation applications. 
We would like to hear from interested potential users as to their level of 
interest, future requirements and specification suggestions (gate count, SEU 
requirements, CAD compatibility, etc) for such a device.

 All inputs welcomed.

--------------------------------------------------------------------
       _______	    _______                                       ?
      / _____ \    / _____ \          AEROSPACE DESIGN CONCEPTS   ^
     / /     \ \  / /     \ \            MEMORIES INTO SPACE     ^
  __/ /__    | |__| |    __\ \__             PLVS VLTRA . . . . ^
 /__| |_ \   /      \   / _| |__\
    | | | | | _    _ | | | | |             THE RAMMAN
    | |_| | | \\  // | | |_| |              Richard Greene
     \___/   \ "  " /   \___/                E-MAIL:R.GREENE@IEEE.ORG
              |    |                          HUMAN:(609) 859-8833
              | oo |                           FAX: (609) 859-3671
               \__/                             VINCENTOWN, NJ 08088




Article: 3290
Subject: Re: Is XC7336 the least expensive CPLD?
From: holmes@yaz.chrysal.com (Christopher G. Holmes)
Date: Thu, 9 May 1996 17:47:13 GMT
Links: << >>  << T >>  << A >>
In article <peter-0805961517470001@appsmac-1.xilinx.com> peter@xilinx.com (Peter Alfke) writes:

> From: peter@xilinx.com (Peter Alfke)
> Newsgroups: comp.arch.fpga
> Date: 8 May 1996 22:15:33 GMT
> Organization: Xilinx
> 
> In article <4mon6i$bko@news.cc.utah.edu>, gf0570 <fang@signus.utah.edu> wrote:
> 
> > Hi,
> >     Is XC7336 the cheapest CPLD one can find in the CPLD marcket?
> 
> XC7318 is half the size, and therefore cheaper. For prices, contact the
> appropriate distributor. You find their names and phone numbers in any
> data book, page 10-6 in the Xilinx data book.
> 
> Peter Alfke, Xilinx Applications

This was true in the past, but our distributor tells us Xilinx is ramping
down production on the 7318's, so they're now more expensive than the 7336
(at least for the speed/pkg we looked at).  The 7336 will take over as the
entry-level chip in that family.

Chris





-- 
=============================================================================
Christopher Holmes			Providing Full Product Development:
Chrysalis Research Corporation		* System Architecture
52 Domino Drive, Concord, MA 01742-2817	* ASIC and FPGA Design
Phone:	508-371-9115			* VHDL/Verilog Modeling & Synthesis
Fax:	508-371-9175			* EMI - EMC Consulting Services 
Me:	holmes@chrysal.com		Business Inquiries: info@chrysal.com


Article: 3291
Subject: Re: Simple Xilinx board
From: William L Hunter Jr <whunte1@osf1.gmu.edu>
Date: Thu, 09 May 1996 15:01:28 -0400
Links: << >>  << T >>  << A >>
William J. Wolf wrote:
> 
> ian@PROBLEM_WITH_INEWS_DOMAIN_FILE (Ian McCrum STAFF) writes:
> > we want to use a simple parallel cable, no expensive Xchecker.
> 
> Xchecker comes with the software, so I don't follow.
> 
> I think you get one per license, so unless people hoard them
> this should suffice.  How much is an extra Xchecker cable?
> 
> ---
> - Bill Wolf, Raleigh NC
> - My opinions, NOT my employer's

A extra Xchecker cable cost $495.00.

Bill


Article: 3292
Subject: Xilinx Placement and Routing Tools
From: morteza@vast.unsw.edu.au (Morteza Saheb Zamani)
Date: 10 May 1996 01:46:14 GMT
Links: << >>  << T >>  << A >>

Hi,

I am going to use Xilinx placement and routing tools (PPR) for a hierarchical
design. I need to constrain the tool to follow my predefined floorplanning.
This may be done by defining regions interactively by using the xilinx floorplanner. However, Since my floorplan is generated by an automatic 
floorplanning package, I need to specify the regions in one of the PPR 
input files to be used by PPR automatically.

I have tried to specify some regions for the modules of the top level of
hierarchy (soft modules) by putting some LOC statements, like:

SYM,adder4_1,adder4,LIBVER=2.0.0,SYSTEM=XMACRO,LOC=CLB_R1C1:CLB_R4C8

but it fails and cannot place it.

I have also tried to put the constraints in .cst file as:
PLACE INSTANCE adder4_1: [CLB_R1C1 CLB_R4C8];

but still cannot work.

Does ayone know what is the problem?

Regards,
Morteza

____________________________________________________________
Morteza   Saheb Zamani     E-mail:  morteza@vast.unsw.edu.au
VaST Lab,
School of Computer Sc. & Eng.
University of N.S.W.       Phone:   +61 2 385-4898
Sydney, 2052, AUSTRALIA    FAX:     +61 2 385-5995
____________________________________________________________



Article: 3293
Subject: The PARALLEL Processing Connection - May 13th Meeting Notice
From: parallel@netcom.com (B. Mitchell Loebel)
Date: Fri, 10 May 1996 06:14:25 GMT
Links: << >>  << T >>  << A >>

May 13th - Run-Time Reconfigurable Hardware - A Design Case History

Dynamically reconfigurable SRAM-based FPGAs are the basic 
building blocks of custom computing machines (CCMs). The 
Component Generator Tool from Atmel is used to develop libraries of 
modules - programmable counter/timers, high-speed computational 
elements (adders, accumulators, multipliers, registers), etc.  
Combinations of these modules can be loaded into the FPGA based 
upon different operational requirements.  Hardware so tailored for 
algorithms results in higher system performance across a broader range 
of applications than can be realized with fixed hardware.  And, as new 
modules are being loaded into one area of the FPGA, the remaining 
sections continue to operate undisturbed, i.e. real-time operation and 
"soft hardware". 

Martin Mason and Lee Ferguson of Atmel will describe the architecture 
of the partial dynamic reconfiguration Atmel FPGA system and the 
design tools that are available.  The techniques used to create 
"windowed" bit-streams necessary for partial reconfiguration and 
guidelines for practical design implementation will also be discussed.  A 
FIR filter design for digital audio will provide a case history backdrop 
for their presentation and a short demonstration is planned.

The main meeting starts promptly at 7:30PM at Sun Microsystems at 
901 San Antonio Road in Palo Alto. This is just off the southbound San 
Antonio exit of 101.  Northbound travelers also exit at San Antonio and 
take the overpass to the other side of 101.  A discussion of member 
projects currently underway and other issues of interest to entrepreneurs 
follows immediately thereafter at 9PM.

Please be prompt; as usual, we expect a large attendance; dont be left 
out or left standing. There is a $10 fee for non-members and members 
will be admitted free.  Yearly membership fee is $50.
-- 
B. Mitchell Loebel                                      parallel@netcom.com 
Director - Strategic Alliances and Partnering                  408 732-9869 
PARALLEL Processing Connection 


Mktg. Director
Minute-Tape International Corporation 


Article: 3294
Subject: The PARALLEL Processing Connection - What Is It?
From: parallel@netcom.com (B. Mitchell Loebel)
Date: Fri, 10 May 1996 06:15:41 GMT
Links: << >>  << T >>  << A >>

The PARALLEL Processing Connection is an entrepreneurial 
association; we mean to assist our members in spawning very 
successful new businesses involving parallel processing.

Our meetings take place on the second Monday of each month at 
7:30 PM at Sun Microsystems at 901 South San Antonio Road in 
Palo Alto, California. Southbound travelers exit 101 at San 
Antonio ; northbound attendees also exit at San Antonio and take the 
overpass to the other side of 101. There is an $10 visitor fee for non-
members and members ($50 per year) are admitted free. Our phone 
number is (408) 732-9869 for a recorded message about upcoming 
meetings; recordings are available for those who can't attend -
please inquire.

Since the PPC was formed in late 1989 many people have sampled 
it, found it to be very valuable, and even understand what we're up 
to. Nonetheless, certain questions persist. Now, in our seventh year of 
operation, perhaps we can and should clarify some of the issues. For 
example:

Q.  What is PPC's raison d'etre?
A.  The PARALLEL Processing Connection is an entrepreneurial 
organization intent on facilitating the emergence of new businesses. 
PPC does not become an active member of any such new entities, ie: 
is not itself a profit center.

Q.  The issue of 'why' is perhaps the most perplexing. After all, a 
$50 annual membership fee is essentially free and how can anything 
be free in 1996? What's the payoff? For whom?
A.  That's actually the easiest question of all. Those of us who are 
active members hope to be a part of new companies that get spun 
off; the payoff is for all of us -- this is an easy win-win! Since 
nothing else exists to facilitate hands-on entrepreneurship, we 
decided to put it together ourselves. 

Q.  How can PPC assist its members?
A.  PPC is a large technically credible organization. We have close 
to 100 paid members and a large group of less regular visitors; we 
mail to approximately 400 engineers and scientists (primarily in 
Silicon Valley). Major companies need to maintain visibility in the 
community and connection with it; that makes us an important 
conduit. PPC's strategy is to trade on that value by collaborating 
with important companies for the benefit of its members. Thus, as 
an organization, we have been able to obtain donated hardware, 
software, and training and we've put together a small development 
lab for hands-on use of members at our Sunnyvale office. Further, 
we've been able to negotiate discounts on seminars and 
hardware/software purchases by members. Most important, 
alliances such as we described give us an inside opportunity to 
JOINT VENTURE SITUATIONS.

Q.  As an attendee, what should I do to enhance my opportunities?
A.  Participate, participate, participate. Many important industry 
principals and capital people are in our audience looking for the 
'movers'!

For further information contact:
-- 
B. Mitchell Loebel                                      parallel@netcom.com 
Director - Strategic Alliances and Partnering                  408 732-9869 
PARALLEL Processing Connection 


Mktg. Director
Minute-Tape International Corporation 


Article: 3295
Subject: socket wanted for xilinx or other way to plug in
From: tw38966@vub.ac.be (Rafiki Kim Hofmans)
Date: 10 May 1996 08:03:07 GMT
Links: << >>  << T >>  << A >>
Hi,

Is there anyone who can sell me a PQsocket-160 for the Xilinx4010EPQ160 ?
I only need one or two. In Belgium I have to buy immediately 15 of them 
and they cost about 40$ each (A.M.P), the sockets of 3M cost about 30$ but 
I have to buy 100 of them :(
So anyone who has a socket or two and willing to sell them ?

If not, is there any other way to plug a Xilinx4010E PQ160 on a 2 layer PCB ?
Don't laugh, this PCB will serve as a prototype for a PCI interface.
But it will take several weeks before the 4 layer PCB will arrive.
In the mean time I'm gone try to test it with a 2 layer PCB.
But all the work, I have to do it on my own and because I'm not very 
handy... I'd like some good advice.

Thanks in advance !

Kim
 
PS : I can pay with VISA


Article: 3296
Subject: which coding style is better for synthesis?
From: flxchen@diig.dlink.com.tw (Felix K.C. CHEN)
Date: Fri, 10 May 1996 17:57:14 +800
Links: << >>  << T >>  << A >>
Dear Friends,

I got different synthesis results using Exemplar on the same logic but
with different default statements.  At least in my example,
style 2 seems better than style 1 (I set constraint in area).
But I am not sure if it is a golden rule of coding style for
synthesis.  Could any one say something about it? 

(style 1)
         when S0 =>
            case (event1 & event2) is
            when "00" =>
              state <= S1;
            when "01" =>
              state <= S2;
            when others =>
              null;  -- I suppose that it implies state <= S0;
            end case;
         when ........

(style 2)
         when S0 =>
            case (event1 & event2) is
            when "00" =>
              state <= S1;
            when "01" =>
              state <= S2;
            when others =>
              state <= S0;
            end case;
         when ........

Many thanks,

Felix K.C. CHEN
-- 
---------------------------------
Felix, Kuan-chih CHEN ( a )
Associate Project Manager
System Product Division
D-Link Co., Hsin-chu, Taiwan
Email: flxchen@diig.dlink.com.tw

Machines and tools are only as
good as the people who use it.
---------------------------------


Article: 3297
Subject: Looking for free FPGA softw./Xilinx
From: Christopher <101337.2254@CompuServe.COM>
Date: 10 May 1996 11:26:01 GMT
Links: << >>  << T >>  << A >>
Hi guys out there in the world,

I am looking for free tools (or shareware) to program for 
instance the XC3030.
I dont need schematic capture etc. for me it is sufficiant if I 
can enter logic equations. It would be great if there is maybe a 
subset of VHDL implemented to describe state machines.

Anybody who can point me into the right direction?

thanks very much
Chris


Article: 3298
Subject: Re: Synario Universal FPGA Design System
From: amblard@imag.fr (Paul Amblard)
Date: 10 May 1996 12:30:39 GMT
Links: << >>  << T >>  << A >>
In article <kurt-0205960828140001@192.55.89.50>,
Volker Kurt Kamp <kurt@emphasys.de> wrote:
>And we want to use it for Xilinx designs. In the Xilinx solution we need
>to have control over mapping and placing of clb's.
--- (it = Synario)

I had a glance this morning on the one-page presentation of Synario.

If I well understood it contains "only" synthesis and simulation.
You enter your design in
ABEL, Verilog (VHDL ??????) or schematics
you can simulate it
you can obtain a XNF file if interested in Xilinx (ot other for Altera, ....)

To "control mapping" to Xilinx seems out of the tool. I understood that this is
"hidden" in the syntesizer.
Controling placement can only be done with xilinx tools (xact, + viewlogic
maybe)

I do not represent Synario.
I read only a one page description. I did not work on the system.


-- 
Paul AMBLARD      L.G.I. I.M.A.G.     BP 53	F 38041 GRENOBLE Cedex 9
Tel (33) 76827212      bat. Ensimag bur. 101bis    Paul.Amblard@imag.fr


Article: 3299
Subject: Re: Looking for free FPGA softw./Xilinx
From: Andy Gulliver <andy.gulliver@crossprod.co.uk>
Date: Fri, 10 May 1996 14:19:30 +0100
Links: << >>  << T >>  << A >>
Christopher wrote:
> 
> Hi guys out there in the world,
> 
> I am looking for free tools (or shareware) to program for
> instance the XC3030.
> I dont need schematic capture etc. for me it is sufficiant if I
> can enter logic equations. It would be great if there is maybe a
> subset of VHDL implemented to describe state machines.


Unlikely, I would have thought :-(

Even the cheapest XILINX tools are around 1000ukp minimum ,3rd party s/w 
tends to be even more expensive.....

-- 
Regards

AndyG




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