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Messages from 3350

Article: 3350
Subject: considering a new XC4010E/XC4013E proto board with RAM
From: jangr@microsoft.com (Jan Gray)
Date: 17 May 1996 05:52:17 GMT
Links: << >>  << T >>  << A >>
Whereas:
* I'm a hobbyist -- and I wish to encourage other hobbyists to try FPGAs.
* I'm fed up with wire-wrapping and want to try designing my own PC boards;
* The PQFP versions of the XC4010E and XC4013E are much less costly than
  the PGA versions (and an XC4010E-PC84 just doesn't have enough I/Os).
* I need 64-bits of fast SRAM and DRAM for my current wide word RISC project.

I'm thinking of designing a little prototyping board with 64-bit RAM bus.

Possible features include:
* 208 pin PQFP pads for one XC4010E or XC4013E
* header pins to expose all the FPGA I/Os for wire wrapping etc.
* 3x4" or so wire wrap area
* SRAM - two 32Kx32 pipelined burst SRAMs (100 pin PQFPs)
  or perhaps a 160-pin COAST (cache on a stick) SRAM module socket
* DRAM - one 168-pin DIMM or two 72-pin SIMMs for optional 64-bit DRAM
  (FPM, EDO, or sync)
* xchecker compatible header pins
* MAX-23x RS-232 level converters and 2 9-pin DIN sockets
* bytewise flash ROM (for data or for master parallel config)
* miscellaneous features also found on Xilinx FPGA demo board:
  configuration DIP switches, crystal socket, some LEDs, etc.
* perhaps a small LCD display
* ISA bus connector? (less important)
* stackable or abuttable? (less important)

Component costs roughly $200/FPGA + $50 (SRAM) + $50 (rest)
+ $??? small run of 4-layer boards + $??? assembly.  I have no
confidence in my ability to hand assemble a board with a 0.5mm
pitch PQFP...

In terms of FPGA floor plan, the 64-bit RAM data path would go to 32
left edge and 32 right edge IOBs.  For instance, for a XC4010E it might
be the pads adjacent to the long lines on rows 5-20.  The 16-bit-or-so
RAM address lines and other control signals would leave the top middle IOBs.


Please reply by email:
* if you know of an inexpensive (<$500) instance of a similar
  board already
* if you might want one/some of these boards, populated or not,
* if you have any ideas or preferences regarding features above,
* if you could help with the design, layout, or manufacture, or
* if you do board layout or manufacture professionally and would like
  to bid on this job
* if you have any other advice to offer

Ideally there is some university out there with PCB manufacturing
tools and experience who could use a small run of such boards.  In
which case we could collaborate on the design/documentation and you
could perform the actual low volume assembly/manufacturing.

Cheers,
Jan Gray
Redmond, WA
--
The opinions expressed in this message are my own personal views 
and do not reflect the official views of Microsoft Corporation.



Article: 3351
Subject: Re: Xilinx 4013 80% utilized but won't route
From: erik@blender (Erik de Castro Lopo)
Date: 17 May 1996 08:35:39 GMT
Links: << >>  << T >>  << A >>
Brad Taylor (blt@emf.net) wrote:
: Eric Ryherd wrote:
: > 
: > Hi,
: > 
: > Anyone have experience with Exemplar and Xilinx 4013s where it
: > was only 80% utlilized but wouldn't route?
: > In synopsys language, I think I need to increase the "porocity"
: > of the design. I have other designs that are 90% and route, but
: > for some reason this one is real bad.
: > ^^^^^^^^^^^^^^^
: >
:  The real problem
:  here is that you have absolutely no feedback on what is hanging up the 
:  router.  If PPR was to print the signal names which were failing to 

The Xilinx XACT software does give feedback on which signals it can't
route. All unrouted signal names are listed in the file :

		<projectname>.rpt
		
Unfortunately, in my experience, this is less use than it may at first
seem. 

Your tip on hand placing is however something I'd like to try out on
some of my less routable designs.

Erik.


Article: 3352
Subject: Re: Comp.Arch.FPGA Reflector V1 #541
From: john@einstein.vcc.com (John Schewel)
Date: Fri, 17 May 1996 20:53:27 GMT
Links: << >>  << T >>  << A >>
> From: jangr@microsoft.com (Jan Gray) 
> Subject: considering a new XC4010E/XC4013E proto board with RAM 
> 
> * I'm a hobbyist -- and I wish to encourage other hobbyists to try FPGAs. 
> * I'm fed up with wire-wrapping and want to try designing my own PC boards; 

In response to a message from Jan Gray.....
for a number of years we have disscussed the
need for a low cost reconfigurable system for
the engineer and hobbyist.... for a couple
of years we have been talking with design/implementation
software manufacturers for a low cost (under $500) development
package to be bundled with a 'hobbyist' board.... this past
year we committed to building the board even though we could
not get the any software house to go alone with the inexpensive
bundle.....

> * The PQFP versions of the XC4010E and XC4013E are much less costly than
>   the PGA versions (and an XC4010E-PC84 just doesn't have enough I/Os).
> * I need 64-bits of fast SRAM and DRAM for my current wide word RISC project.

we had to make a few trade offs between bare bones and useful features...
the Virtual ISA Proto Board was the result (see below for details)
> 
> * if you know of an inexpensive (<$500) instance of a similar
>   board already
>
  Although the current price is $1100 /w XC5210-6      $1400 /w the XC 4013E...
 we felt the features included were import...... 

 though we are contemplating further cutting the cost (thus price) by
 removing the HP Analyzer capablilities (2 layers).....any comments... 

best

john schewel

-----------------------------------------------------------------------------

VIRTUAL COMPUTER CORPORATION's Reconfigurable Computers

Announces
		The Virtual ISA Proto Board (tm)
		   'An Electronic Sandbox'

		    A Virtual Computer (tm)


The Virtual ISA Proto Board- is a reconfigurable development system with
prototyping features.  It provides an integrated tool set consisting of 
software driver,  Windows software support, Plug n' Play interface, and a 
reference logic configuration library for 'canned' configurations for the 
on-board FPGA.  The features of the board have been specifically selected 
to provide a flexible and configurable base platform from which developers 
can easily spring off into their areas of expertise.   The driver source 
code supplies the programmer with  a functional base and reference code 
for multiple Window operating environments from which applications can be 
built. Hardware features include 10,000 reconfigurable logic gates, signal 
break-outs, logic analyzer interface, a Plug n Play interface, two PCB grid 
areas, and an optional programmable oscillator. All Xilinx pins broken out 
for ease of logic analysis.  The - Virtual ISA Proto  Board provides a 
low-risk platform for the immediate trial and implementation of new projects 
and continuing development.  

An Optional  Multi-FPGA Daughter Board allows for multiple FPGA Application 
designs.  The daughter board plugs onto the Proto Board's XC5210-6 Breakout 
Pins. (in development)

The Virtual Computer, reconfigurable computer was developed to support the
standard, proven CAE design systems for FPGA implementation. The major
difference between the Virtual Computer platform and standard implementations 
of FPGA designs comes in the design's downloading process.

Whe using the Virtual Computer platform, the digital design is converted to a 
`C' program routine format. This enables the developer to download their 
designs on-the-fly  into the FPGA through normal `C' programming. The result
is a fast, simple and powerful method for testing, perfecting and using digital
designs over and over.

 Single Xilinx XC5210-PQFP160  (or/ XC4013E)
 IBM PC/Compatible
 Supports 8/16 bits ISA operation mode, Plug n Play spec.V1.0a and Windows95
  ready
 Fujitsu MB86701 Plug and Play interface for fully compliant interface 
  (includes all     drivers & config.)
 Two user feed through grids areas (opposite ends of board), for Analog and
  Digital prototyping
 Support for 2 - 30pin SIMMs (SIMMS not included), EEROM and 32KB 
  SRAM
 Ground and power test points --- Separate power and ground planes for signal
  integrity     (TBD)
 All Xilinx pins available on .100" headers --- Silk screen coordinates and
  Signal list for ease of use
 Xilinx FPGA supports all configuration modes:  Peripheral ISA Bus,  Serial
  Slave Download   (Xchecker), Master Parallel (on board ROM), Master Serial 
  (on board serial ROM)
 Logic Analyzer interface for industry standard HP logic analyzer through 
  auxillary connect board
 Programmable Oscillator  360kHz to 120 MHz  (Optional)
 Multi-FPGA Daughter Board  (Optional)

-  Schematics,
-  Manual,
-  Interface Software (Viewlogic not incl.),
-  Driver 
-  Examples Programs with Source Code
-  Service & Support contract available

Xilinx Development tools and Design Entry Software are needed. (not incl.)


PRICING:

 ISA1 -- Virtual ISA Proto Board   w/1 - XC5210-6                 $1100.00 USD
    Includes  Interface (Schematic, VHDL & Verilog), 'C' function routines.

 ISA2 -- Virtual ISA Proto Board  w/1 - XC4013E-3                 $1499.00 USD

 MISA-5210 -- Multi-FPGA Daughter Board   w/ 4-XC5210-6	           $1134.00 USD
 MISA-4013E-- Multi-FPGA Daughter Board   w/ 4-XC4013E-3           $2520.00 USD
 POM-2     -- Programmbale Oscillator                                $99.00 USD

    	excl. shipping &  CA sales tax (if purchased in CA)
(VCC's University Program Discount of 15% off for all items)
_______________________________________
Prices subject to change without notice.
_____________________________________________________________
For Further Information, Contact:

John Schewel, VP Marketing & Sales
VIRTUAL COMPUTER CORPORATION 6925 CANBY AVE #103  
RESEDA, CA 91335 USA  (818)342-8294  fax (818)342-0240
E-MAIL  jas@vcc.com


Article: 3353
Subject: A Collection of VHDL, FPGA Resources on Web
From: huang@engr.uky.edu
Date: 17 May 1996 21:30:45 GMT
Links: << >>  << T >>  << A >>
Hi, Everyone there:

  I've made a collection of VHDL, FPGA Resources on Web. It can be found at:
http://www.ewl.uky.edu/~huang/jimmy.html. it's especially designed for those who 
are new to VHDL and FPGA. Check the appropriate entry in MAIN MENU.

Good luck!

Jimmg Huang


Article: 3354
Subject: Re: is high input number mutliplxer inferrable?
From: "Martin Radetzki" <Martin.Radetzki@Informatik.Uni-Oldenburg.DE>
Date: Sat, 18 May 1996 13:08:43 +0200
Links: << >>  << T >>  << A >>
Felix K.C. CHEN wrote:
> 
> Dear friends,
> 
> I want to make the VHDL synthesizer (Synopsys's Design compiler
> or Galileo's Logic Explorer) infer multiplexor.  I do not want
> to use design ware (or modgen) in component instantiation
> style.  Can any one tell me is there any difference in the
> results of synthesis between the two codes:
> 
> process(SEL, INP_A, INP_B, INP_C, INP_D) -- INPs is 32 bit bus each
> begin
> case SEL
> when "00" =>
>   OUTP <= INP_A;
> when "01" =>
>   OUTP <= INP_B;
> when "10" =>
>   OUTP <= INP_C;
> when others =>
>   OUTP <= INP_D;
> end case;
> end process;
> 
> with SEL select
> OUTP <= INP_A when "00",
>         INP_B when "01",
>         INP_C when "10",
>         INP_D when others;
> 
> As I know that most FPGA vendors provide multiplexor hard macro
> up to 4->1, I do not know how smart synthesizer can be for
> inferring multiplex functions with input number larger than 4?
> Any comment?
> 
> By the way, from my experience, Exemplar's Galileo seems not infer
> MX4 macro for the codes above when targeting Actel DX32000.
> The evidence is that the synthesis gate count is much
> larger than (32 * MX4 + possible fan-out buffers for SEL).
> Perhaps I have made mistakes, but I am really frustrated.
> 
> Regards,
> 
> Felix K.C. CHEN
> 
> --
> ---------------------------------
> Felix, Kuan-chih CHEN ( a )
> Associate Project Manager
> System Product Division
> D-Link Co., Hsin-chu, Taiwan
> Email: flxchen@diig.dlink.com.tw
> 
> Machines and tools are only as
> good as the people who use it.
> ---------------------------------

Felix,

the concurrent conditional signal assignment (WITH ... SELECT) is
equivalent to a process with an if...elsif statement (cf. LRM,
IEEE Std 1076-1987, p. 9-9):

process( SEL, INP_A, INP_B, INP_C, INP_D )
begin
  if SEL = "00" then
    OUTP <= INP_A;
  elsif SEL = "01" then
    OUTP <= INP_B;
  elsif SEL = "10" then
    OUTP <= INP_C;
  else
    OUTP <= INP_D;
  end if;
end process;

Recently, there was a discussion about different synthesis results
from if and case statements in this newsgroup. Trying synthesis on
your examples and my process using Synopsys and an ASIC library,
I encountered that:
- the same multiplexor structure was produced in all the three cases
  (using And-Or-Invert-Gates instead of mux cells)
- the control logic for the multiplexor structure was equivalently
  synthesized from your WITH-Statement and my process, but slightly
  more complex from your CASE-Statement.

>From a short look at Actel's homepage , I suppose that it doesn't
matter whether the 4x1 multiplexor hard macro is used or an equivalent
structure, if both can be allocated in one C(ombinational)-Module
of the 3200DX which provides 4 normal and 2 control inputs, if my
interpretation of the "3200DX Floorplan" on 

      http://www.actel.com/marcom/prodbrief/pb32_c.html

is correct. From my experience with Altera FPGAs, I suggest you should
place&route a hand-coded mux-macro example and a synthesized
non-mux-macro example on the FPGA and compare the number of allocated
FPGA cells afterwards instead of measuring the pre-routing gate count.

By the way, is the mux macro available in the synthesis technology
library or only for hand-instantiation?

Hope this helps,
Martin.

------------------------------------------------------------------------
Martin Radetzki      e-mail: martin.radetzki@informatik.uni-oldenburg.de
Carl v. Ossietzky University
D-26111 Oldenburg, Germany


Article: 3355
Subject: Re: Xilinx 4013 80% utilized but won't route
From: Brad Taylor <blt@emf.net>
Date: Sat, 18 May 1996 10:19:05 -0700
Links: << >>  << T >>  << A >>
Erik de Castro Lopo wrote:
> 
> Brad Taylor (blt@emf.net) wrote:
> : Eric Ryherd wrote:
> : >
> : > Hi,
> : >
> : > Anyone have experience with Exemplar and Xilinx 4013s where it
> : > was only 80% utlilized but wouldn't route?
> : > In synopsys language, I think I need to increase the "porocity"
> : > of the design. I have other designs that are 90% and route, but
> : > for some reason this one is real bad.
> : > ^^^^^^^^^^^^^^^
> : >
> :  The real problem
> :  here is that you have absolutely no feedback on what is hanging up the
> :  router.  If PPR was to print the signal names which were failing to
> 
> The Xilinx XACT software does give feedback on which signals it can't
> route. All unrouted signal names are listed in the file :
> 
>                 <projectname>.rpt


The report will only tell you the signals that failed to route entirely.
What I should have said, was that PPR could print the names of the signals  
it is having trouble routing.  If these signals are eventually routed, 
the information is lost. This partial information is necessary if 
you are you trying to speed up routing, or trying to improve the 
placement for timing reasons or to increase density by mapping.

This would also make the routing a little more 
interesting for those of us with nothing better to do than watch the 
screen during routing.  A real time XACT view would be even more fun.
Waiting for routes is a good time to do floorplanning.

By the way I just upgraded from a 486-66 to a Pentium-120 and it cut 
my total compile time on a project from 55 minutes to 19 minutes.  
The Project was an XC4010E 50% full with pins located and generally 
unlocated logic with lots of RPMs , and went from source code to .bit 
file to simulatable .xnf.  I wonder if there are any standard benchmark
.xnf files I could use to compare my compile performance to other 
systems, such as Suns, Pentium Pro ... It would also be useful to 
measure the effect of floorplanning on routing time, and much more 
importantly, timing and density.

-
Brad



Article: 3356
Subject: Introduction to FPGAs
From: Biju Nair <bn@cacs.usl.edu>
Date: Sat, 18 May 1996 18:52:49 -0500
Links: << >>  << T >>  << A >>
Can any one suggest some introductory materials on FPGAs.


Article: 3357
Subject: Re: is high input number mutliplxer inferrable?
From: David Barr <david@oren.co.il>
Date: Mon, 20 May 1996 08:53:25 +0200
Links: << >>  << T >>  << A >>
Felix K.C. CHEN wrote:
> 
> Dear friends,
> 
> I want to make the VHDL synthesizer (Synopsys's Design compiler
> or Galileo's Logic Explorer) infer multiplexor.  I do not want
> to use design ware (or modgen) in component instantiation
> style.  Can any one tell me is there any difference in the
> results of synthesis between the two codes:

[examples snipped]

What version of Design Compiler are you using. As of version 3.4a it 
has the capability of using muxes from the target library. This might 
help you do what you wish.

-- 
David Barr.

Oren Semiconductor Ltd.,      | E-mail: david@oren.co.il
P.O.Box 201,                  | Tel:    +972-4-9894565  
Yoqne'am Illit 20692,         | Fax:    +972-4-9894566  
Israel.                       |


Article: 3358
Subject: Xilinx and Viewlogic
From: Dr Edmund Lai <E.Lai@cowan.edu.au>
Date: Mon, 20 May 1996 15:10:03 +0800
Links: << >>  << T >>  << A >>
I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series
software tools.  We are having a lot of problems with ProCapture and
Prosim running under Windows 95 in a Pentium machine with 16Mb RAM.

The "add-component" window of ProCapture has to be turned off.
Otherwise the system will crash.  Also, we cannot get Prosim running
at all.

Has anyone got this experience?  It has been difficult to get any
technical support.  They simply don't reply.  We will be grateful
for any comments and/or help.

Edmund Lai


Article: 3359
Subject: PCI fpga
From: mes@odme.nl (Martin van Eersel)
Date: Mon, 20 May 1996 14:12:23 GMT
Links: << >>  << T >>  << A >>
Hello,

We are just starting with a project to get some experience with a PCI add in 
card for a Windows NT PC.

The card should have a high speed data channel, an interrupt, and some 
settings registers.

Can you give me some hints or tips, or better still, does anybody have a VHDL 
/ Schematic design for Xilinx XACT 6.0 for a PCI interface ?


Thanks in advance


Martin van Eersel
Media Morphics
mes@odme.nl



Article: 3360
Subject: Re: PCI fpga
From: tw38966@vub.ac.be (Rafiki Kim Hofmans)
Date: 20 May 1996 15:17:49 GMT
Links: << >>  << T >>  << A >>
Martin van Eersel (mes@odme.nl) wrote:
: Hello,

: We are just starting with a project to get some experience with a PCI add in 
: card for a Windows NT PC.

: The card should have a high speed data channel, an interrupt, and some 
: settings registers.

: Can you give me some hints or tips, or better still, does anybody have a VHDL 
: / Schematic design for Xilinx XACT 6.0 for a PCI interface ?


: Thanks in advance


: Martin van Eersel
: Media Morphics
: mes@odme.nl

Well, actually... a part of my thesis concerns implementing a PCI
interface in a Xilinx FPGA 4010E pq160.
The PCI interface is finished (done with viewlogic). But I dunno if it
works because I'm still waiting for my PCB.

Anyways if you need, hints, tips, answers about PCI design, you can mail me.
I'm not a PCI expert though cuz I only started this year studying it's
architecture.

Cheers,

Kim

PS : the Netherlands -> Belgium         : 2 points
     Belgium         -> the Netherlands : 1 point.

Ain't we nice for each other ? ;)

--


==============================================================================

			************************************
			*	Hofmans Kim 		   *	
  		       	*				   *
			*	tw38966@vub.ac.be	   *
			*	khofmans@info.vub.ac.be	   *
			*                                  *
			*	Brouwerijstraat 62         *
			*	1630 Linkebeek             *
			*	Belgium 		   *
			*				   *
			*	32-2-3771012		   *
			*				   *
			************************************



Article: 3361
Subject: Viewlogic Xilinx users
From: bierre@sasibtlc.inet.it
Date: Mon, 20 May 1996 09:17:28 -0700
Links: << >>  << T >>  << A >>
Hi'
I'm searching people that developed logic in Fpga Xilinx for exchange
information and so on...

best regards
Roberto Bonomi  e-mail: bierre@sasibtlc.inet.it


Article: 3362
Subject: Pcm data management in Fpga Xilinx
From: bierre@sasibtlc.inet.it
Date: Mon, 20 May 1996 09:34:54 -0700
Links: << >>  << T >>  << A >>
hi' I'm searching some application abuot data management pcm data with
fpga xilinx (xc52xx family).
Firstly i need information about a state machine for sincronization 
control of serial stream.
best regards
Roberto Bonomi
italy


Article: 3363
Subject: Re: Xilinx and Viewlogic
From: Andy Gulliver <andy.gulliver@crossprod.co.uk>
Date: Tue, 21 May 1996 08:47:25 +0100
Links: << >>  << T >>  << A >>
Dr Edmund Lai wrote:
> 
> I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series
> software tools.  We are having a lot of problems with ProCapture and
> Prosim running under Windows 95 in a Pentium machine with 16Mb RAM.
> 
> The "add-component" window of ProCapture has to be turned off.
> Otherwise the system will crash.  Also, we cannot get Prosim running
> at all.
> 
> Has anyone got this experience?  It has been difficult to get any
> technical support.  They simply don't reply.  We will be grateful
> for any comments and/or help.
> 
> Edmund Lai

To put it simply - the Xilinx XACT6/Pro-series package does not run 
under Win95.  Xilinx are aware of the problem.  It is apparently the 
Viewlogic stuff which can't cope (I'd have thought they'd have had 
enough time to get their act together by now!).  The last official news 
I had from tech. support was that it should be fixed by April 96.  
Unofficially, I hear that we are now looking at nearerJune/July/who 
knows :-(

We are currently evaluating the new Aldec-based package from Xilinx 
which is much cheaper and appears to have (a) much better schematic 
capture than Viewlogic (b) the version we have includes VHDL *and* a 
version of the Esperan Masterclass tutorial - oh yes, and it runs OK 
under Win95 (It does have a couple of little bugs, though....)
-- 
Regards

AndyG


Article: 3364
Subject: Re: *** The Great ESDA Shootout ***
From: jtconnor@trog.dra.hmg.gb ()
Date: 21 May 1996 11:44:30 GMT
Links: << >>  << T >>  << A >>

Can anyone comment on the usefulnes of mentor's system architect in *real*
designs?  We are just about to trial it and would appreciate anyones
feedback. Are there any others which you would recommend (or keep well
clear of?)

Thanks,


Jon.





Article: 3365
Subject: Re: Xilinx and Viewlogic
From: ft63@dial.pipex.com (Peter)
Date: Tue, 21 May 1996 12:19:32 GMT
Links: << >>  << T >>  << A >>

The Pro series Viewlogic uses a DOS extender which works only under
win3.x, not win95 or winNT.

Viewlogic have dropped the Pro series quite some time ago (didn't
sell, reportedly), but Xilinx still sell it.

Peter.


Article: 3366
Subject: INDUSTRY GADFLY: "Barbarians At tHe Gate"
From: jcooley@world.std.com (John Cooley)
Date: Tue, 21 May 1996 18:27:11 GMT
Links: << >>  << T >>  << A >>

      !!!     "It's not a BUG,                        jcooley@world.std.com
     /o o\  /  it's a FEATURE!"                              (508) 429-4357
    (  >  )
     \ - /         INDUSTRY GADFLY: "Barbarians At The Gate"
     _] [_          
                       by John Cooley, EE Times Columnist

        Holliston Poor Farm, P.O. Box 6222, Holliston, MA  01746-6222

For EDA rabble rousers, last year's DAC in San Francisco opened with all the
intrigue and suspense worthy of a John LeCarre' novel.  Prior to DAC, Steve
Schulz of the Users Society for Electronic Design Automation (USE/DA) had
been surveying EDA customers about proposed changes in the way EDA tools are
sold.  When USE/DA tried to have a panel to discuss the results, the DAC
Committee nixed the idea for fear of stealing from Ron Collett's CEO panel.
The DAC Committee also refused to list the USE/DA panel in any schedule and
expressly forbid the use of signs directing engineers to where the USE/DA
panel was.  Plus, they asked the CEOs not to attend!  At the last minute, we
were told that Collett already had two unknown users from IBM and Siemens
to represent users views on his panel, so no USE/DA people were needed.  It
looked like the "System" had succeeded in keeping the USE/DA barbarians
stopped at the DAC city gates.

Not to be outdone, the forbidden USE/DA panel went ahead to draw 200
attendees plus CEOs Wally Rhines of Mentor Graphics and Aart De Geus of
Synopsys.  Interestingly, after USE/DA's Steve Schulz presented his survey
results, we found some real working data from polling the audience: customers
preferred a model of having all tools always available to use as needed and
to pay later on a per use basis (as opposed to the PC shrink wrap sales
model.)

In contrast, at Collett's CEOs-Acting-Like-Professional-Wrestlers panel, Joe
Costello (CEO of Cadence) blurted: "We're stuck in a fixed-pie model.  Have
you seen three big dogs hovering over one bowl of dog food?  It's not a
pretty picture."  Aart De Geus (CEO of Synopsys) came back with:  "If you
think of yourself as a dog, you deserve dog food!"  Alain Hanover (CEO of
ViewLogic) said about his rebellious Chronologic: "Our founding forefathers
guaranteed us the right to life, liberty, the pursuit of happiness and the
right to sue each other."  Gerry Hsu (CEO of what was then ArcSys) took pot
shots at Cadence by describing how bureaucratic it was when he used to work
there.  Overall, this panel had the look and feel that it had been scripted
by professional wrestlers newly knowlegeable in EDA terminology.

This year the DAC Organizing Committee wanted something more driven from a
user point of view.  Yes, it makes interesting press that Cadence and Avant!
are sueing the pants off of each other, but what does this really have to do
with day-to-day ASIC designers?  Hence USE/DA struck a deal with the DAC
people to create a DAC CEO panel that's purely user driven.

Now comes your turn.  As an EDA user what would *you* like to ask the
head honchos of the EDA vending companies?  (Please e-mail them to me at
"jcooley@world.std.com")  Here's a sample of what we've gotten so far: How
will the change from pricey UNIX workstation to relatively inexpensive
PC's change the way EDA tools are bought, sold and maintained?  Have the
Verilog/VHDL Wars taught us anything?  Are EDA Vendors also becoming
merchants of on-site EDA consulting a threat to career engineers?  Is the
Internet changing the way we do business in a positive way or just a cheap
substitute for live phone support of customers in trouble?

Sure, because of the very nature of the EDA beast, we'll have *some* of this
year's EDA dirt in review, but we want most of the questions to be about
issues effecting the engineers in the trenches.  Send in those questions!

------

John Cooley runs the E-mail Synopsys Users Group (ESNUG), is president of the
User Society for Electronic Design Automation (USE/DA) & works as a contract
ASIC/FPGA designer.  He loves hearing from fellow engineers at "jcooley
@world.std.com" or (508) 429-4357.  [ Copyright 1996 CMP Publications ]


Article: 3367
Subject: Re: Xilinx and Viewlogic
From: daveb@iinet.net.au (Dave)
Date: Tue, 21 May 1996 22:39:15 GMT
Links: << >>  << T >>  << A >>
Dr Edmund Lai <E.Lai@cowan.edu.au> wrote:

>I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series
>software tools.  We are having a lot of problems with ProCapture and
>Prosim running under Windows 95 in a Pentium machine with 16Mb RAM.

>The "add-component" window of ProCapture has to be turned off.
>Otherwise the system will crash.  Also, we cannot get Prosim running
>at all.

>Has anyone got this experience?  It has been difficult to get any
>technical support.  They simply don't reply.  We will be grateful
>for any comments and/or help.

>Edmund Lai
 I was advised by EDA (the Aust. agent for Xilinx software) that the
current release is not compatible with Win-95 (only with Win-3.11).
Actually, mine does work under Win-95, provided I install QEMM, rather
than letting Microsoft run my high-memory. In practice, I use the
DOS-tools (except for Floorplanner) rather than Windows, as they seem
much simpler & faster.

--  Dave Brooks
PGP public key: finger  daveb@opera.iinet.net.au
                servers daveb@iinet.net.au
    fingerprint 20 8F 95 22 96 D6 1C 0B  3D 4D C3 D4 50 A1 C4 34



Article: 3368
Subject: [ANNOUNCEMENT] Xilinx User's Mailing List
From: ecla@world.std.com (alain arnaud)
Date: Tue, 21 May 1996 22:42:58 GMT
Links: << >>  << T >>  << A >>


Announcing the Xilinx Users mailing list!


This list is for general discussion among users of Xilinx products: FPGAs,
EPLDs and software tools.

Email your questions, bug reports, short-cuts you would like to share, why
you're using Xilinx FPGAs instead of a competitor, your likes and dislikes
about the products.

To subscribe to the list, unsubscribe from the list, or to change your 
address, send mail to xuma-request@ecla.com. 
                      ----------------------

If you sent your subscribe message to the whole list, that's okay, 
but please use the -REQUEST address next time!

To send something to the list, mail it to xuma@ecla.com. 
                                          --------------
Mention in your mail if you would like to remain anonymous.

A FAQ is being developed. Send in your suggestions on what you would like
to see in it.

DISCLAIMER: Xilinx is trademark of Xilinx Inc.
This list is not supported by Xilinx Inc, and has no direct or indirect
relationship to Xilinx.




Article: 3369
Subject: Re: Evolvable HW
From: jimtoer@idt.unit.no (Jim Toerresen)
Date: 22 May 1996 09:38:15 +0200
Links: << >>  << T >>  << A >>
Thanks to all of you who answered my request on evolvable HW:

Date: Tue, 14 May 1996 19:29:50 -0500
From: Scott Kroeger <scott.kroeger@mei.com>

Jim Toerresen wrote:
> 
> As a part the finalizing PhD we are in Norway assigned a subject 14 days in
> advance. In two weeks we shall collect available research publications and
> give an overview of the subject for the Ph.D. committee.  I have been
> assigned the very interesting subject "Evolvable Hardware".
> 
> For this topic, partial programmable FPGAs are of main interest.
> A. Thompson at Univ. of Sussex has evolved an oscillator on the new Xilinx
> XC6200. Except for him I haven't heard about any other person evolving FPGA
> configuration, that is the cells configuration is evolved by genetic
> algorithm and not a human designer. I would like to know about other
> researchers doing these kinds of experiments. Further, is there any other
> devices than XC6200 or Atmel AT6000 which are partial reconfigurable?
> 
> Please email me as soon as possible and I will summarize to this newsgroup.

I think I heard that the Pilkington architecture (Motorola MPA) is 
partially reconfigurable. I could be wrong though!

Regards,
Scott

Jim: The Web-page is a bit vague on this issue. Even though the achitecture
is interesting it will earliest be on the market this summer (it was first
mentioned in 1993).

Date: 14 May 1996 17:35:15 U
From: "Peter Alfke" <peter.alfke@xilinx.com>
Subject: Darwinian Design

                       Subject:                               Time:5:22 PM
  OFFICE MEMO          Darwinian Design                       Date:5/14/96
I think you are right, there are only two types of devices, Atmel's and Xilinx
XC6200.

Atmel's has internal 3-sate buffers, which means it cannot tolerate a random
bitstream.
XC6200 doesn't have that problem. It will never have internal contention, even
with a random bitstream. ( all metal lines are unidirectional, you can never
connect two drivers to the same interconnect line ).
I have not heard about anybody but Thompson who has investigated this peculiar
aspect. We talked about it at the Xilinx sales conference a few weeks ago.

Interesting subject, but it's still rather virgin. ( jungfrulig?)

Greetings
Peter Alfke, Xilinx Applications
( I spent 10 years in Stockholm, long ago, so I am almost Scandinavian...)


From: " (Tony Hirst)" <A.J.Hirst@open.ac.uk>
As you correctly say, adrian thompson is currently the only person evolving
configuration bitstreams for FPGA's, although Higuchi et al have reported
using FPGAs configured according to cicrcuits evolved
offline/extrinsically. 

I've written a short review of work to date on EHW, available via:

http://kmi.open.ac.uk/~monty/evoladaphwpaper.html

I also maintain a bibliography of EHW reports:

http://kmi.open.ac.uk/~monty/EHWbib.html

and a general EHW resource page -

http://kmi.open.ac.uk/~monty/EHW.html


If I can be of any help, let me know (although I'm a bit rushed at the mo.
hence the pointy nature of this message)

regards

monty
--------------------------------------------------------------------------
 All opinions etc etc...
--------------------------------

Jim: These page are very informative and good for online paper access.

 -Jim

Jim Toerresen                                # E-mail: jimtoer@idt.unit.no
Dept. of Computer Systems and Telematics     # Tel: +47-73594458 (office)
The Norwegian Institute of Technology        # Tel: +47-73886676 (home)
N-7034 Trondheim, NORWAY		     # Fax: +47-73594466 (office)

-- 

Jim Toerresen                                # E-mail: jimtoer@idt.unit.no
Dept. of Computer Systems and Telematics     # Tel: +47-73594458 (office)
The Norwegian Institute of Technology        # Tel: +47-73886676 (home)
N-7034 Trondheim, NORWAY		     # Fax: +47-73594466 (office)


         %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
         % The world is like a book, and if you never %
         %     leave home you only read one page.     %
         %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%


Article: 3370
Subject: Which FPGA is better for PCI?
From: Pedro Merino Gonzalez <merino@die.upm.es>
Date: Wed, 22 May 1996 10:37:12 +0200
Links: << >>  << T >>  << A >>
Hello, I'm new to this newsgroup and I need your help.

Here (in the Technical University of Madrid) we are involved in
the development of an interface with the PCI bus. We think that 
an FPGA will be suitable to make the interface.

Unfortunately we haven't enough experience with FPGAs and we
don't know which is more suitable (if any).

Any suggestions are welcome.


-- 
            ///                   \\\
           ( ..)                 (.. )
--------o00-(_)-00o-----------o00-(_)-00o--------------------------

Pedro Merino Gonzalez
Ph. D. Student

mail:	E.T.S.I. de Telecomunicacion
	Dpto. de Ingenieria Electronica (LSI-CAD)
	Ciudad Universitaria s/n 
	28040 Madrid (Spain)

phone:	(+34 1) 549 57 00 x 420 x 544
fax:	(+34 1) 336 73 23

e-mail:	merino@die.upm.es
___________________________________________________________________


Article: 3371
Subject: Re: Xilinx and Viewlogic
From: Antonio J A Esteves <esteves@di.uminho.pt>
Date: Wed, 22 May 1996 15:55:12 +0100
Links: << >>  << T >>  << A >>
Dr Edmund Lai wrote:

> I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series
> software tools.  We are having a lot of problems with ProCapture and
> Prosim running under Windows 95 in a Pentium machine with 16Mb RAM.
> 
> The "add-component" window of ProCapture has to be turned off.
> Otherwise the system will crash.  Also, we cannot get Prosim running
> at all.
> 
> Has anyone got this experience?  It has been difficult to get any
> technical support.  They simply don't reply.  We will be grateful
> for any comments and/or help.

We use the same packages and unfortunately we have the same problemms. 
It seems that these packages are not 32 bits compatibles. So, until
Xilinx have a 32 bits version of XACT & Proseries (!!!), we have to
run the s/w on a WIN3.11 machine. 
Xilinx must give you a correct explanation, but I think this is correct.


+-----------------------+-----------------------------------------------------+
| Antonio J. A. Esteves |                                                     |
| Dep. Informatica      | esteves@di.uminho.pt                                |
| Universidade do Minho | Tel: +351 53 604479                                 |
| Largo do Pac,o        | Fax: +351 53 604471                                 | 
| 4719 Braga Codex      | PGP: finger -l esteves@shiva.di.uminho.pt           | 
| Portugal              | WWW: http://www.di.uminho.pt/~esteves/index.html    |
+-----------------------+-----------------------------------------------------+


Article: 3372
Subject: Re: Xilinx and Viewlogic
From: garyk@svpal.svpal.org (George Noten)
Date: 22 May 1996 15:53:05 GMT
Links: << >>  << T >>  << A >>
Dr Edmund Lai (E.Lai@cowan.edu.au) wrote:
: I have purchased a copy of Xilinx XACT 6.0 and Viewlogic Pro-series
: software tools.  We are having a lot of problems with ProCapture and
: Prosim running under Windows 95 in a Pentium machine with 16Mb RAM.

 Is it PROseries or WorkView office ?  The PROseries is a product
 that runs in Windows 3.1.

: The "add-component" window of ProCapture has to be turned off.
: Otherwise the system will crash.  Also, we cannot get Prosim running
: at all.

: Has anyone got this experience?  It has been difficult to get any
: technical support.  They simply don't reply.  We will be grateful
: for any comments and/or help.

: Edmund Lai

 I had the same experience with the PROseries 6.0 in Windows environment
 but most of my problems vere related to VHDL synthesis.

	George.


Article: 3373
Subject: Re: *** The Great ESDA Shootout ***
From: Steven Bird <steve@vizef.demon.co.uk>
Date: Wed, 22 May 1996 17:00:12 +0100
Links: << >>  << T >>  << A >>
In article <4nsaau$npr@trog.dra.hmg.gb>, jtconnor@trog.dra.hmg.gb writes
>
>Can anyone comment on the usefulnes of mentor's system architect in *real*
>designs?  We are just about to trial it and would appreciate anyones
>feedback. Are there any others which you would recommend (or keep well
>clear of?)
>
>Thanks,
>
>
>Jon.
>
>
>
Jon,

I tried to email you at jtconnor@trog.dra.hmg.gb with an answer to your
question, but the mail was bounced by a machine deep inside in the MOD
(relay.mod.uk). If you are interested, mail me direct with your address,

Thanks,

Steve.

------------------------------------------------
Steven Bird

VIZEF Limited
Tel: 44 (0)1628 481571
Fax: 44 (0)1628 483902
------------------------------------------------


Article: 3374
Subject: Re: Xilinx and Viewlogic
From: David Pashley <david@fpga.demon.co.uk>
Date: Wed, 22 May 96 16:54:09 GMT
Links: << >>  << T >>  << A >>
In article <31A1750D.2754@crossprod.co.uk>
           andy.gulliver@crossprod.co.uk "Andy Gulliver" writes:

"To put it simply - the Xilinx XACT6/Pro-series package does not run 
"under Win95.  Xilinx are aware of the problem.  It is apparently the 
"Viewlogic stuff which can't cope (I'd have thought they'd have had 
"enough time to get their act together by now!).  The last official news 
"I had from tech. support was that it should be fixed by April 96.  
"Unofficially, I hear that we are now looking at nearerJune/July/who 
"knows :-(
"
"We are currently evaluating the new Aldec-based package from Xilinx 
"which is much cheaper and appears to have (a) much better schematic 
"capture than Viewlogic (b) the version we have includes VHDL *and* a 
"version of the Esperan Masterclass tutorial - oh yes, and it runs OK 
"under Win95 (It does have a couple of little bugs, though....)
"
PRO Series 6.0, to which the original poster refers, is about a year 
old, and therefore totally predates Windows95. The final version of 
PRO Series was 6.1

Late last year, Viewlogic unveiled new tools written especially for 
Windows95 and WindowsNT, called Workview Office. These new tools 
are available for those operating systems, and work very well.

These are the facts. Please beware of comparing the latest from 
"Vendor A" with something historical of unspecified product name or 
version from "Vendor B". 
                                                                
-- 
David Pashley                 <
 ------------------------  <  <  <  ---------- Email: david@fpga.demon.co.uk
| Direct Insight Ltd    <  <  <  <  >            Tel: +44 1280 700262      |
| *The EDA Source*         <  <  <               Fax: +44 1280 700577      |
 ---------------------------  <  ------------------------------------------





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