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Messages from 4475

Article: 4475
Subject: Re: XACT under WinNT is very slow
From: z80@digiservve.com (Peter - one extra v to stop junk mail)
Date: Sun, 03 Nov 1996 12:36:44 GMT
Links: << >>  << T >>  << A >>
Are you running a special driver for the Xilinx dongle? This alone
normally totally stops the s/w running under NT.

Funnily enough I find that XACT runs much *faster* under FWG3.11 than
under DOS, probably due to excessive disk cache flushing.

Peter.

>Hi All,
>
>Following the instructions offered up by Xilinx, I've gotten the command
>line portion of XACT (5.2.1) running under WinNT 3.51.  However it runs
>about 30 times slower than under pure DOS 6.22.  Has anyone else
>encountered this problem?  Better yet, has anyone else encountered a
>solution?!
>
>Thanks,
>Scott

Article: 4476
Subject: Re: XACT under WinNT is very slow
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Sun, 03 Nov 1996 07:36:12 -0600
Links: << >>  << T >>  << A >>
Peter wrote:

> Are you running a special driver for the Xilinx dongle? This alone
> normally totally stops the s/w running under NT.

Yes, I'm running the NT version of the Rainport driver.  The software
runs my design to completion, it just takes 26 minutes to place and
route a test design containing 6 CLBs.  And as you might imagine my real
design is somewhat more complex.

> Funnily enough I find that XACT runs much *faster* under FWG3.11 than
> under DOS, probably due to excessive disk cache flushing.

I didn't notice much difference between DOS6.22 and Win3.1 but both are
faster than Win95 and lots faster than WinNT.

Scott
Article: 4477
Subject: Re: XACT under WinNT is very slow
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 3 Nov 1996 17:41:09 GMT
Links: << >>  << T >>  << A >>
Hi,

Any 16 bit DOS app is going to run much slower under NT.  To run 16 bit
programs in NT, NT uses a lot of software layers to maintain the integrety
of the OS.  Even EDIT runs real real slow...

The next release of the Xilinx tools will be made to run under NT.  This
current release does run, at least all the DOS tools do.  I don't know if
the number I get is 30 times slower, it may be 2-4 times slower.

You may want to pick up the Windows NT 4.0 WS Resource Kit and follow the
tips on speeding up NT.  It has a whole chapter on optimizing NT.

Good Luck!

Austin Franklin
darkroom@ix.netcom.com

Article: 4478
Subject: Re: What is the fastest fpga for ...
From: peter@xilinx.com (Peter Alfke)
Date: Sun, 03 Nov 1996 13:05:24 -0700
Links: << >>  << T >>  << A >>
In article <55clpn$dod@news2.Belgium.EU.net>, Vincent.Himpe@ping.be
(Vincent Himpe) wrote:

> hi
> 
> I have a small problem.
> 
> I have a fairy simple circuit : a 24 bit counter with parallel load 

I forgot to explain the acid test for a TRULY UNIVERSA UNRESTRICTED
circuit of the kind you described:

Reset the 24-bit counter to 000000, then load FFFFFF on one clock edge,
then use the next clock edge to increment to 000000, and the following
clock edge to increment to 000001.

In this case, the carry logic must be built up and then be built down,
each in one single clock period. 
All sneaky tricks will fail this high-speed test, only a straightforward
carry implementation will succeed. 
But ithat takes a 24-input AND/XOR gate to drive the MSB input, and that
is tough to implement when you have only 16 ns minus the clock-to-out of
all flip-flops, minus the input set-up time of the MSB.
I'll look into an EPLD implementation using the XC7300 family.

Peter Alfke, Xilinx Applications
Article: 4479
Subject: CFP: 1997 Intl. Symp. on Physical Design, April 14-16, CA
From: ispd97@jade.cs.Virginia.EDU (1997 International Symposium on Physical Design)
Date: Sun, 3 Nov 1996 21:48:50 GMT
Links: << >>  << T >>  << A >>
=============================================================================

                             Call for Papers

               1997 International Symposium on Physical Design
                             April 14-16, 1997
                          Napa Valley, California

              Sponsored by the ACM SIGDA in cooperation with 
                   IEEE Circuits and Systems Society

   The International Symposium on Physical Design provides a forum to
exchange ideas and promote research on critical areas related to the
physical design of VLSI systems.  All aspects of physical design, from
interactions with behavior- and logic-level synthesis, to back-end
performance analysis and verification, are within the scope of the
Symposium.  Target domains include semi-custom and full-custom IC, MCM
and FPGA based systems.
 
   The Symposium is an outgrowth of the ACM/SIGDA Physical Design
Workshop.  Following its five predecessors, the symposium will
highlight key new directions and leading-edge theoretical and
experimental contributions to the field. Accepted papers will be
published by ACM Press in the Symposium proceedings. Topics of
interest include but are not limited to:

       1. Management of design data and constraints 
       2. Interactions with behavior-level synthesis flows 
       3. Interactions with logic-level (re-)synthesis flows 
       4. Analysis and management of power dissipation 
       5. Techniques for high-performance design 
       6. Floorplanning and building-block assembly 
       7. Estimation and point-tool modeling 
       8. Partitioning, placement and routing 
       9. Special structures for clock, power, or test
      10. Compaction and layout verification
      11. Performance analysis and physical verification 
      12. Physical design for manufacturability and yield 
      13. Mixed-signal and system-level issues.
      
IMPORTANT DATES:    Submission deadline:              December 20, 1996
                    Acceptance notification:          February 1, 1997
                    Camera-ready (6 page limit) due:  March 1, 1997

SUBMISSION OF PAPERS:

    Authors should submit full-length, original, unpublished papers 
    (maximum 20 pages double spaced) along with an abstract of at most 
    200 words and contact author information (name, street/mailing address, 
    telephone/fax, e-mail).

    Electronic submission via uuencoded e-mail is encouraged (single 
    postscript file, formatted for 8 1/2" x 11" paper, compressed with 
    Unix "compress" or "gzip''). Email to:

                        ispd97@ece.nwu.edu

    Alternatively, send ten (10) copies of the paper to:

                        Prof. Majid Sarrafzadeh
                        Technical Program Chair, ISPD-97
                        Dept. of ECE, Northwestern University
                        2145 Sheridan Road, Evanston, IL 60208 USA
                        Tel 847-491-7378 / Fax 847-467-4144 

SYMPOSIUM INFORMATION:

    To obtain information regarding the Symposium or to be added to the
    Symposium mailing list, please send e-mail to ispd97@cs.virginia.edu. 
    Information can also be found on the ISPD-97 web page:   

                         http://www.cs.virginia.edu/~ispd97/

SYMPOSIUM ORGANIZATION:

General Chair:               A. B. Kahng (UCLA and Cadence)
Past Chair:                  G. Robins (Virginia)
Steering Committee:          J. Cohoon (Virginia), S. Dasgupta (Sematech),
                             S. M. Kang (Illinois), B. Preas (Xerox PARC) 
Program Chair:               M. Sarrafzadeh (Northwestern)
Keynote Address:             T. C. Hu (UC San Diego) & E. S. Kuh (UC Berkeley)
Special Address:             R. Camposano (Synopsys)
Publicity Chair:             M. J. Alexander (Washington State)
Local Arrangements Chair:    J. Lillis (UC Berkeley)
Technical Program Committee: C. K. Cheng (UC San Diego)
                             W. W.-M. Dai (UC Santa Cruz) 
                             J. Frankle (Xilinx) 
                             D. D. Hill (Synopsys) 
                             M. A. B. Jackson (Motorola) 
                             J. A. G. Jess (Eindhoven)  
                             Y.-L. Lin (Tsing Hua) 
                             C. L. Liu (Illinois)
                             M. Marek-Sadowska (UC Santa Barbara)
                             M. Sarrafzadeh (Northwestern)
                             C. Sechen (Washington) 
                             K. Takamizawa (NEC)
                             M. Wiesel (Intel) 
                             D. F. Wong (Texas-Austin) 
                             E. Yoffa (IBM)

=============================================================================

Article: 4480
Subject: FPGA references for beginner?
From: aet@murlibobo.cs.mu.OZ.AU (Bert THOMPSON)
Date: 4 Nov 1996 08:04:57 GMT
Links: << >>  << T >>  << A >>
Hi,

Can anyone suggest references for a beginner who wants to learn
about FPGAs? I'm an Elec Eng undergrad.

Please email me --- I will summarise should there be interest.

Many thanks,
Bert
---------------------------------------------------------------------------
Bert Thompson                                               aet@cs.mu.oz.au
---------------------------------------------------------------------------
Article: 4481
Subject: Info on FPGA Internal Architecture/ Programming
From: "Craig Slorach" <craigs@elec.gla.ac.uk>
Date: 4 Nov 1996 11:17:10 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm looking for info on any FPGA's currently available where the internal
architecture and programming information is known (ie. where I can write to
programming registers myself instead of having to use manufacturers own
tools).

Does anyone know of such an FPGA (from what I've found in the data books so
far, they talk only about the tools supplied by vendors to produce the
programming code).

Reply by e-mail to craigs@elec.gla.ac.uk  would be preferred.

Best regards

Craig Slorach

Article: 4482
Subject: ORCA Configuration
From: Aage Farstad <aage.farstad@ffi.no>
Date: Mon, 04 Nov 1996 17:36:04 +0100
Links: << >>  << T >>  << A >>
Hi ORCA friends,

Has anybody encountered problems with two consecutive configurations of
the ATT2C26.? In our case it seems like, after a successful first time
configuration, that the device's I/Os are activated somewhere in the
middle of a second one. We made a testcircuit consisting of the TSALL
component only, and this time we were able to reconfigure the device
repeatedly. BTW, the device is programmed in the serial slave mode from
an on-board uP using the *.rbt option. Does anbode have a hint?

Best regards 

Aage Farstad
Article: 4483
Subject: Re: What is the fastest fpga for ...
From: husby@fnal.gov (Don Husby)
Date: 4 Nov 1996 17:11:25 GMT
Links: << >>  << T >>  << A >>

Lucent ORCA chips can probably do the job without too much
fancy logic.

From their timing specs I get a cycle time for a 24-bit loadable
counter of about 15ns for the 2C00a-4 speed chips.  The -3 chips
would give an 18ns cycle.

This is probably the limiting circuit.  The comparator and reset
logic can be easily pipelined.






Article: 4484
Subject: Re: Multipliers on Xilinx FPGAs
From: Simon <106072.1620@CompuServe.COM>
Date: 4 Nov 1996 17:22:08 GMT
Links: << >>  << T >>  << A >>
The Altera apps note will be different to the Xilinx one because 
Xilinx 4000 parts have DISTRIBUTED RAM which is much more 
suitable for generating look-up table based multipliers. Also, 
because the RAM is DISTRIBUTED, it's right where you need it to 
be (i.e. right where you want your multiplier) and hence it will 
be faster. I seriously suggest waiting for the Xilinx Apps note 
before making a decision as using DISTRIBUTED RAM and partial 
products (hence smaller look-up tables) makes for faster, more 
compact multipliers.

-- 
Simon
106072.1620@Compuserve.com
These opinions are entirely my own and, in keeping with the 
true nature of opinions, are not always valid or rational.
Article: 4485
Subject: Re: FPGA references for beginner?
From: singhg@lattice.com (Amarpreet Singh Geadhoke)
Date: Mon, 4 Nov 1996 17:44:41 GMT
Links: << >>  << T >>  << A >>

In article <55k839$ljd@mulga.cs.mu.OZ.AU>, aet@murlibobo.cs.mu.OZ.AU (Bert THOMPSON) writes:
CHi,
C
CCan anyone suggest references for a beginner who wants to learn
Cabout FPGAs? I'm an Elec Eng undergrad.
C
CPlease email me --- I will summarise should there be interest.
C
CMany thanks,
CBert
C---------------------------------------------------------------------------
CBert Thompson                                               aet@cs.mu.oz.au
C---------------------------------------------------------------------------



Article: 4486
Subject: Fastest way to get started??
From: bschwabe@ionet.net (Beau Schwabe)
Date: 5 Nov 1996 05:09:39 GMT
Links: << >>  << T >>  << A >>
Hello,

	I work at a research center, and currently use PIC uP's.
       What I want to do expand our knowledge in FPGA or FPAA...
       ...This topic seems to be a "meat market" between 
       manufacturers and I would simply like some "real world"
       information. ie: What kind of setup can I get for $5,000.
       What have you made your FPxx do? What can it do?-impress me

				Beau Schwabe
				bschwabe@ionet.net
     


Article: 4487
Subject: Re: XACT under WinNT is very slow
From: Piet du Toit <pdtoit@csir.co.za>
Date: 5 Nov 1996 07:12:05 GMT
Links: << >>  << T >>  << A >>
Scott Kroeger <Scott.Kroeger@mail.mei.com> writes: > Hi All,
> 
> Following the instructions offered up by Xilinx, I've gotten the command
> line portion of XACT (5.2.1) running under WinNT 3.51.  However it runs
> about 30 times slower than under pure DOS 6.22.  Has anyone else
> encountered this problem?  Better yet, has anyone else encountered a
> solution?!
> 
> Thanks,
> Scott

I have used the XACT 5.2X software on Windows NT 4.0. 
The Place and Routing of the device was fast compared to Win 95. 

Wir2Xnf was very fast on NT 4.0 Beta (5 to 10 times faster that on WIN 95)
On the final release of NT 4.0, Wir2Xnf was very slow. It does a lot of
disk swopping. It sounds as if the hard drive is going to crash. I would
also like know to what the reason for the change in Wir2Xnf behaviour is.

Hope this helps
Piet
Article: 4488
Subject: UART FOR FPGAS
From: Jens Weigle <weigle@tc-wedel.de>
Date: Tue, 05 Nov 1996 09:26:26 +0100
Links: << >>  << T >>  << A >>
Hi!

I need a RS-232 interface for XILINX FPGAS.

Who can help me ?

I need a ready and tested UART-DESIGN for quick implementation.
-- 
---
Mit freundlichen Gruessen
Jens Weigle, Dept. T62
=======================================================================
ESW, Extel Systems Wedel
Gesellschaft fuer Ausruestung mbH  | Phone : (+49) 4103 60-3664
Industriestr. 23-33                | FAX   : (+49) 4103 60-4513
D-22880 Wedel                      | e-mail: weigle@tc-wedel.de
=======================================================================
Article: 4489
Subject: recent FPGA boards ?
From: s1012057@hdw1ss25.u-aizu.ac.jp (Kimiko Nemoto)
Date: 05 Nov 1996 09:54:42 GMT
Links: << >>  << T >>  << A >>


Dear Netters:

Does anyone know some good pointers on very recent FPGA boards ?
(commercial products)

I need around 100,000 available gates for my designs (several FPGA
chips on the same board).

regards,

Kimiko

-- 
ܴ
Article: 4490
Subject: Re: XACT under WinNT is very slow
From: Scott Kroeger <Scott.Kroeger@mei.com>
Date: Tue, 05 Nov 1996 08:59:35 -0600
Links: << >>  << T >>  << A >>
Piet du Toit wrote:
> 
> Scott Kroeger <Scott.Kroeger@mail.mei.com> writes: > Hi All,
> >
> > Following the instructions offered up by Xilinx, I've gotten the command
> > line portion of XACT (5.2.1) running under WinNT 3.51.  However it runs
> > about 30 times slower than under pure DOS 6.22.  Has anyone else
> > encountered this problem?  Better yet, has anyone else encountered a
> > solution?!
> >
> > Thanks,
> > Scott
> 
> I have used the XACT 5.2X software on Windows NT 4.0.
> The Place and Routing of the device was fast compared to Win 95.
> 
> Wir2Xnf was very fast on NT 4.0 Beta (5 to 10 times faster that on WIN 95)
> On the final release of NT 4.0, Wir2Xnf was very slow. It does a lot of
> disk swopping. It sounds as if the hard drive is going to crash. I would
> also like know to what the reason for the change in Wir2Xnf behaviour is.

Piet,

Edit _DEFAULT.PIF in your WINNT(40?) directory.  If you haven't
allocated enough XMS memory the MS-DOS command prompt the tools will
swap excessively.  Under NT3.51 the most you can allocate is 16Megs,
which is insufficient for large designs.  The factory default is 1Meg,
which slowed things so much that PPR took all night just to open my
input file!  To let NT automatically allocate as much XMS memory as
needed, replace the default 1024KB with -1.

Win95 appears nearly as fast as DOS6.22 to me.

Regards,
Scott
Article: 4491
Subject: Re: Info on FPGA Internal Architecture/ Programming
From: rick@camden.algor.co.uk (Rick Filipkiewicz)
Date: 5 Nov 1996 18:14:12 GMT
Links: << >>  << T >>  << A >>
Craig Slorach (craigs@elec.gla.ac.uk) wrote:
: Hi,

: I'm looking for info on any FPGA's currently available where the internal
: architecture and programming information is known (ie. where I can write to
: programming registers myself instead of having to use manufacturers own
: tools).

: Does anyone know of such an FPGA (from what I've found in the data books so
: far, they talk only about the tools supplied by vendors to produce the
: programming code).

: Reply by e-mail to craigs@elec.gla.ac.uk  would be preferred.

: Best regards

: Craig Slorach


I think that you are currently out of luck here. As far as I'm aware
all FPGA manufacturers still seem to treat this info as a dark
secret. This probably stems from the early days of FPGAs where the
market was so small that the vendors thought the only way to make any
money was to charge the earth for highly vendor specific tools. The
prices of the tools have dropped sharply but they still haven't opened
up their architecures completely to allow 3rd party tool sets.

 _________________________________________________________________________

 Dr. Richard Filipkiewicz 	phone: +44 171 700 3301
 Algorithmics Ltd.		fax: +44 171 700 3400
 3 Drayton Park			email: rick@algor.co.uk
 London N5 1NU
 England
Article: 4492
Subject: Just try this, it will work
From: sbolting@nemonet.com (Stephen Boltinghouse)
Date: Tue, 5 Nov 1996 18:44:01 GMT
Links: << >>  << T >>  << A >>

Take five minutes to read this and it WILL change your life.
 
 The Internet has grown tremendously. It doubles in size every 4 months.
 think about it. You see those 'Make.Money.Fast' posts more and more.
 That's ... because it WORKS !  So I thought, all those new users might
 make it work. And I decided to try it out, a few months ago.  Besides,
 whats $5.00, I spend more than that in the morning on my way to work on
 coffee and cigs for the day. So I sent in my money and posted.
 Everyone was calling it a scam, but there are SO many new users from
 AOL, Netcom, etc. they will join in and make it work for you.

 Well, two weeks later, I began recieving bucks in the mail!  I couldn't
 believe it! Not just a little, I mean big bucks!  At first only a few
 hundred dollars, then a week later, a couple of thousand, then BOOM. By
 the end of the fourth week, I had recieved nearly $47,000.00. It came
 from all over the world. And every bit of it perfectly legal and on the
 up and up. I've been able to pay off all my bills and still had enough
 left over for a nice vacation for me and my family.

 Not only does it work for me, it works for other folks as well.  Markus
 Valppu says he made $57,883 in four weeks. Dave Manning claims he made
 $53,664 in the same amount of time. Dan Shepstone says it was only
 $17,000 for him. Do I know these folks? No, but when I read how they
 say they did it, it made sense to me. Enough sense that I'm taking a
 similar chance with $5 of my own bucks. Not a big chance, I admit--but
 one with incredible potential, because $5 is all anyone ever invests in
 this system. Period. That's all Markus, Dave, or Dan invested, yet
 their $5 netted them tens of thousands of dollars each, in a safe,
 legal, completely legitimate way. Here's how it works in 3 easy steps:

STEP 1.

Invest your $5 by writing your name and address on five seperate pieces
of paper along with the words: "PLEASE ADD ME TO YOUR MAILING LIST." (In
this way, you're not just sending a dollar to someone; you're paying for
a legitimate service.) Fold a $1 bill, money order, or bank note inside
each paper, and mail them by standard U. S. Mail to the following five
addresses:

 1-  Fern Suarez
     Mallorca 112
     Hato Rey, P.R., USA, 00917
 
 2-  Philippe
     2104 De Mexico
     Chomedey, Laval
     Quebec, Canada     
     H7M 3C6    
     
 3-  Natalie Jansen
     Lancveldlaan 18
     5671 CN Nuenen
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 4-  Chad Collier
     2785 Cold Springs Rd. #49
     Placerville, CA  95667  

 5-  Steve Boltinghouse
     1009 Bird St.
     Hannibal, MO  63401

STEP 2.

    Now remove the top name from the list, and move the
    other names up.This way, #5 becomes #4 and so on.
    Put your name in as the fifth one on the list.


STEP 3.

    Post the article to at least 250 newsgroups. There are at
    least 19000 newsgroups at any given moment in time.
    Try posting to as many newsgroups as you can. Remember
    the more groups you post to, the more people will see your
    article and send you cash!


STEP 4.

    You are now in business for yourself, and should start seeing
    returns within 7 to 14 days! Remember, the Internet is new
    and huge. There is no way you can lose.
 
    Now here is how and why this system works:
 
    Out of every block of 250 posts I made, I got back 5 responses.
    Yes, thats right,only 5. You make $5.00 in cash, not checks or
    money orders, but real cash with your name at #5.
 
    Each additional person who sent you $1.00 now also makes 250
    additional postings with your name at #4, 1000 postings. On
    average then, 50 people will send you $1.00 with your name at
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    Now these 50 new people will make 250 postings each with your
    name at #3 or 10,000 postings. Average return, 500 people= $500.
    They make 250 postings each with your name at #2= 100,000
    postings=5000 returns at $1.00 each=$5,000.00 in cash!
 
    Finally, 5,000 people make 250 postings each with your name at
    #1 and you get a return of $60,000 before your name drops off
    the list.And that's only if everyone down the line makes only 250
    postings each! Your total income for this one cycle is $55,000.
 
    From time to time when you see your name is no longer on the list,
    you take the latest posting you can find and start all over again.

		The end result depends on you. You must follow through
		and repost this article everywhere you can think of.
		The more  postings you  make, the more cash ends up in
		your mailbox. It's too easy and too cheap to pass up!!!

    So thats it. Pretty simple sounding stuff, huh? But believe me, it
    works. There are millions of people surfing the net every day, all
    day, all over the world. And 100,000 new people get on the net
    every day. You know that, you've seen the stories in the paper.
    So, my friend, read and follow the simple instructions and play
    fair. Thats the key, and thats all there is to it. Print this out
    right now so you can refer back to this article easily. Try to keep
    an eye on all the postings you made to make sure everyone is
    playing fairly. You know where your name should be.

    If you're really not sure or still think this can't be
    for real, then don't do it. But please print this article and pass it
    along to someone you know who really needs the bucks, and see
    what happens.


    REMEMBER....HONESTY IS THE BEST POLICY.YOU DON'T
    NEED TO CHEAT THE BASIC IDEA TO MAKE THE BUCKS!
    GOOD LUCK TO ALL, AND PLEASE PLAY FAIR AND YOU WILL
    WIN AND MAKE SOME REAL INSTANT FREE CASH!

*** By the way, if you try to deceive people by posting the messages
with your name in the list and not sending the bucks to the people
already included, you will not get much. I know someone who did this
and only got about $150 (and that's after two months). Then he sent
the 5 bills, people added him to their lists, and in 4-5 weeks he had
over $10,000!

		TRY IT AND YOU'LL BE HAPPY!!!  :o) !!!!!!!!!!
Article: 4493
Subject: Re: UART FOR FPGAS
From: Peter Alfke <peter@xilinx.com>
Date: Tue, 05 Nov 1996 16:03:51 -0700
Links: << >>  << T >>  << A >>
Here is the reason why there are no UART designs in the libraries:
UARTs were invented more than 20 years ago by semiconductor
manufacturers like Intel and NSC and Motorola and Zilog, who wanted to
sell one standard device to many customers with different requirements (
word length, number of stop bits, parity, etc ). So they made all these
parameters programmable, the Zilog SIO then threw in a FIFO and so on.

Implementing the functionality in an FPGA for any one useris trivial,
but implementing all these programming registers is very inefficient,
and is inherently unnecessary in an FPGA. So, we should not have one
UART in our library, but dozens, one for each programming option.
Otherwise our users would laugh about the inefficiency of the FPGA
implementation. Using four CLBs for an 8-bit control register that gets
set once and for all, is not an efficient use of an FPGA.

Peter Alfke, Xilinx Applications
Article: 4494
Subject: Re: UART FOR FPGAS
From: Brad Taylor <blt@emf.net>
Date: Tue, 05 Nov 1996 17:00:34 -0800
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> 
> Here is the reason why there are no UART designs in the libraries:
> UARTs were invented more than 20 years ago by semiconductor
> manufacturers like Intel and NSC and Motorola and Zilog, who wanted to
> sell one standard device to many customers with different requirements (
> word length, number of stop bits, parity, etc ). So they made all these
> parameters programmable, the Zilog SIO then threw in a FIFO and so on.
> 
> Implementing the functionality in an FPGA for any one useris trivial,
> but implementing all these programming registers is very inefficient,
> and is inherently unnecessary in an FPGA. So, we should not have one
> UART in our library, but dozens, one for each programming option.
> Otherwise our users would laugh about the inefficiency of the FPGA
> implementation. Using four CLBs for an 8-bit control register that gets
> set once and for all, is not an efficient use of an FPGA.
> 
> Peter Alfke, Xilinx Applications


Even so, it seems silly to build and debug yet another 8 bit, no parity,
1 stop bit UART.  Such things are not trivial and I would really rather
buy one than build one.  It seems to me that this is the case for
virtually every high level function I would like to implement.  This
problem goes right to the heart of why we are still reinventing the
wheel.  Well actually an 8 bit loadable wheel with a 4 deep FIFO for
reads ... and it's really tight for area, but it only need to run at 1
MHz. (by the way I need it in an obsolete version of viewlogic). 

What I really need is not 2^gazillion different UART macros, but a UART
generator.  Same with multipliers, adders etc.  Of course, if you built
one, it probably wouldn't give me exactly what I need so why bother. On
the other hand, I could then blame the macro generator for generating
what I asked for and not what I wanted.

-
Brad Taylor

Article: 4495
Subject: Actel Designer and Win NT 4.0
From: jmarden@world.std.com (Jeffrey C. Marden)
Date: Wed, 6 Nov 1996 02:45:40 GMT
Links: << >>  << T >>  << A >>
Hello:

Is anybody using the Actel Designer tools with Windows NT v4.0

Thanks,

Jeff Marden
jmarden@world.std.com

Article: 4496
Subject: Re: What is the fastest fpga for ...
From: Lance Gin <c43lyg@dso.hac.com>
Date: Tue, 05 Nov 1996 19:16:15 -0800
Links: << >>  << T >>  << A >>
Austin Franklin wrote:

> You say you're using synthesis?  Did you try doing the design in
> schematics?

exactly my thought! i'm using mentor's autologic II to target VHDL to a
xilinx 4025e. earlier this summer, i was dissapointed to discover that
counter inference is not that easy to attain. this means that autologic
will normally not build a xilinx counter for you using any special
architectural primitives or even macros. at best, al2 will use an xblox
inc/dec rpm as part of the counter.

i'd be surprised if any synth tool can infer something like a cc16ce
straight away from your code. fortunately, many synth tools will let
you do a target component instantiation in your hdl code. but that's
like using a schematic.  :)

-- 
_______________________________________________________________________

Lance Gin                                         "off the keyboard
Delco Systems - GM Hughes Electronics              over the bridge,
OFC: 805.961.7567  FAX: 805.961.7739               through the gateway,
C43LYG@dso.hac.com                                 nothing but NET!"
_______________________________________________________________________
Article: 4497
Subject: Re: What is the fastest fpga for ...
From: erik@blender (Matthew Harding)
Date: 6 Nov 1996 05:29:38 GMT
Links: << >>  << T >>  << A >>
Vincent Himpe (Vincent.Himpe@ping.be) wrote:
: hi

: I have a small problem.

: I have a fairy simple circuit : a 24 bit counter with parallel load  
: The counter is hooked to a comparator which can either reset the counter  , or
: make it load a new value.


I'd agree with what others have been saying: try using a prescaler.

The other possibility is to use CPLD devices. They don't have anywhere near
as much logic in them but for small fast designs, they are ideal.

I've been using Lattice ispLSI 2064 devices for about a year now. They delay
from flip-flop to flip-flop within the device can be as low a 5ns.

Hope this helps,
Erik

======================================================
Erik de Castro Lopo
erikd@zip.com.au
======================================================
Article: 4498
Subject: PCB Handling of chip packages greater than 100 pins?
From: Manolis Stratakis <strataki@ics.forth.gr>
Date: Wed, 06 Nov 1996 09:26:38 +0200
Links: << >>  << T >>  << A >>
Hello,

        We are using Allegro to make several complicated PCBs for
our designs. We use extensively Xilinx FPGAs and other chips but up
to now we take care our chips not to exceed ~ 100 pins. Actually when
the package comes in any PGA we can handle it easily with our layout
software and our lab's facilities. But when it comes to greater chip
packages we do not have the necessary experience.

        Are there any pointers to info about the handling of these
monster chips? How about the PCB manufacturers, do they normally support
them? How does the package choice affect the total cost of the PCB?
It is true that at least for the Xilinx FPGAs the PGA packages tend to
be a lot more expensive than the respective PLCCs. I would expect this
to be especially true with the more complicated packages.

        Also are there any converter sockets available that would
convert a xxx (xxx = a difficult to handle) package to PGA? 

        Please mail cc: strataki@ics.forth.gr

        Thank you in advance,

        Manolis Stratakis.

_______________________________________________________________
Manolis Stratakis,                E-mail: strataki@ics.forth.gr
Digital Design Engineer,                     Tel: +30-81-391669
VLSI Design & Computer Architecture Lab,     Fax: +30-81-391609
Institute of Computer Science (ICS),
Foundation for Research and Technology - Hellas (FORTH),
P.O.Box 1385, S.T.E.P.-C,  Heraklio,  Crete,  GR 71-110 GREECE.
_______ Home Page: http://www.ics.forth.gr/~strataki __________
Article: 4499
Subject: Re: XACT under WinNT is very slow
From: no.bulk.mailing@thanks.com (Peter)
Date: Wed, 06 Nov 1996 10:51:02 GMT
Links: << >>  << T >>  << A >>


>Yes, I'm running the NT version of the Rainport driver.

OK.

> The software
>runs my design to completion, it just takes 26 minutes to place and
>route a test design containing 6 CLBs.  And as you might imagine my real
>design is somewhat more complex.

Curious. I assume that, as in most XACT runs, 90+% of the time is
being spent in PPR. This program does not use the disk, or indeed the
API. It is purely a CPU-intensive process. So I would check the DOS
box priority, or whatever governs how much CPU time that app gets
under NT.


Peter.

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