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Messages from 4450

Article: 4450
Subject: Anyone experience Altera 10k
From: John McDougall <johnm@newbridge.com>
Date: Wed, 30 Oct 1996 14:59:41 -0500
Links: << >>  << T >>  << A >>
I'm looking into doing a large fpga design which would require a
Xilinx 4010E device. (I'm familiar with Xilinx). We've had good luck
with using ORCAs also. We have been able to push the ORCAs at faster
speeds than xilinxs.

The Altera 10K50 looks like a nice part and great price. I haven't been
able to find anyone with experience on this or other 10K devices. Are
they for real? Fast? What sort of routability?
Article: 4451
Subject: Altera & Verilog
From: williamv@pacbell.net (William Vollrath)
Date: Wed, 30 Oct 1996 14:02:33 -0800
Links: << >>  << T >>  << A >>
Would anyone care to comment on the use of Altera with Verilog (or VHDL)?

I am specifically curious about performance.  Altera's AHDL, when 
compiled, can take advantage of things like carry chains... I assume 
that if I start with Verilog design entry that I cannot specify that 
the carry chains get used.

I know that there are 3rd party products that allow me to code in 
VHDL and still get carry chains... what about Verilog?

Does anyone have any comments about synthesizing from Verilog 
without using carry chains?  Is the performance hit by not using 
them excessive?

Thanks for any comments!

---
William Vollrath, LOTS Technology
Article: 4452
Subject: Re: VHDL for Xilinx designs?
From: espsys@aol.com (ESPSys)
Date: 30 Oct 1996 21:10:11 -0500
Links: << >>  << T >>  << A >>
>I'd like to vote too:
> I use schematics (Viewlogic), but have a tool that lets me put
>logic equations right on the schematic page.  For me, this is the
>best of both worlds since I can see data paths and textual
>representation of my random logic all together.  It also gives me
>good control of mapping and signal naming.  My hope is that eventually
>this will be a standard.
>
>  Strangely enough, I sometimes use the logic equations instead of
>a schematic symbol to specify a data path.

What is the tool that you use to add text to your Viewlogic designs?  That
sounds like a great idea.  My own personal opinion is that a schematic/HDL
hybrid design can make the design easier to understand and follow (e.g.
schematic for data flow, HDL for state machines).

Ed.
espsys@aol.com
Article: 4453
Subject: FREE ELECTRONICS DIRECTORY
From: tpeterson@netins.net (Todd Peterson)
Date: 31 Oct 1996 03:24:53 GMT
Links: << >>  << T >>  << A >>
Greetings!

E-LAB Digital Engineering, Inc. is pleased to make freely available our new
Electronics Internet Resource Directory!

This directory is a collection of many internet sites of use to
electronics builders, designers, and engineers.  It is divided into
40 categories, with each category containing many hot-links to companies
and/ or web pages containing information on topics from Compilers to
Code Examples to Components Distributors.

The directory is available at http://www.netins.net/showcase/elab
You WILL want to set a bookmark!

We also invite you to check out our products, such as our new line of
integrated circuits for embedded design.

Thanks,

Todd Peterson
E-LAB Digital Engineering, Inc.




Article: 4454
Subject: Re: Altera & Verilog
From: Steve Wiseman <steve@sj.co.uk>
Date: Thu, 31 Oct 1996 07:34:33 +0000
Links: << >>  << T >>  << A >>
William Vollrath wrote:
> 
> Would anyone care to comment on the use of Altera with Verilog (or VHDL)?

Using the Altera-supplied toolset (Magnum?), it all works. Design clock
speeds of 32M are easy, routing takes about 5-10 minutes for a Flex
8452, including synthesis time on a P90. The simulator is a simple
post-synthesis timing waveform driven thing, useful in its own way, but
you also get a timing VHDL file (.vho) to throw at modeltec, so all your
original test vectors still work. 
> 
> I am specifically curious about performance.  Altera's AHDL, when
> compiled, can take advantage of things like carry chains... I assume
> that if I start with Verilog design entry that I cannot specify that
> the carry chains get used.

Their supplied VHDL tools make good use of carry chain. (nipping into
the floorplan editor confirms this). While I have no doubt that a smart
and patient human can beat the tools on small lumps of the design, I'm
happy with the results. Altera don't seem to sell a Verilog option, but
do interface to other peoples tools. 
> 
> I know that there are 3rd party products that allow me to code in
> VHDL and still get carry chains... what about Verilog?

To be honest, call them. The UK team is friendly, competent and fast. I
don't know about your area.  

> Does anyone have any comments about synthesizing from Verilog
> without using carry chains?  Is the performance hit by not using
> them excessive?

Yup. It's quite bad news, speed hit of about 30%, if I remember right,
but I only turned off that button once. 

  Steve.
-- 
Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK
Desk +44 1223 578524 (Fax 578525) Group +44 1223 578518   steve@sj.co.uk
Article: 4455
Subject: Weird pre-config VCC-GND short in Altera or Xilinx
From: Steve Wiseman <steve@sj.co.uk>
Date: Thu, 31 Oct 1996 07:40:08 +0000
Links: << >>  << T >>  << A >>
An odd problem has appeared....

I have a plug-in card for a set top box. On it are 
1*Xilinx XC3164A
1*Altera Flex 8452, with 128K*8 fast SRAM hung off the side
16Mbit Flash
SEEQ ATM25 93C95 line driver / receiver. 
and a bunch of stuff to provide RS232. 

On powering up the host, sometimes the card takes enough current to kill
the PSU, which ought to have at least 4 amps spare at 5V, more during
spin-up. The PSU goes into thermal shutdown, so nothing gets hot (damn
it). 
When the card works, it works fine. The over-power symptom cuts in _way_
before the devices are configured, in fact while reset is asserted on
the host's CPU (The FPGAs are both booted from the host)
  This seems to be related to the dV/dT on the +5V. Anyone have any
ideas? This is getting tiresome. 


  Cheers,
     Steve

-- 
Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK
Desk +44 1223 578524 (Fax 578525) Group +44 1223 578518   steve@sj.co.uk
Article: 4456
Subject: Re: VHDL for Xilinx designs?
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 31 Oct 1996 14:00:49 GMT
Links: << >>  << T >>  << A >>
> What is the tool that you use to add text to your Viewlogic designs? 

A Viewlogic schematic symbol will allow you to have anything underlying it.
 You specify it as a type module (instead of type composite) and when you
run wir2xnf it doesn't go into the symbol.  Then you need some tool (like
any of the synthesizers that provide Xilinx output, XAbel, Synopsys etc...)
that puts out a .xnf file. When you run xnfmerge, it just looks for .xnf
files, and provided the signal names match up (and it will tell you if they
don't!) you're set!  One thing you need to be aware of is that you have to
specify inverted sense signal names in a textual manner, ie. not use the
invert signal sense command in Viewlogic, no bars over signal names.  I use
BLA_L for my inverted signal sense names.  You can still keep the bubble on
the pins of the symbols because they are only annotation anyway.

If you use VHDL under under the symbol, and you add some attributes to the
symbol, such as PINORDER (and some others I can't think of right now) you
can so unit delay simulation to the entire design compiling it.  This is a
real nice feature.

Viewlogic does have a new FPGA Synthesizer with their Workview Office
product.  I haven't tried it yet, but when I do (if I do) I'll post my
impressions.

Austin Franklin
darkroom@ix.netcom.com

Article: 4457
Subject: Re: Altera & Verilog
From: "Kevin D. Drucker" <kdrucker@hns.com>
Date: Thu, 31 Oct 1996 09:48:47 -0500
Links: << >>  << T >>  << A >>
Steve Wiseman wrote:
> Would anyone care to comment on the use of Altera with Verilog (or VHDL)?

I have used Altera with Verilog and Synopsys Design Compiler/FPGA
Compiler.

The biggest complaint I have  is getting your setup correct the first
time.
The documentation in the Synopsys Interface Guide is poor and sometimes
just
plain incorrect.

> I am specifically curious about performance.  Altera's AHDL, when
> compiled, can take advantage of things like carry chains... I assume
> that if I start with Verilog design entry that I cannot specify that
> the carry chains get used.

If you utilize the Design Ware libraries that Altera supplies for DC/FC
then you can make use of the carry chains.  However, without the DC/FC
libraries (using the standard Synopsys components) you won't get carry
chains.
A good way to see if your libraries are set up correctly is to quickly
synthesize
a counter and see if the carry chains get implemented.

> I know that there are 3rd party products that allow me to code in
> VHDL and still get carry chains... what about Verilog?

See previous comments.

> Does anyone have any comments about synthesizing from Verilog
> without using carry chains?  Is the performance hit by not using
> them excessive?

Significant timing penalty!
-- 
-Kevin

Kevin D. Drucker        |  email: kdrucker@hns.com
Member Technical Staff, |  work:  (301) 601-4167  
Hardware Development    |  fax:   (301) 601-4275  
Hughes Network Systems  |
Article: 4458
Subject: Re: Weird pre-config VCC-GND short in Altera or Xilinx
From: Marc Boulais <marc_boulais@nt.com>
Date: Thu, 31 Oct 1996 15:51:42 -0500
Links: << >>  << T >>  << A >>
Steve Wiseman wrote:
> 
> An odd problem has appeared....
> 
> I have a plug-in card for a set top box. On it are
> 1*Xilinx XC3164A
> 1*Altera Flex 8452, with 128K*8 fast SRAM hung off the side
> 16Mbit Flash
> SEEQ ATM25 93C95 line driver / receiver.
> and a bunch of stuff to provide RS232.
> 
> On powering up the host, sometimes the card takes enough current to kill
> the PSU, which ought to have at least 4 amps spare at 5V, more during
> spin-up. The PSU goes into thermal shutdown, so nothing gets hot (damn
> it).
> When the card works, it works fine. The over-power symptom cuts in _way_
> before the devices are configured, in fact while reset is asserted on
> the host's CPU (The FPGAs are both booted from the host)
>   This seems to be related to the dV/dT on the +5V. Anyone have any
> ideas? This is getting tiresome.
> 
>   Cheers,
>      Steve
> 
> --
> Steve Wiseman, Senior Systems Engineer, SJ Consulting Ltd, Cambridge, UK
> Desk +44 1223 578524 (Fax 578525) Group +44 1223 578518   steve@sj.co.uk

I've seen application where the _total_ decoupling on the +5Vdc rail was
enough to exceed the maximum specified capacitive loading of certain PSU
(especialy PUPS), in this situation some PSU will start and some will not.
To see if its your problem  all you have to do is to add-up all decoupling 
capacitors values on your +5V rail and see the designer and/or supplier of 
your PSU to check if its OK or not.

Marc Boulais
Article: 4459
Subject: Re: Info/opinions wanted for PCI interface in an FPGA
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 1 Nov 1996 05:33:18 GMT
Links: << >>  << T >>  << A >>
Dan,

Your interpretation of how to implemen multiple configuration spaces is
correct to the best of my knowledge.  The spec is sparse about it, but is
pretty clear.

If you are going to implement that in a Xilinx FPGA, you will have to use
one column of CLBs for each ROM portion of each function, and if you want
5, that would be 5 columns.  You would also need 1 base address reg per
function, and one status command register per function, thats 10 more
columns.

I have done three PCI designs using Xilinx 4k series parts.  None of them
multifunction.  That doesn't sound that hard to implement on top of what I
have done.  I have a PCI core of my own done in Viewlogic schematics.  It
supports both target and a burst master.  It is not based on the Xilinx
design, actually, they were originally going to buy mine.

Do you need target only or master too?

Austin Franklin
darkroom@ix.netcom.com

  
Article: 4460
Subject: What is the fastest fpga for ...
From: Vincent.Himpe@ping.be (Vincent Himpe)
Date: Fri, 01 Nov 1996 12:06:11 GMT
Links: << >>  << T >>  << A >>
hi

I have a small problem.

I have a fairy simple circuit : a 24 bit counter with parallel load  
The counter is hooked to a comparator which can either reset the counter  , or
make it load a new value.
In this way it forms a sequencer.
This should be easy. 

The entire design has some additional registers but these are very low speed.
A Verilog (Synopsys) file is available.

now comes the tricky part: This counter needs to run at at least 60MHZ !.


I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
It fits all right. But the maximum speed i can get is around 25 MHz. 

Are there any comonents out there that can do this ?.
After all , i can make the entire circuit with some 74Fxxx series ttl chips....

regards

Vincent.Himpe@ping.be
regards

Vincent
--------------------------------------------------------------
Vincent Himpe
                                                 /////
Internet :                                       O  *)
   vincent.himpe@ping.be                          /
   vi_himpe@mietec.be                            \__/

http://www.ping.be/~ping0751
--------------------------------------------------------------

Article: 4461
Subject: Re: What is the fastest fpga for ...
From: "Thomas J. Loftus" <tloftus@hns.com>
Date: Fri, 01 Nov 1996 09:42:28 -0500
Links: << >>  << T >>  << A >>
Vincent,

You don't say what the long delay path is which is preventing you from
reaching your 65 MHz speed goal.  I will guess that because of the
size of your counter, you have too many levels of logic to accomodate
both the counter, the comparator and the reset.  Have you looked at the
schematic inside Synopsys to see what is being generated?

I would recommend splitting up your problem to isolate where to
spend the most effort.  For example, can you implement the
circuit at speed if it was only 8 bits?  Can you implement only
the counter without the comparator?  Perhaps breaking your problem
up and pipelining it will work well.

I don't have specific experience on current Xilinx parts, but I have
implemented 24 and 32 bit high speed counters for military parts
in older technologies that could easily do 25 MHz.  Since current
technology parts are much faster, you must be
doing something inefficient in the coding or synthesis of your 
design.  Minimizing the levels of logic between registers is the
key and no magic with the synthesis tools is a substitute.

Lastly, as seems to be mentioned commonly on these pages, there are
special resources in each FPGA family which make for the highest
speed design.  You need to make use of these with your synthesis
tool to get the most effective results.  Just using generic gates
during synthesis will probably not succeed.  We use FPGA Compiler
with the vendor supplied DesignWare libraries and do pretty well.

Hope this helps.

Tom




Vincent Himpe wrote:
> 
> hi
> 
> I have a small problem.
> 
> I have a fairy simple circuit : a 24 bit counter with parallel load
> The counter is hooked to a comparator which can either reset the counter  , or
> make it load a new value.
> In this way it forms a sequencer.
> This should be easy.
> 
> The entire design has some additional registers but these are very low speed.
> A Verilog (Synopsys) file is available.
> 
> now comes the tricky part: This counter needs to run at at least 60MHZ !.
> 
> I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
> It fits all right. But the maximum speed i can get is around 25 MHz.
> 
> Are there any comonents out there that can do this ?.
> After all , i can make the entire circuit with some 74Fxxx series ttl chips....
> 
> regards
> 
> Vincent.Himpe@ping.be
> regards
> 
> Vincent
> --------------------------------------------------------------
> Vincent Himpe
>                                                  /////
> Internet :                                       O  *)
>    vincent.himpe@ping.be                          /
>    vi_himpe@mietec.be                            \__/
> 
> http://www.ping.be/~ping0751
> --------------------------------------------------------------

-- 
Thomas J. Loftus             |   Electrical Design Automation Group
phone: (301) 548-1916        |   Hughes Network Systems
email: tloftus@hns.com       |   11717 Exploration Lane
FAX:   (301) 212-2099        |   Germantown, MD  20876
Article: 4462
Subject: FPGA Demonstration Board
From: rci111@aol.com (RCI111)
Date: 1 Nov 1996 10:41:14 -0500
Links: << >>  << T >>  << A >>
Can anyone tell me where I can get XC3000/XC4000 FPGA demonstration Board
and pricing ? Thank you very much .
Article: 4463
Subject: Position Available - Programmable logic design
From: Eric Huber <huber@aio.jsc.nasa.gov>
Date: Fri, 01 Nov 1996 10:08:03 -0600
Links: << >>  << T >>  << A >>
Position Available :

Metrica Inc. has a small but growing robotics research group located in
the Houston area. This group is ramping up for several new projects
including one involving the development of a high speed stereo vision
machine. For this project we will need to hire an Electrical and/or
Computer engineer with the following skills and experience :


* Programmable logic design (especially FPGA)

* Digital Signal Processing (especially video processing)

* Board layout and fabrication

* D/A and A/D conversion

* C or C++


Applicants should have an affinity for a fun but difficult projects.
Metrica provides competitive salaries and benefits to motivated
individuals.

Contact :

Eric Huber
huber@metricanet.com

 
-- 
Eric
Article: 4464
Subject: Re: What is the fastest fpga for ...
From: waters@npss.enet.dec.com ()
Date: 1 Nov 1996 17:45:23 GMT
Links: << >>  << T >>  << A >>

In article <55clpn$dod@news2.Belgium.EU.net>, Vincent.Himpe@ping.be (Vincent Himpe) writes:
|>I have a fairy simple circuit : a 24 bit counter with parallel load  
|>The counter is hooked to a comparator which can either reset the counter,
|>or make it load a new value.  In this way it forms a sequencer.
|>
|>The entire design has some additional registers but these are very low speed.
|>A Verilog (Synopsys) file is available.
|>
|>now comes the tricky part: This counter needs to run at at least 60MHZ !.
|>I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
|>It fits all right. But the maximum speed i can get is around 25 MHz. 

Are you willing to build the counter with the low bits as a logically
separate prescaler?  (The prescaler could be made programmable too.)
My point is that a 24-bit equality comparator doesn't give you the highest
speed.  Only the low bits to the comparator change near the full clock rate.
So separate the bottom 2 bits from the upper 22.  Use predictive logic to
handle the upper 22 bits, making comparator decisions only once per 4 clock
cycles.  When you're within 4 to 7 ticks of the target value or something
like that, enable the full-speed decision on the low 2 bits to clear or
reload the whole counter.

You'll need to compare the top 22 bits to a value 1 less than their target
value.  So the minimum counter cycle length would be 4 or so.  Is that
acceptable?

If so, you can probably run the sequencer at over 150 MHz in XC3190A-09.
I don't know for sure.  We have a Xilinx-based ATM test device in the lab,
and its XC3190A-4 chip includes a fixed, 32-state counter at 155.52 MHz.
I'm hoping that with XC3190A-09, you can build the 2-bit loadable, resettable
prescaler at 150 MHz which allows the rest of your sequencer to run at 1/4
that clock rate (using multi-cycle logic).  --Greg Waters, Digital Equipment
Article: 4465
Subject: Re: VHDL for Xilinx designs?
From: husby@fnal.gov (Don Husby)
Date: 1 Nov 1996 20:31:08 GMT
Links: << >>  << T >>  << A >>
Austin Franklin  darkroom@ix.netcom.com wrote:
> A Viewlogic schematic symbol will allow you to have anything underlying it.
> [etc]

My tool allows you to put equations right on the schematic sheet as
attributes. The software post-processes a .wir file and looks for
attributes that contain logic equations and then converts the logic
eqations into gates.  I've been using for about three years now and
wouldn't do a design without it. 

You can see example schematics (adobe acrobat .PDF format) at

            http://www-ese.fnal.gov/eseproj/trigger/hit.pdf 
   and      http://www-ese.fnal.gov/eseproj/trigger/dsender.pdf

I keep a copy of these tools at our ftp site:

 ftp://eseserver1.fnal.gov/pub/docs/xilinx
    awks.zip       tools (1.2M)
    example.zip    example designs (264K)
    mans.zip       Only the documentation (14K)
    read.me        installation instructions (3K)

    




Article: 4466
Subject: Re: What is the fastest fpga for ...
From: jhallen@world.std.com (Joseph H Allen)
Date: Fri, 1 Nov 1996 21:23:13 GMT
Links: << >>  << T >>  << A >>
In article <55clpn$dod@news2.Belgium.EU.net>,
Vincent Himpe <Vincent.Himpe@ping.be> wrote:
>hi

>I have a small problem.

>I have a fairy simple circuit : a 24 bit counter with parallel load  

For small designs, the XC3000 series can be faster- like 270MHz for a single
flip flop in the fastest part.  If it's possible, use a linear feedback
shift register for your design instead of a counter.  The count sequence
will not be linear, but it can cycle through all but one of the possible
codes for 24 bits.  The longest delay in this circuit will be only a single
flip flop plus a single logic block, plus the routing delay.

-- 
/*  jhallen@world.std.com (192.74.137.5) */               /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 4467
Subject: Re: What is the fastest fpga for ...
From: "Kevin D. Drucker" <kdrucker@hns.com>
Date: Fri, 01 Nov 1996 16:30:34 -0500
Links: << >>  << T >>  << A >>
Vincent Himpe wrote:
> I have a fairy simple circuit : a 24 bit counter with parallel load
> The counter is hooked to a comparator which can either reset the counter  , or
> make it load a new value.
> In this way it forms a sequencer.
> This should be easy.
> The entire design has some additional registers but these are very low speed.
> A Verilog (Synopsys) file is available.
> now comes the tricky part: This counter needs to run at at least 60MHZ !.
> I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
> It fits all right. But the maximum speed i can get is around 25 MHz.

Are you using the E or EX parts?

> Are there any comonents out there that can do this ?.
> After all , i can make the entire circuit with some 74Fxxx series ttl chips....

I would say your biggest problems may be:
1) Are you using the carry chains?  You may not have the XBLOX libraries
from Xilinx, if not, then the design is goign to use inefficient routing
resources and logic mapping.

2) The counter you are trying to synthesize is 24 bits.  Best case (if
you're lucky) is that it's going to fit int
about 16 CLBs (maybe a few more or less) when you consider the not only
the flops, but the logic that feeds each flop. In the part you've
select, you have a 10x10 CLB matrix.  As a result, you are going to have
to cross columns.  BIG performance hit.  Once you get the area down,
pick a part that fits the entire counter in one column (i.e. 4006/4008)

3) If you do all this, and STILL don't meet your performance goal (you
should though), try duplicating certain intermediate bits of the counter
and then floorplanning them closer to the next over (or two or three)
bits in the chain (i.e. create cheater bits).  This will give you more
clocks to get the data where it's going (good mainly for long barrel
shifters).

If that doesn't work...call me.

-Kevin

Kevin D. Drucker        |  email: kdrucker@hns.com
Member Technical Staff, |  work:  (301) 601-4167  
Hardware Development    |  fax:   (301) 601-4275  
Hughes Network Systems  |
Article: 4468
Subject: Re: What is the fastest fpga for ...
From: "Austin Franklin" <darkroom@ix.netcom.com>
Date: 1 Nov 1996 22:07:27 GMT
Links: << >>  << T >>  << A >>

> The entire design has some additional registers but these are very low
speed.
> A Verilog (Synopsys) file is available.
> 
> now comes the tricky part: This counter needs to run at at least 60MHZ !.
> 
> 
> I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
> It fits all right. But the maximum speed i can get is around 25 MHz. 

You say you're using synthesis?  Did you try doing the design in
schematics?

Austin Franklin
darkroom@ix.netcom.com

Article: 4469
Subject: XACT under WinNT is very slow
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Fri, 01 Nov 1996 17:49:07 -0600
Links: << >>  << T >>  << A >>
Hi All,

Following the instructions offered up by Xilinx, I've gotten the command
line portion of XACT (5.2.1) running under WinNT 3.51.  However it runs
about 30 times slower than under pure DOS 6.22.  Has anyone else
encountered this problem?  Better yet, has anyone else encountered a
solution?!

Thanks,
Scott
Article: 4470
Subject: Online Panel - Users tell Vendors
From: sbaker@best.com
Date: 2 Nov 1996 01:00:20 GMT
Links: << >>  << T >>  << A >>
The free WinEDA online conference has just activated a week long Panel Debate on
What Users Want From Their EDA Vendors!  A group of 7 user panelists (plus one
editor - Richard Goering of EE Times) speak out and tell the vendors what works for
them, what doesn't and what they need to improve their design flow.  And the
vendors are standing by to respond...

This Panel is open to the public - tell us what YOU want from vendors.

Access the WinEDA panel at http://www.wedasite.com/session6.  Lurkers welcome.

To engage in the Discussion, please register at no charge at the gateway
site: http://www.wineda.com.

The Panel session is open from Nov. 1 through Nov. 8.  Check it out and maybe 
you'll find some solutions or peers with similar problems who can help.

Stan Baker
Program Chairman
WinEDA '96

Article: 4471
Subject: Re: What is the fastest fpga for ...
From: peter@xilinx.com (Peter Alfke)
Date: Fri, 01 Nov 1996 19:14:53 -0700
Links: << >>  << T >>  << A >>
In article <55clpn$dod@news2.Belgium.EU.net>, Vincent.Himpe@ping.be
(Vincent Himpe) wrote:

> hi
> 
> I have a small problem.
> 
> I have a fairy simple circuit : a 24 bit counter with parallel load  
> The counter is hooked to a comparator which can either reset the counter  , or
> make it load a new value.
> now comes the tricky part: This counter needs to run at at least 60MHZ !.
> 
The problem with this circuit is that it must propagate a carry through 24
bits in less than 16 ns. Everything else is comparatively trivial.
A ripple-carry adder circuit may be marginally able to do this.

There are popular tricks to speed up synchronous counters. The most
popular is the CEP/CET trick used in the 74161.
Watch out ! 
These tricks do not really work for a loadable counter, if you expect to
load an arbitrary value on one clock edge, and use the next clock edge to
increment the counter. I have done applications work on these counters for
27 years, ever since their birth as the Fairchild 9316, and I know all the
potential pitfalls.

So you have to decide: 
If you need absolute universality, loading and counting on successive
clock edges, without a wait state, tehn you need very fast hardware, and
you cannot use any sneaky tricks. You will most likely have problems with
the MSI solution also.
 
If, however, you can stall the counter for one clock period after loading
it, or if you know that you will never load "ugly" values, then the
problem becomes very much simpler.

If ( IF ! ) you can use an LFSR counter, the problem becomes almost
trivial, and the circuit can easily run at 100 or 150 MHz.

In either case I can tell you the best Xilinx solution, if you e-mail me
more details.( peter@xilinx.com ).

Peter Alfke, Xilinx Applications
Article: 4472
Subject: Re: What is the fastest fpga for ...
From: fliptron@netcom.com (Philip Freidin)
Date: Sat, 2 Nov 1996 04:47:13 GMT
Links: << >>  << T >>  << A >>
In article <327A6BFA.23AA@hns.com> kdrucker@hns.com writes:
>Vincent Himpe wrote:
>> I have a fairy simple circuit : a 24 bit counter with parallel load
>> The counter is hooked to a comparator which can either reset the counter  , or
>> make it load a new value.
>> In this way it forms a sequencer.
>> This should be easy.
>> The entire design has some additional registers but these are very low speed.
>> A Verilog (Synopsys) file is available.
>> now comes the tricky part: This counter needs to run at at least 60MHZ !.
>> I tried synthesizing it into a xilinx Xc4003 and XC4004 : no luck.
>> It fits all right. But the maximum speed i can get is around 25 MHz.
>
>Are you using the E or EX parts?
>
>> Are there any comonents out there that can do this ?.
>> After all , i can make the entire circuit with some 74Fxxx series ttl chips....
>
>I would say your biggest problems may be:
>1) Are you using the carry chains?  You may not have the XBLOX libraries
>from Xilinx, if not, then the design is goign to use inefficient routing
>resources and logic mapping.

The biggest problem is probably synthesis, but as Kevin points out in the 
next section, available topological constraints will also effect the design.

Before worrying about the details, take a step back. If a binary sequence
is not needed, then an LFSR may be a much smarter choice, as there is no
carry chain. Can the comparison be pipelined? Can a prescaler be used for
the low order bits?, Does the parallel load need to be done in a single
cycle, ... and others.

>2) The counter you are trying to synthesize is 24 bits.  Best case (if
>you're lucky) is that it's going to fit into
>about 16 CLBs (maybe a few more or less) when you consider the not only
>the flops, but the logic that feeds each flop. In the part you've
>select, you have a 10x10 CLB matrix.

Well actually 12 CLBs (or 13 if you want TC or CEO. See xilinx's CC8CLE
for the schematic and floor plan. Libraries manual page 3-163

> As a result, you are going to have to cross columns.  BIG performance hit.

Only if you let the synthesis software do it for you. The XC4000 and
XC4000E devices allow the carry to go up one column and down the next,
with the U turn forced to be on the top edge, and the direction is only
left to right. Topology could look like:

Q10,Q11    Q12,Q13
Q8,Q9      Q14,Q15
Q6,Q7      Q16,Q17
Q4,Q5      Q18,Q19
Q2,Q3      Q20,Q21
Q0,Q1      Q22,Q23

i.e, two columns, by 6 rows, top row must be top row of the chip.

A similar U turn capability is on the bottom row of the chips.

None of the Xilinx libraries use this capability, nor can any of the
software figure this out for itself, and fold a counter over. If you
want to do this, you have to draw the schematic your self, and do the 
location constraints just right.

As I have often said, " the xilinx tools may not be easy to use, but
if there is a way for the chip to do something neat, there is a way to
beat the software into doing just what you want"

> Once you get the area down,
>pick a part that fits the entire counter in one column (i.e. 4006/4008)
>
>3) If you do all this, and STILL don't meet your performance goal (you
>should though), try duplicating certain intermediate bits of the counter
>and then floorplanning them closer to the next over (or two or three)
>bits in the chain (i.e. create cheater bits).  This will give you more
>clocks to get the data where it's going (good mainly for long barrel
>shifters).
>If that doesn't work...call me.
>-Kevin
>Kevin D. Drucker        |  email: kdrucker@hns.com
>Member Technical Staff, |  work:  (301) 601-4167  
>Hardware Development    |  fax:   (301) 601-4275  
>Hughes Network Systems  |


So If we look at the data book, and guess that Vincent is trying to get
this into an XC4003E-4, then the delay through the carry chain is:

Tcko + Troute + Topcy + 11 * Tbyp + Tcck  = 3.7 + 1.0 + 3.2 + 11*1.0 + 5.0
 = 23.9 = 41.8 MHz   (the Tcck is a guess because it isn't in my 1996
data book! Come on Xilinx, I've been buying these for over a year. How
about some non preliminary AC info)

Ok, so here it is for -2 speed grade (marked 'advanced' in my 1996-july
data book:

2.8 + 1.0 + 2.1 + 11*0.6 + 4.0 = 16.5 = 60.6 MHz

A little tight for my liking. I think maybe a prescaler or LFSR or other
modified topology is probably called for. 

Good Luck
Philip Freidin

Article: 4473
Subject: Re: Altera Configuration EPROM Equivalents
From: Martin Mason <martin@atmel.com>
Date: Sat, 02 Nov 1996 18:00:55 -0500
Links: << >>  << T >>  << A >>
Paul S Secinaro wrote:
> 
> Just a note/warning: According to the FAQ on the Atmel web site
> (www.atmel.com), the only package that's compatible with Altera is the
> 8-pin DIP.  Apparently Altera's PLCC20 package has a wierd pinout
> (thanks a lot, Altera).
> 
> -Paul

Paul all is not lost if you want to use the 20 pin PLCC socket for 
Atmel's EEPROM serial FPGA configuration memories with Altera FPGAs.
(8 pin dip is pin compatible as you point out)

Q.  Can I use the AT17Cxxx 20 pin PLCC package in the Altera 20 pin PLCC 
    socket.
A.  There is a very simple PCB modification that can be made to support 
    the Atmel 20 pin plcc device.  The modification works like this:

	Atmel 20 pin plcc	Altera 20 pin plcc
	Pin #	Function	Pin #	Function
	========================================
	2	Data		2 	Data
	4	CLK		4	CLK
	8	OE/Reset	6 	OE/Reset
	9	CS		8 	CS
	10 	GND		10	GND
	18	VDD		18 	VDD
	20	VDD		20	VDD


	Pin out to support both 20 pin PLCC formats
	Pin #	Function
	================
	2	Data
	4 	CLK
	6	OE/Reset
	8	Jumper to pin 9 for Altera (CS)  
		Jumper to PIN 6 for Atmel  (OE/Reset)
	9	CS
	10 	GND
	18	VDD
	20 	VDD

You may also find this table useful: 

Device		Bits	Altera Part #	Atmel Part #	
====================================================
EPF8282		40K	EPC1064	     	AT17C65
EPF8452		64K	EPC1064	     	AT17C65
EPF8636		86K	EPC1213	     	AT17C128 **
EPF8820		128K	EPC1213	     	AT17C128 **
EPF81188	192K	EPC1213	     	AT17C256 
EPF81500	250K	EPC1213+1064	AT17C256 **

** Lower density Atmel part can be used.

You can request samples at http://www.atmel.com/atmel/config.html
You can get info. at http://www.atmel.com/atmel/products/products3.html

Regards,

Martin Mason
configurator@atmel.com
Article: 4474
Subject: Re: VHDL for Xilinx designs?
From: z80@digiservve.com (Peter - one extra v to stop junk mail)
Date: Sun, 03 Nov 1996 11:43:39 GMT
Links: << >>  << T >>  << A >>


>A Viewlogic schematic symbol will allow you to have anything underlying it.
> You specify it as a type module (instead of type composite) and when you
>run wir2xnf it doesn't go into the symbol.  Then you need some tool (like
>any of the synthesizers that provide Xilinx output, XAbel, Synopsys etc...)
>that puts out a .xnf file. When you run xnfmerge, it just looks for .xnf
>files, and provided the signal names match up (and it will tell you if they
>don't!) you're set!

Yes, I have done this many times with

 CUPL -> PALASM -> PDS2XNF -> XNFOPT -> XNF

All in one batch file, and much cheaper than any VHDL tool I know of.
The CUPL is a 1991 version, BTW. This capability was much restricted
in later versions AFAIK, to make you buy the much more expensive
version of CUPL which has direct XNF output. And Xilinx stopped
supplying PDS2XNF as well.

I recently looked at the very cheap Altera VHDL tool, to see if it can
somehow be used to do the above, i.e. to produce PALASM output. It
seems it is possible, if you have a JEDEC -> PALASM converter. There
are some around.

Peter.


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