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Messages from 5375

Article: 5375
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: "John L. Smith" <jsmith@univision.com>
Date: Tue, 11 Feb 1997 13:45:23 -0800
Links: << >>  << T >>  << A >>
Christos Dimitrakakis wrote:
> 
> Anyone got any info on RNGs?
> Since I'm only generating a 6-bit number with it
> I could just use a simple counter scheme for it that runs @8Mhz
> while using one of the other clock outputs provided in the chip,
> say the 490Hz one, for the rest of the circuitry.
> Will that reduce the decorrelate the timing of the RNG from the
> rest of the chip?
> 
> Is there any better way that does not take up a lot of chip area?
> [I considered using a Fibonacci series, but it takes up too much space
> if sufficient randomness is required]
> 

Peter Alfke at Xilinx put together a good app note on compact
long linear feedback shift registers for the 4000 family,
available in pdf @

http://www.xilinx.com/apps/counter.htm

Use a long enough one, and you probably don't have to
worry about correlation.



-- 
John L. Smith
Univision Technologies, Inc.
6 Fortune Drive
Billerica, MA 01821-3917
jsmith@univision.com
Article: 5376
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: "John L. Smith" <jsmith@univision.com>
Date: Tue, 11 Feb 1997 13:57:56 -0800
Links: << >>  << T >>  << A >>
Christos Dimitrakakis wrote:
> 
> Anyone got any info on RNGs?
> Since I'm only generating a 6-bit number with it
> I could just use a simple counter scheme for it that runs @8Mhz
> while using one of the other clock outputs provided in the chip,
> say the 490Hz one, for the rest of the circuitry.
> Will that reduce the decorrelate the timing of the RNG from the
> rest of the chip?
> 
> Is there any better way that does not take up a lot of chip area?
> [I considered using a Fibonacci series, but it takes up too much space
> if sufficient randomness is required]
> 

Peter Alfke put together a good app note on compact long linear feedback
shift registers for the 4000 family, available in pdf at:

http://www.xilinx.com/apps/counter.htm

With a long enough counter of this type , you don't need to worry about
correlation, and it doesn't take up much space either.

-- 
John L. Smith
Univision Technologies, Inc.
6 Fortune Drive
Billerica, MA 01821-3917
jsmith@univision.com
Article: 5377
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: Ray Andraka <randraka@ids.net>
Date: Tue, 11 Feb 1997 15:23:06 -0800
Links: << >>  << T >>  << A >>
Christos Dimitrakakis wrote:
> 
> Anyone got any info on RNGs?
> Since I'm only generating a 6-bit number with it
> I could just use a simple counter scheme for it that runs @8Mhz
> while using one of the other clock outputs provided in the chip,
> say the 490Hz one, for the rest of the circuitry.
> Will that reduce the decorrelate the timing of the RNG from the
> rest of the chip?
> 
> Is there any better way that does not take up a lot of chip area?
> [I considered using a Fibonacci series, but it takes up too much space
> if sufficient randomness is required]
> 
If you are looking for a uniform distribution just use a linear feedback
shift register counter (LFSR).  The sequence out of the LFSR is
pseudo-random and will repeat after 2^n -1 clocks (assuming the feedback
chosen is for a maximal length sequence).  The counter should have
several more bits than your desired result, and the msbs of the output
should be taken from the input end of the shift register to avoid a
tendency toward an exponential function.  Refer to the Xilinx app notes
on LFSRs and on efficient shift registers using the CLB RAM for
implementation details.  BTW, the LFSR can be done in just a few CLBs.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5378
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: mush@jps.net (David Decker)
Date: Wed, 12 Feb 1997 01:24:17 GMT
Links: << >>  << T >>  << A >>
"John L. Smith" <jsmith@univision.com> wrote:

>Christos Dimitrakakis wrote:
>> 
>> Anyone got any info on RNGs?
>> Since I'm only generating a 6-bit number with it

>Peter Alfke at Xilinx put together a good app note on compact
>long linear feedback shift registers for the 4000 family,
>available in pdf @
>
>http://www.xilinx.com/apps/counter.htm
>
>Use a long enough one, and you probably don't have to
>worry about correlation.

>
>-- 
>John L. Smith
>Univision Technologies, Inc.
>6 Fortune Drive
>Billerica, MA 01821-3917
>jsmith@univision.com

Remember, you can use a long sequence RAM based LFSR as suggested by
Peter Alfke/John L. Smith, or just a normal LFSR, if you don't need
too many bits, Then just use a random process to permanently select 6,
of the 'n' shift register bits. Now, you have a 6 bit output that will
not repeat for an arbitrarily long time.

Dave Decker
ddecker@diabloresearch.com
mush@jps.net
Article: 5379
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: mush@jps.net (David Decker)
Date: Wed, 12 Feb 1997 01:52:10 GMT
Links: << >>  << T >>  << A >>
"John L. Smith" <jsmith@univision.com> wrote:

>Christos Dimitrakakis wrote:
>> 
>> Anyone got any info on RNGs?
>> Since I'm only generating a 6-bit number with it

.  .  .

> 
>
>Peter Alfke at Xilinx put together a good app note on compact
>long linear feedback shift registers for the 4000 family,
>available in pdf @
>
>http://www.xilinx.com/apps/counter.htm
>
>Use a long enough one, and you probably don't have to
>worry about correlation.
>
>-- 
>John L. Smith
>Univision Technologies, Inc.
>6 Fortune Drive
>Billerica, MA 01821-3917
>jsmith@univision.com

Remember, you can use a long sequence RAM based LFSR as suggested by
Peter Alfke/John L. Smith, or just a normal LFSR, if you don't need
too many bits, Then just use a random process to permanently select 6,
of the 'n'  shift register bits. Now, you have a 6 bit output that
will not repeat for an arbitrarily long time.
Article: 5380
Subject: PCI Prototyping board with a XC4013E or XC4013EX
From: "Peeters" <iolair@weirdness.com>
Date: 12 Feb 1997 02:15:10 GMT
Links: << >>  << T >>  << A >>
Knows anybody where you can or is willing to sell a 'simple' PCI
prototyping board with a XC4013E or XC4013EX ?
A scheme or PCB layout would also be great !!!
Purpose : testing VHDL code for the PCI control. 
I haven't found it on the Xilinx website, even pci@xilinx.com never
replied.
(I don't need one with six or ten FPGA's , reconfigurable computing machine
..)

No PCI prototyping board, PCI prototyping kit, PCI demo kit,...

Thanks for any hints 8-]




Article: 5381
Subject: Re: PCI Prototyping board with a XC4013E or XC4013EX
From: "Austin Franklin" <#darkroom@ix.netcom.com#>
Date: 12 Feb 1997 03:37:57 GMT
Links: << >>  << T >>  << A >>
I tried to e-mail you, but it got bounced.  If you want info on this,
e-mail me directly or provide a valid e-mail address.

I have a board that has a 4013E PQ208 on it, and is attached to the PCI
bus.

I'm curious how you are going to do a PCI interface for a Xilinx in an HDL.
 Even doing it in schematics requires a lot of mapping, placement and logic
massaging to make 33MHz.  You can probably do a simple target
implementation, but not a master, much less a burst master in an HDL unless
you can map, place and control how the logic gets implemented...

Austin Franklin
..darkroom@ix.netcom.com.


Peeters <iolair@weirdness.com> wrote in article
<01bc188a$b27fba80$8b0c07c2@mon00238>...
> Knows anybody where you can or is willing to sell a 'simple' PCI
> prototyping board with a XC4013E or XC4013EX ?
> A scheme or PCB layout would also be great !!!
> Purpose : testing VHDL code for the PCI control. 
> I haven't found it on the Xilinx website, even pci@xilinx.com never
> replied.
> (I don't need one with six or ten FPGA's , reconfigurable computing
machine
> ..)
> 
> No PCI prototyping board, PCI prototyping kit, PCI demo kit,...
> 
> Thanks for any hints 8-]
> 
> 
> 
> 
> 
Article: 5382
Subject: @@ it's very easy to find chipmaker websites (approx. 350 valid sites listed here) @@
From: Gray Creager <gcreager@scruznet.com>
Date: Wed, 12 Feb 1997 00:10:16 -0800
Links: << >>  << T >>  << A >>
Just a reminder to everyone.

I have been compiling a semiconductor manufacturer website listing (and
making it available to other engineers on the web) for about a year and
a half now. I used to post it to sci.electronics every so often in the
past, but it got way too big for that. There are about 350 companies on
the list currently. These are chipmakers, so if you can't find the data
sheet that you need because you don't know the manufacturer's website,
try my listing. Bookmark it and tell your co-workers.

I try to keep it the most up-to-date and useful listing anywhere on the
web (by constantly searching for new URLs before most others find them)
and it is now widely used by a lot of people. The following categories
exist among my "engineering" subpages.

- Semiconductor URLs (Brief listing)
- Semiconductor URLs (Verbose listing; includes product categories)
- New Semiconductor URLs
- Missing Semiconductor URLs
- Motivations
- 25 Best Semiconductor Websites
- 25 Worst Semiconductor Websites
- Engineering Humor

try it out, I think you'll find it to be quite useful. Let me know what
you think.

-- 
+---------------------------------------------+
| Gray Creager                                |
| http://www.scruznet.com/~gcreager           |
+---------------------------------------------+
| "If you're not part of the solution, you're |
|  part of the precipitate." - Steven Wright  |
+---------------------------------------------+
Article: 5383
Subject: Re: Serial Communication Controller Design
From: Rune Baeverrud <r@acte.no>
Date: Wed, 12 Feb 1997 09:48:39 +0100
Links: << >>  << T >>  << A >>
Peter wrote:

> I personally would like to see *schematic* (not HDL) designs for:

Doing such designs in schematic is a waste of designer's time. This is
so much easier accomplished in a HDL.

> 1. The 16450 UART (with the FIFOs done in the schematic).
> 
> 2. The 16550 UART (with the 16-byte FIFOs done using external RAM, and
> thus obviously extensible). It would be a waste of an FPGA to do 32
> bytes of FIFO inside the FPGA.

Why would you want the 16450/16550 with all the overhead (and limited)
functionality? If you start with my compact UART, then you could easily
add a FIFO buffer if you need it, and your design will consume very
little FPGA space.

By the way: If you use an Altera FLEX 10K, the dedicated RAM blocks are
ideal for implementing a FIFO buffer.

My Compact UART is located at:
http://www.geocities.com/SiliconValley/Lakes/3656

_-_rune_-_
Article: 5384
Subject: bonding of XC4025
From: juerg@zaphod.ethz.ch (Juerg Haefliger)
Date: 12 Feb 1997 13:59:32 GMT
Links: << >>  << T >>  << A >>
hi,
does anybody know how the core of a XC4025 is connected to the pads
of the package (HQ240).
what i have to know is how the core-geometry looks like and which logic-
cell is connected to which pad.
is there a chance to get these informations from XACTstep? i played around
a short time with the tool, so don't expect i really understand the software!
thanks
Article: 5385
Subject: Re: bonding of XC4025
From: juerg@zaphod.ethz.ch (Juerg Haefliger)
Date: 12 Feb 1997 15:24:14 GMT
Links: << >>  << T >>  << A >>
Juerg Haefliger (juerg@zaphod.ethz.ch) wrote:
: hi,
: does anybody know how the core of a XC4025 is connected to the pads
: of the package (HQ240).
: what i have to know is how the core-geometry looks like and which logic-
: cell is connected to which pad.
: is there a chance to get these informations from XACTstep? i played around
: a short time with the tool, so don't expect i really understand the software!
: thanks

what i need is something like the 'CLB-to-PAD relationship' as described
in the documentation for the XC50xx.
Article: 5386
Subject: Re: bonding of XC4025
From: fliptron@netcom.com (Philip Freidin)
Date: Wed, 12 Feb 1997 16:57:28 GMT
Links: << >>  << T >>  << A >>

You can find out the CLB row/column relationship by using either the XDE 
chip editor, or the floorplanner. For XDE just open it and select a NEW 
chip, and set the type to the partnumber and package you will be using.

For the floorplanner, you need to create a trivial dummy design so that 
the floorplanner has something to munch on.

The info you want is NOT published in any of Xilinx's documentation for 
any XC 2000, XC3000, XC4000, XC4000E, XC4000A, XC4000H products. This has
annoyed me for years, and I have repeatedly asked for Xilinx to include
this info in their documentation. No luck yet !

Another alternative is LCA2PS.EXE  at ftp.netcom.com :
/pub/fl/fliptron/files_from_fliptron/lca2ps.exe

This program needs an empty LCA file (you can create one with an editor)
and in -template mode may be just what you need. You need a postscrip 
printer to view the output.

Philip Freidin.

In article <5dsic4$bf@elna.ethz.ch> juerg@zaphod.ethz.ch (Juerg Haefliger) writes:
>hi,
>does anybody know how the core of a XC4025 is connected to the pads
>of the package (HQ240).
>what i have to know is how the core-geometry looks like and which logic-
>cell is connected to which pad.
>is there a chance to get these informations from XACTstep? i played around
>a short time with the tool, so don't expect i really understand the software!
>thanks


Article: 5387
Subject: Re: Serial Communication Controller Design
From: aqhrt@txt5.ibm.net (Aaron Quantz)
Date: Wed, 12 Feb 1997 17:11:07 GMT
Links: << >>  << T >>  << A >>
evjapps@inet.uni-c.dk wrote:

>Hello all Altera designers!

>I would like to promote the idea of a FreeCore Library. The FreeCore
>Library consists of free, parameterizable building blocks for Altera
>programmable logic that can be used in your design for absolutely free!

>My first contribution is the parameterizable Compact UART. This is a
>simple, complete and compact UART. An 8-bit UART may consume as little
>as 63 logic cells in a FLEX 8000 or FLEX 10K architecture, including
>transmitter, receiver and baud rate generator.

>The documentation and download page is available at:

>http://www.geocities.com/SiliconValley/Lakes/3656/

>Please give me your feedback on the FreeCore philosophy. I plan to set
>up a FreeCore site soon, and I hope that you, the designers and
>application guys, would like to contribute to the library.

>What kind of functions would you like to see in the FreeCore library? 

>I'm planning my next release soon: A single master I2C (I squared C)
>controller.

>NOTE:
>Although I work as a Field Application Engineer for one of the Altera
>distributors, I would like to state that this is totally my personal
>initiative. Altera is not involved in any way.

>Uffe Tyrsted Toft
>-------------------------------------------
>ACTE NC Denmark A/S
>E. V. J. Elektronik
>Titangade 15
>DK 2200 Copenhagen N
>Phone: +45 35 86 90 22
>Fax:     +45 35 86 90 00
>E-mail: evjapps@inet.uni-c.dk
>-------------------------------------------

Just checked out and downloaded your UART design. This is GREAT!! I do
Altera designs (ALOT nicer than that OTHER companies tools!) and have
an application I'll be working on in the next couple of months. I will
plan on using your design and see how it works. Keep in touch.


Regards,
Aaron Quantz
Mgr Software Development, TCS
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
HR Textron                        | Phone: (805) 253-5471
25200 W. Rye Canyon Rd.           | Fax:   (805) 253-5962
Valencia, CA USA 91355-1265       | Email: aquantz@ibm.net
Visit the Textron web site: http://www.textron.com
----------------------------------------------------------------------

Article: 5388
Subject: Re: DES Challenge
From: john@iastate.edu (John Hascall)
Date: 12 Feb 1997 17:16:43 GMT
Links: << >>  << T >>  << A >>
David Jacobson <jacobson@cello.hpl.hp.com> wrote:
}Michael Koch  <mkoch@earthlink.net> wrote:
}>I have no data whatsoever
}>that columbian cocaine dealers encrypt their pick-up schedules w/ DES,
}
}I don't have a good idea what the bandwidth needed by the columbian
}drug system is, but it can't be all that high.  A hundred kilobytes a
}day would seem like plenty.  So all they have to do is exclusive-OR
}their message with the LSBs of some pre-agreed-on music CD, used as a
}one-time pad.  A 70 minute CD has 92 MB of just LSBs, good for
}encrypting 920 days of traffic at 100KB per day.  ...

   No, no, no -- the solution is for our government to ban
   the export of these one-time pads.

   One exception would be "In a Metal Mood" which we should
   carpet bomb all of our enemies with.

John
-- 
John Hascall, Software Engr.        Shut up, be happy.  The conveniences you
ISU Computation Center              demanded are now mandatory. -Jello Biafra
mailto:john@iastate.edu
http://www.cc.iastate.edu/staff/systems/john/welcome.html  <-- the usual crud
Article: 5389
Subject: CFP Design and Test special issue
From: fmeyer@cs.tamu.edu (Jackie Meyer)
Date: 12 Feb 1997 18:53:55 GMT
Links: << >>  << T >>  << A >>
                        Call For Papers:  FPGA
                  IEEE Design and Test of Computers
                            Special Issue
                   Spring 1998, Volume 15, Number 1
     Web Page: http://www.cs.tamu.edu/faculty/lombardi/datsi.htm

Deadline:  May 1st

IEEE Design and Test of Computers seeks original manuscripts for a
theme issue on Field Programmable Gate Arrays (FPGAs) scheduled to
appear in the first issue of 1998.  Articles concerning applied
research and practical experience reports are solicited.  The topics
of interest include, but are not limited to:

   FPGA Fabrication and Technology.  Manufacturing, process control,
   yield enhancement, and novel architectures for and device
   technology to support field programmable chips.

   Exploitation of Field Programmability.  Configurable computer
   architectures, rapid prototyping, programmable interconnect
   architectures, field configurable memories, programmable I/O
   systems, and novel implementations.

   Reliable Online Implementations.  Online testing, built-in
   self-test, concurrent testing, design for rapid testability,
   latency reduction, fault containment, verification of
   reprogramming, online reconfiguration approaches, and design for
   reconfigurability.

   Synthesis Approaches and Tools.  Partitioning, logic minimization
   and technology mapping, placement and routing, test generation,
   verification of synthesis, and design for synthesizability.

Submitted articles must not have been previously published or
currently submitted for publication elsewhere.  Authors should submit
their original work to the guest editor by May 1, 1997, formatted
according to the instructions below.  Notification of acceptance will
be sent September 1, 1997.  Camera-ready copy for accepted papers will
be due November 1, 1997.

Submit articles by May 1, 1997 to:

Prof. Fabrizio Lombardi, Guest Editor
Department of Computer Science                  Phone:  (409) 845--5464
Texas A & M University                            Fax:  (409) 847--8578
College Station TX  77843-3112            E-Mail:  lombardi@cs.tamu.edu

Important dates:

        May 1, 1997:  Submission deadline
  September 1, 1997:  Authors notified of acceptance
                      with requested revisions
   November 1, 1997:  Final copy due to Design & Test Managing Editor
        Spring 1998:  Publication in IEEE Design and Test of Computers

Submission requirements:

Send six (6) copies of the manuscript, in English, to the guest
editor.  Manuscripts are not to exceed 35 double-spaced pages,
inclusive of figures and tables, in A4 or 8.5 by 11 inches.  Type size
must be at least 12 point.  Each copy of the manuscript must contain a
cover page with author contact information (name, postal address,
telephone number, and e-mail address) and a 100-word abstract.
Manuscripts must be cleared for publication.  Accepted manuscripts
will be edited for technical content, structure, style, clarity, and
grammar.  Detailed information for authors can be found at the Computer
Society D&T website at http://www.computer.org/pubs/d&t/d&t.htm or in
the Spring 1996 issue of Design & Test.
Article: 5390
Subject: Re: DES Challenge
From: Ray Andraka <randraka@ids.net>
Date: Wed, 12 Feb 1997 11:11:38 -0800
Links: << >>  << T >>  << A >>
Nicholas C. Weaver wrote:

>         Back to comp.arch:  Anyone have a circuit for GENERATING
> random bits?  Preferably something that can be built into a VLSI chip?
> 
See my post or those from John Smith from yesterday regarding random
number generators in Xilinx

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5391
Subject: Re: Altera BitBlaster/ByteBlaster replacement
From: DrNo <DrNo@organisation.com>
Date: Wed, 12 Feb 1997 12:27:35 -0800
Links: << >>  << T >>  << A >>
Unfortunately, the hack of Steve Schossow won't work for Max7000s
chips... (no .ttf file). 
So if you don't want to pay 200$ for a piece of wire, you can make your
own ByteB****** with the following schematic:

Parallel port                           JTAG connector
SubD25:         HC244 buffer:           HE10 10pins:


2 ______________4_|\_16_____________________1
                  |/

3_______________2_|\_18_____________________5
                  |/

8_______________6_|\_14_____________________9
                  |/

7_______________8_|\_12_
                  |/    |
10______________________|

11______________9_/|_11____________________3
                  \|

13______________7_/|_13____________________7
                  \| 

18-25___Gnd                         Vcc____4

                                    Gnd____2,10

Gnd______1,10,19 of HC244
Vcc______20 of HC244

Enjoy !
Article: 5392
Subject: Re: bonding of XC4025
From: Ray Andraka <randraka@ids.net>
Date: Wed, 12 Feb 1997 15:45:35 -0800
Links: << >>  << T >>  << A >>
Juerg Haefliger wrote:
> 
> hi,
> does anybody know how the core of a XC4025 is connected to the pads
> of the package (HQ240).
> what i have to know is how the core-geometry looks like and which logic-
> cell is connected to which pad.
> is there a chance to get these informations from XACTstep? i played around
> a short time with the tool, so don't expect i really understand the software!
> thanks
I've run into the same thing several times.  Xilinx doesn't have the pad
to column/row info published anywhere for any of the 2K,3K or 4K parts. 
You can get the info by either going into the LCA editor or the
floorplanner.  For the floorplanner, you will need a trivial design. 
You also will need to get the package files for the 4025 from Xilinx,
since they weren't included with the XACT6 release.

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5393
Subject: Re: Gate level Simulation with Mentors Quicksim from Galileo
From: Kayvon Irani <kirani@cinenet.net>
Date: Thu, 13 Feb 1997 00:05:01 -0800
Links: << >>  << T >>  << A >>
Duncan Davis wrote:
> 
> I hoping someone can help me.
> 
> I am convinced I read a posting from someone regarding the topic of
> simulating at the gate level on Quicksim, having syntheised from Galileo.
> I seem to remember it involved EDIF. I think it appeared about a month or
> two ago.

	You're right. I've not tried it personally because we do not have the EDIF
	reader option on our quicksim; however, we were able to simulate at gate level
	with QuickHDL and vital libraries.

	Regards,
	Kayvon Irani
Article: 5394
Subject: MG Autologic, Xilinx FPGAs and X-Blox
From: Christos Dimitrakakis <olethros@geocities.com>
Date: Thu, 13 Feb 1997 10:52:42 +0000
Links: << >>  << T >>  << A >>
First of all, I'd like to thank all those that replied to my previous
question, I really appreciate it.

To the problem:

We are using MG to synthesize VHDL here at the Uni, with Xilinx-supplied
software to actually route and upload the designs to the chips.
The problem is that if the no-flatten option is used in Autologic
the component names associated with x-blocks are in capital letters.
That wouldn't be a problem if it weren't for a bug in the xilinx
software that convers everything to lower-case. This makes the xilinx
software unable to find the x-blocks components.
If the flatten option is used then the x-blocks seem to be splitted
into gates and the xilinx software works - but does it actually
re-create the x-blocks from the collection of gates, or does it leave
the gates as they were, wasting a lot of valuable space??


I tried a number of work-arounds, including:
A)renaming the components and correcting the broken references created
by the renaming
B)making an xnf netlist and skipping some of the stages that you
normally go through to place and route a design
but neither worked.

As there is no available Xilinx documentation apart from the crude
online help, I am at a loss.
Any ideas?

Thanks in advance,

-- 
Christos Dimitrakakis
---------------------
mailto:mbge4cd1@fs4.eng.man.ac.uk
mailto:mbge4cd1@afs.mcc.ac.uk
http://www.man.ac.uk/~mbge4cd1
Article: 5395
Subject: [Q].FIFO in FPGA XILINX
From: oivanov@westell.com
Date: Thu, 13 Feb 1997 06:41:28 -0600
Links: << >>  << T >>  << A >>
I am currently designing 106 Bytes(848 bits)FIFO in XILINX 4000E.
Is there any other more efficient way rather than using RAM cell macros?

Thank you!

-------------------==== Posted via Deja News ====-----------------------
      http://www.dejanews.com/     Search, Read, Post to Usenet
Article: 5396
Subject: Experience with LOG/iC2
From: bdstoehr@ise.ipvr.informatik.uni-stuttgart.de (Bernd Stoehr)
Date: 13 Feb 1997 12:54:34 GMT
Links: << >>  << T >>  << A >>
Hi,

I've just seen a LOG/iC2 design system supporting all CPLDs and 
XILINX / ACTEL FPGAs offered on the ISDATA homepage for 4.999 DM
including simulation.

Any experiences with LOG/iC2?

Thanks




Article: 5397
Subject: Re: Embedded SRAM in FPGAs
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Thu, 13 Feb 1997 14:42:20 GMT
Links: << >>  << T >>  << A >>
I work for a Lucent Disti, just so you know.

On Thu, 06 Feb 1997 05:46:45 GMT, kenk@teleport.com (Ken Krolikoski)
wrote:
>Most of Lucents sales comes from captive AT&T accounts. ORCA is not a
>major player in the general marketplace. 

So shipping millions of dollars of product in volume to large accounts
that are price/performance sensitive doesn't make you a major player
in the "general marketplace"? I believe Xilinx likes to count AT&T as
one of its customers anyway, so I don't think they could exactly be
described as 'captive'.

When a company's programmable logic offering is FPGA's, and high
density ones at that (3000 series excluded), I would think that a
market turnover of around $100M would be pretty good going. I'm sure
that if Xilinx had a 'better deal' then some of the major companies
using ORCA would switch. But they haven't.BTW  What would you suggest
they replace a 2T40A-4 with? or even a 2C40 from way back in 1995?

>The new routing sw that xilinx is releasing now for workstations and
>in april for windows NT will significantly improve your route times.

Aah. Do you mean the NeoCAD engine? I recall Lucent shipped their own
version_way_before Xilinx after the buy-out.

Lucent's Foundry 9.0 has been running on NT for about a year now. XACT
doesn't (5.x in a DOS box?) Good speed too. Well usable for large
parts so long as you have enough memory etc.

>the new 4Kex and 4kxl devices have double the routing resources of the
>4ke.

Can't get a 4010EX though, can you? and Lois Cartier says that ORCA
has more resource than 4000E. (XBRF005.pdf). How gracious!

>the next three parts available from xilinx will be the 4062(now),
>4085(2q97) and 40125(3q97). I found the press release on their web
>site. (www.xilinx.com)

I could blether on about the Lucent 3C series and the 200K+ gate parts
etc. but I don't consider this kind of posturing relevant to designers
doing work today. Actel say 500K gates, Xilinx says a million. Come on
guys, it's boring.

<snip of Xilinx vapour-ware press release>

Xilinx, Altera, Lucent, Actel (apologies for missed ones) all have
user SRAM implementations of one sort or another. Some fit well in
some areas, some don't.

Please don't slag off your competitors' business models. Customers
will spot it for the smoke screen it really is. Lucent is a $20B+
dollar company so I guess they must be getting something right:
	#1 Worldwide in Digital Cellular DSP's
	#1 Worldwide in Standard Cell ASIC
	#1 Worldwide in videoconferencing IC's
	#1 Worldwide in Telecom Power Systems

Compare FPGA's for specific applications. Sometimes Xilinx will have a
winning feature, other times Lucent, Altera, or anyone else.

Just my two cents

Stuart
Article: 5398
Subject: Re: BIGGER (was Embedded SRAM in FPGAs)
From: s_clubb@netcomuk.co.uk (Stuart Clubb)
Date: Thu, 13 Feb 1997 14:42:22 GMT
Links: << >>  << T >>  << A >>
On Thu, 6 Feb 1997 09:06:59 -0000, eteam@aracnet.com (bob elkind)
wrote:

>I don't see any reason why Lucent is any less of an FPGA
>vendor than Xilinx or Altera, for any size project or
>company.

Agreed

>On the subject of "whose xxx is bigger":  If you're going
>to use *lots* of gates (list of huge Xilinx FPGAs deleted),
>and use them at a high enough bandwidth, then power can become
>a limiting factor before you are bound by gates, routing
>channels, etc.  Last time I looked, the Lucent 2cA series
>had a speed/power advantage of X 4KE, but that may have
>changed.  Both the L and the X company have made much-needed
>improvements in the thermal characteristics of their packages,
>but last time I looked the Lucent 2C40 with its cavity-down
>packaging had a definite advantage in the field.

Take a look at the Lucent OR2T40A. It's a 0.35 micron device which
runs a 3.3V core (5V tolerant I/O's) It will run the same speed as the
five volt parts, but gives a very satisfactory reduction in power
consumption. It is also in full production.

Correct me if I'm wrong, but Lucent appear to be the only FPGA vendor
with same speed 5V and pure 3.3V parts (available today).

Stuart
Article: 5399
Subject: Re: Inversion 1/T with registers
From: peter@xilinx.com (Peter Alfke)
Date: Thu, 13 Feb 1997 09:20:44 -0700
Links: << >>  << T >>  << A >>
In article <01bc17f5$32984e80$745c34c1@ensbr.bretagne.ens-cachan.fr>,
"bergeon" <bergeon@bretagne.ens-cachan.fr> wrote:

> Can someone tell me where I can find a structure of a system which can do a
> 1/T
> (T is in BCD) with registers.
> 
Yves,
there are several methods, and your choice depends on:
 required accuracy
 available time for converson
 available resorces, registers, counters etc. In other words: acceptable cost
 acceptable design effort.

You can kludge together something that is slow and crude and wasteful, or
you can dig deeper and design something far more elegant.

I would be tempted fo first convert your decimal numbers to binary, then
get successive reciprocal bits by successive approximation multiplication,
one bit per clock or per two clocks.

But you can also emulate the human longhand method: keep it in BCD,
normalize, subtract from 1.000000 as often as you can ( that gives you the
first digit ) then shift one decimal position, and repeat...

Needless to say, all of this can easily be done in an FPGA at >20 MHz
clock rate.

Peter Alfke, Xilinx Applications


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