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Article: 5425
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Article: 5427
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Article: 5428
Subject: What kind of functions mostly implemented using FPGAs?
From: r.m.muench@ieee.org (Robert M. Muench)
Date: Sat, 15 Feb 1997 12:34:02 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm interested in the set of functions which get mostly implemented
using FPGAs? And in any information where are the biggest problems
faced when using FPGAs.

Robert M. Muench
SCRAP EDV-Anlagen GmbH, Karlsruhe, Germany

--> Answer to: r.m.muench+ieee.org <--
--> replace the + with @           <--

PGP-Fingerprint:
08 E9 EE 9F 33 ED 46 11  A5 CD BE FC 9D ED 75 14
Article: 5429
Subject: Re: HELP: XC4000 download cable
From: timolmst@cyberramp.net
Date: Sat, 15 Feb 1997 16:32:55 GMT
Links: << >>  << T >>  << A >>
Hi David,

I can't answer for the XC4000 family, but I've programmed (uploaded)
XC3000 parts using the serial protocol, and there is a strandity that
they don't mention in the book with these parts. When you have shifted
all the bits from your MCS file, DONE will probably NOT be high. You
have to continue shifting ones (1's) until you get a high on DONE.
After each one you write, check DONE, and quit when it goes high. For
the XC3030, it takes 16 extra clocks.

Don't know if this will help with the XC4000 family, but you don't
have much to loose to try it.


David Charles Hirschfield <dch+@andrew.cmu.edu> wrote:

>I'm trying to build an xchecker cable replacement and an xchecker
>program replacement for programming Xilinx XC4003A Demo boards, I have
>some documentation on the pin connections needed but I need some
>clarification.

>The documentation says that for the XC4000 the programming/downloading
>process is as follows:

>Raise the PROG line, wait some indeterminate time, and then lower it to
>begin programming the board.

>Toggle the CCLK line while feeding data to the DIN line until all the
>bits in the .bit file have been sent.

>If everything went OK, the DONE line should go high, signaling that the
>board got the program.

>Have I got this routine right?
>Are all my high/low signals correct?
>Does anyone have more information on this process? Specifically, does
>anyone know exactly what timings and settings the board requires?

>Thanks for any help,
>-David Hirschfield

>+-===========================================================================-+
>|                                                --== e-mail ==--             |
>|     _/_/_/      _/_/    _/   _/  _/_/_/       dch@andrew.cmu.edu            |
>|    _/    _/  _/    _/  _/  _/   _/                   or                     |
>|   _/    _/  _/_/_/_/  _/ _/    _/_/       dhirschfield@giss.nasa.gov        |
>|  _/    _/  _/    _/  _/_/     _/                                            |
>| _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
>|                                          http://srv.res.cmu.edu/~dch/       |
>+-===========================================================================-+
> 


Article: 5430
Subject: Re: Serial Communication Controller Design
From: zx80@dgiserve.com (Peter)
Date: Sat, 15 Feb 1997 20:42:43 GMT
Links: << >>  << T >>  << A >>

>1) You can't make an 11-bit UART. How do you do that? With programmable
>logic, of course!

One does not often need 11-bit UARTs :)

But this reminds me of a job I did a while ago, involving a 122-bit
UART! This was for comms with some obscure Japanese PLC. I did it with
a Xilinx 3064.

But that UART had to do clever things with the 122-bit packet anyway.


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5431
Subject: Re: Lucent Foundry (PC) bug
From: eteam@aracnet.com (bob elkind)
Date: Sat, 15 Feb 1997 20:49:01 -0000
Links: << >>  << T >>  << A >>
In article <MPG.d6e5d4fa16018979897f3@nntp.aracnet.com>, eteam@aracnet.com 
says...
> In case you didn't know, the latest version (9.0x) of
> Lucent (Orca) Foundry has the following minor bug:
> 
> Epic (EditLCA equivalent :-) ) won't display the guts of
> the edited device if your Windows display is configured
> for more than 256 colours.

As a followup,
I'm running NT4 SP2 (although I don't think the problem is
specific to NT), on an Intel processor.  I've installed the
9.0a patch (from CD) as well as the 9.0d patch (downloaded).

Can anyone confirm that the problem does or doesn't present
itself on the W95 OS?

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5432
Subject: Re: FPGA power dissipation
From: eteam@aracnet.com (bob elkind)
Date: Sat, 15 Feb 1997 21:12:36 -0000
Links: << >>  << T >>  << A >>
I think Peter has some strong opinions, and has left a lot of room
for respectful disagreement.  Rather than try to point out every
detail on which his opinions might not be universally held,
I'll offer the following:

1.  I'd rather have *some* consistent data, or "feedback", on
expected power dissipation than have *none*.  In short order, it
will become readily apparent whether the data is absolutely
correct (within a tolerance), is a useful indicator (there is a
correlation between the report numbers and reality), or the
feedback is total rubbish (no useful correlation, etc.).

2.  I have to believe, if the first attempts are less than
perfect, that successive attempts at reporting anticipated
power dissipation will improve on the first ones.

3.  20% of the effort required to devise an exquisite power
estimator would yield 80% to 90% of the benefits of the
exquisite estimator, and I am confident that that would
be generally useful and helpful to the vast majority of FPGA
designers (including myself).

-- Bob

In article <33002a39.2684074@news.alt.net>, zx80@dgiserve.com says...
> 
> I think that FPGA dynamic Icc is high because of all the "superfluous"
> nets which are toggled, rather than due to any property of the silicon
> process used to make the logic elements.
> 
> The large (relative to an ASIC, for example) number of toggled nets is
> the result of two factors:
> 
> 1. Connections are routed via fixed lines and via muxes, rather than
> directly;
> 
> 2. Good FPGA design practice requires the use of a *global* clock net
> (which goes all over the chip!) and use of clock-enable inputs on
> D-types to select which one actually gets clocked. So practically the
> whole chip is bobbing up and down at 4MHz, 50MHz, or whatever.
> 
> I therefore don't see how one can easily do dynamic Icc estimation
> based purely on a netlist. To get a figure which is anywhere near in
> the right area, one would need to take account of *where* everything
> is routed, and the capacitance of each long line, each mux's I/O, etc.
> 
> 
> Peter.

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5433
Subject: multi-vendor VHDL design tool
From: eteam@aracnet.com (bob elkind)
Date: Sat, 15 Feb 1997 21:39:39 -0000
Links: << >>  << T >>  << A >>
My apologies if anyone is offended by this posting, please
accept this in the spirit with which it is offered.

OrCAD is developing a VHDL design tool, with support for several
of the FPGA vendors and technologies we all know and love.
These include (but not limited to) Xilinx, Actel, AMD, Altera,
and Lattice.

The offering price, I believe, is about $5K US.
More information may be found at the Orcad web site
  http://www.orcad.com/products/exprssds.htm

I am doing work for Orcad on this project as a consultant,
specifically to help develop and test support for one or more
FPGA vendors.  Truth in posting!

I've been hoping for a retargetable (technology-independent) 
and affordable design tool for FPGAs ever since Neocad was
acquired by Xilinx.  I think Express will fulfill most of my
hopes and desires, although I don't presume that Express is
the *only* product to do so.

The back-end layout tools are still required (XactStep, etc.).
Mixed schematic/VHDL code is handled seamlessly.
Express includes all Capture capabilities, so it includes a
full-blown schematic editor/netlister.

Finally, these are my opinions.  I am not speaking for
Orcad.  And I am providing services to Orcad, for hire,
although this posting is not part of those paid services!

If you are interested in further details, check the web page.
If you are interested in tire-kicking or beta-testing,
contact Mike Lottridge at 503.671.9500 or MikeL@OrCAD.com

Again, I aplogize if this comes across as shilling, this is
not my intent.

Regards,

Bob Elkind

****************************************************************
Bob Elkind                              mailto:eteam@aracnet.com 
7118 SW Lee Road               part-time fax number:503.357.9001
Gaston, OR 97119           cell:503.709.1985   home:503.359.4903
****** Video processing, R&D, ASIC, FPGA design consulting *****
Article: 5434
Subject: Re: X84 board VHDL examples
From: "jjfakas@erols.com"@erols.com
Date: Sat, 15 Feb 1997 14:52:24 -0800
Links: << >>  << T >>  << A >>
Jim Roehn wrote:
> 
> Richard Schwarz wrote:
> > APS is starting a VHDL examples link and is putting up VHDL examples 
> on the following topics using XILINX FPGAs:
> .....
> > They are also encouraging students and other users of the board
> > to post their examples, including student Labs done with the
> > board.
> 
> Could you tell us the URL of these postings please?

Jim,

I know the URL for the X84 stuff:

http://www.erols.com/aaps/prog.htm
Article: 5435
Subject: Re: HELP: XC4000 download cable
From: "jjfakas@erols.com"@erols.com
Date: Sat, 15 Feb 1997 15:20:45 -0800
Links: << >>  << T >>  << A >>
Dave, 

It sounds like what you are doing is right, but you should make sure of 
the following:

1) You have the reccomended pull up resistors on the appropriate lines.
(init, done, prog)

2) APS has an X84 PC ISA fpga kit which sells stand alone for around 
$250.00. The kit comes complete with schematics and directions on exactly 
how to do this from both the ISA bus and from an external cable. The kit 
also gives C code examples which take the .rbt files and checks the chip 
type and downloads it. It can save tons of time and is well worth the 
price in the time alone. The company has also started an examples page 
specifically for Xilinx VHDL using the X84 board. The examples can 
easily be ported to other designs. The examples look like they are on 
some relavent topics too, like spread spectrum, filtering, etc..

The URL is:

http://www.erols.com/aaps  







David Charles Hirschfield wrote:
> 
> I'm trying to build an xchecker cable replacement and an xchecker
> program replacement for programming Xilinx XC4003A Demo boards, I have
> some documentation on the pin connections needed but I need some
> clarification.
> 
> The documentation says that for the XC4000 the programming/downloading
> process is as follows:
> 
> Raise the PROG line, wait some indeterminate time, and then lower it to
> begin programming the board.
> 
> Toggle the CCLK line while feeding data to the DIN line until all the
> bits in the .bit file have been sent.
> 
> If everything went OK, the DONE line should go high, signaling that the
> board got the program.
> 
> Have I got this routine right?
> Are all my high/low signals correct?
> Does anyone have more information on this process? Specifically, does
> anyone know exactly what timings and settings the board requires?
> 
> Thanks for any help,
> -David Hirschfield
> 
> +-===========================================================================-+
> |                                                --== e-mail ==--             |
> |     _/_/_/      _/_/    _/   _/  _/_/_/       dch@andrew.cmu.edu            |
> |    _/    _/  _/    _/  _/  _/   _/                   or                     |
> |   _/    _/  _/_/_/_/  _/ _/    _/_/       dhirschfield@giss.nasa.gov        |
> |  _/    _/  _/    _/  _/_/     _/                                            |
> | _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
> |                                          http://srv.res.cmu.edu/~dch/       |
> +-===========================================================================-+
>

Article: 5436
Subject: Re: HELP: XC4000 download cable
From: "jjfakas@erols.com"@erols.com
Date: Sat, 15 Feb 1997 15:20:45 -0800
Links: << >>  << T >>  << A >>
Dave, 

It sounds like what you are doing is right, but you should make sure of 
the following:

1) You have the reccomended pull up resistors on the appropriate lines.
(init, done, prog)

2) APS has an X84 PC ISA fpga kit which sells stand alone for around 
$250.00. The kit comes complete with schematics and directions on exactly 
how to do this from both the ISA bus and from an external cable. The kit 
also gives C code examples which take the .rbt files and checks the chip 
type and downloads it. It can save tons of time and is well worth the 
price in the time alone. The company has also started an examples page 
specifically for Xilinx VHDL using the X84 board. The examples can 
easily be ported to other designs. The examples look like they are on 
some relavent topics too, like spread spectrum, filtering, etc..

The URL is:

http://www.erols.com/aaps  







David Charles Hirschfield wrote:
> 
> I'm trying to build an xchecker cable replacement and an xchecker
> program replacement for programming Xilinx XC4003A Demo boards, I have
> some documentation on the pin connections needed but I need some
> clarification.
> 
> The documentation says that for the XC4000 the programming/downloading
> process is as follows:
> 
> Raise the PROG line, wait some indeterminate time, and then lower it to
> begin programming the board.
> 
> Toggle the CCLK line while feeding data to the DIN line until all the
> bits in the .bit file have been sent.
> 
> If everything went OK, the DONE line should go high, signaling that the
> board got the program.
> 
> Have I got this routine right?
> Are all my high/low signals correct?
> Does anyone have more information on this process? Specifically, does
> anyone know exactly what timings and settings the board requires?
> 
> Thanks for any help,
> -David Hirschfield
> 
> +-===========================================================================-+
> |                                                --== e-mail ==--             |
> |     _/_/_/      _/_/    _/   _/  _/_/_/       dch@andrew.cmu.edu            |
> |    _/    _/  _/    _/  _/  _/   _/                   or                     |
> |   _/    _/  _/_/_/_/  _/ _/    _/_/       dhirschfield@giss.nasa.gov        |
> |  _/    _/  _/    _/  _/_/     _/                                            |
> | _/_/_/    _/    _/  _/       _/_/_/             --== WWW ==--               |
> |                                          http://srv.res.cmu.edu/~dch/       |
> +-===========================================================================-+
>

Article: 5437
Subject: Re: Xilinx programming...(long)
From: Scott Kroeger <Scott.Kroeger@mail.mei.com>
Date: Sat, 15 Feb 1997 20:14:13 -0600
Links: << >>  << T >>  << A >>
David Charles Hirschfield wrote:

<snip>

> We were able to get some xchecker replacement code that works with
> XC3000 and XC2000 series FPGA boards written by Scott Kroeger.
> Unfortunately we have been unsuccessful in programming XC4000 boards
> with that code.
> 
> In the rather meager documentation we have we've uncovered some
> information about the cable connections and programming cycle...but not
> nearly enough.
> 
> Does anyone know of in depth documentation on programming xilinx boards,
> making your own download cables or anything else even remotely related
> to what's in this post?

Xilinx databook is a necessary and sufficient source of configuration
information.  But I guess I'll save you some effort.  I hacked the
enclosed program together as a guide.  It has not been tested.  It
hasn't even been compiled.  I believe the original XC2000/3000 program
was intended for QuickC, which may no longer exist.  This program
includes the same headers and so will need the same tweaks you used to
get the other program running.

I may have inverted the sense of a pin or gotten a bit position in a
register wrong (or gotten the register addresses wrong). I may have
neglected a pullup or pulldown on some configuration related pin. 
You've been warned!

Unlike the XC2000/3000 program I wrote, this one presumes that data is
in binary format (that's the way I do it these days, it's smaller,
faster and easier to understand).  You can hack out the Intel hex reader
portion of the previous program to produce something that just converts
an Intel hex file into a binary file or if you wish I can dig up the
source for the program I use.

The loop counts used for Init and Busy timing are just fill in values. 
If you use CPU loop timing you should figure out what values make sense
for your computer.

After configuration is complete you may wire up the internals of the
FPGA to allow communication with the PC over the printer port in
whatever mode you choose.  The configuration code will work in the basic
unidirectional mode, but you should take advantage of bidirectional, ECP
or EPP modes for communications after configuration.

Hope this helps,
Scott

Program follows (tab = 4 spaces)...
/******************************************************************************
   A simple program to download binary Xilinx bitmap files to
   Xilinx 4K devices in async peripheral mode via LPT1.
   
   Scott Kroeger Copyright 1997 (use it, but remember where it came
from)

Wiring:

LPT		LPT		Dir		Xilinx 4K	PC Port			Bit-to-Pin
Pin		Name			Pin			Register.Bit	Sense
---		----	---		-----		------------	---------
1		Stb		   ->	*WS			Control.0		Inverted
2		D0		<--->	D0			Data.0
3		D1		<--->	D1			Data.1
4		D2		<--->	D2			Data.2
5		D3		<--->	D3			Data.3
6		D4		<--->	D4			Data.4
7		D5		<--->	D5			Data.5
8		D6		<--->	D6			Data.6
9		D7		<--->	D7			Data.7
10		*Ack	<-		Done		Status.6
11		Busy	<-		*Busy		Status.7		Inverted
12		PE		<-		*Init		Status.5
13		SLCT	<-		?			Status.4
14		AFD		   ->	*Program	Control.1		Inverted
15		*Err	<-		?			Status.3
16		*Init	   ->	CS1			Control.2
17		SLIN	   ->	*CS0		Control.3		Inverted
18		Gnd		  -		Gnd
19		Gnd		  -		Gnd
20		Gnd		  -		Gnd
21		Gnd		  -		Gnd
22		Gnd		  -		Gnd
23		Gnd		  -		Gnd
24		Gnd		  -		Gnd
25		Gnd		  -		Gnd

Control.4 = data port direction, 0 = output
Control.5 = interrupt enable, 1 = enable

* = active low
? = any I/O pin

Depending on the construction of your particular parallel port, you may
need pullup resistors on the status inputs and perhaps even on the
control outputs. 1K ohm will probably do the trick.

Other Xilinx connections:

M1 = 4.7K pulldown to Gnd (M2 and M0 have weak pullups and may be left
unconnected)

*RS (I don't recall if this has an internal weak pullup during
configuration, if not
add a 47K pullup).

******************************************************************************/

#include <stdio.h>
#include <ctype.h>
#include <fcntl.h>
#include <conio.h>

#define PortBase 0x378
#define PortRegisterPitch 1

//-----------------------------------------------------------------------------
#define Data PortBase + 0

//-----------------------------------------------------------------------------
#define Status PortBase + 1 * PortRegisterPitch

// bit defs
#define Init 0x20		// 1 = initialization complete
#define	Done 0x40		// 1 = configuration done
#define Busy 0x80		// 1 = busy

//-----------------------------------------------------------------------------
#define Control PortBase + 2 * PortRegisterPitch

// bit defs
#define WS		1		// 1 = write
#define CS0		2		// 1 = select
#define	CS1		4		// 1 = select
#define Prog	8		// 1 = program
#define IntEn	0x10	// 1 = enable interrupts
#define DataDir	0x20	// 1 = input

#define Idle	0
#define Write	WS + CS0 + CS1
#define Program Prog

//-----------------------------------------------------------------------------
#define InitTimeLimit	100000
#define	BusyTimeLimit	10000

main(argc,argv)

char *argv[];
int argc;

{
	FILE *in;
	register long int Byte, Timer;

	printf("Xilinx 4K downloader V0.1\n");

	if (argc != 2) {
		printf("Correct usage is: download filename\n");
		exit(1);
	}

	in = fopen (argv[argc-1],"rb");
	if(in == NULL){
		printf("Can't open input file: %s\n",argv[argc-1]);
		exit (2);
	}

	outp(Control,Program);
	outp(Control,Idle);
	Timer = 0;
	while ( (inp(Status) & Init) == 0) {
		if (Timer++ > InitTimeLimit) {
			printf("Init did not go high\n");
			exit(3);
		}
	}

	while ((Byte=getc(in)) != EOF) {
		Timer = 0;
		while (inp(Status) & Busy) {
			if(Timer++ >= BusyTimeLimit) {
				printf("Busy did not go high.\n");
				exit(4);
			}
		}
		outp(Data,Byte);
		outp(Control,Write);
		outp(Control,Idle);
	}
	if (inp(Status) & Done){
		printf("Done!\n");
	}
	else {
		printf("Done did not go high.\n");
	}

	fclose(in);
	return (0);
}
Article: 5438
Subject: Re: Random Number Generators with Xilinx FPGA xc4000 series
From: Richard Schwarz <aaps@erols.com>
Date: Sat, 15 Feb 1997 22:42:52 -0500
Links: << >>  << T >>  << A >>
I read it, and it was a good paper Peter !


Richard Schwarz


Peter Alfke wrote:
> 
> In article <33006F03.58C1@geocities.com>, Christos Dimitrakakis
> <olethros@geocities.com> wrote:
> 
> > Anyone got any info on RNGs?
> > Since I'm only generating a 6-bit number with it
> > I could just use a simple counter scheme for it that runs @8Mhz
> > while using one of the other clock outputs provided in the chip,
> > say the 490Hz one, for the rest of the circuitry.
> > Will that reduce the decorrelate the timing of the RNG from the
> > rest of the chip?
> >
> There is only one oscillator running inside the chip. So all its outputs
> are correlated.
> Therefore, you must use one external oscillator for your scheme.
> 
> I would prefer a Linear Feedback Shift Register counter (LFSR). You can
> make them extremely long in a few XC4000 CLBs. In August 1995, I published
> a 6-page App Note called "Efficient Shift Registers, LFSR Counters, and
> Long Pseudo-Random Sequence Generators". It is available on the Xilinx Web
> pages.
> 
> Peter Alfke, Xilinx Applications
Article: 5439
Subject: The TechExpo Calendar of Science & Technology Events
From: "N. Gat" <oksi@cerfnet.com>
Date: Sun, 16 Feb 1997 01:01:44 -0800
Links: << >>  << T >>  << A >>
Hello,

To those unfamiliar -- TechExpo provides a free Calendar of science &
technlogy event.  This is the largest such calendar on the Internet,
including over 2,000 events, organized in chronological order, and
searchable by location, sponsoring organization, event name, or other
key words.  The calendar is visited daily by thousands of scientists,
engineers, and technical managers.  Most technical societies and
organizations poste their events there.

Free listing to qualified organizations.  Nominal charge to commercial
entities for posting short courses, seminars, workshops of commercial
nature.

URL:  http://www.techexpo.com

Regards,

N. Gat, Ph.D.
Article: 5440
Subject: Re: FPGA power dissipation
From: zx80@dgiserve.com (Peter)
Date: Sun, 16 Feb 1997 10:40:33 GMT
Links: << >>  << T >>  << A >>
Bob, I am very happy to hear myself being corrected on something I did
not know. But can you be more specific? Yes, I do have strong views on
certain things. But what's wrong with that?

I give you one example. I have just ported an XC3090 design to an
ASIC. 

I don't know what geometry a XC3090A-5 uses, but the ASIC is "0.7
micron", probably not too different from the FPGA.

Well, the FPGA design was drawing about 30mA, nearly all of this being
dynamic Icc. This same Icc, more or less, was found when doing the
design in a 3064, 3064A, 3042, 3042A, 3142 over 2-3 years. The
3042/3142 parts were down to about 15mA.

The ASIC, done from the same ex-Xilinx netlist used for the FPGA,
draws 2.5mA under identical dynamic conditions. 10x less.

Both tests were done at 5V.

How else can one explain this?

Incidentally, I could have got the ASIC Icc down by possibly another
2x if I did not have to use so many global clock nets, and gated
clocks instead. I had to use global clock nets for the FPGA design
because the thing just won't work otherwise, usually. But this is
always the big problem when prototyping a supposedly low-power ASIC
using an FPGA.

>I think Peter has some strong opinions, and has left a lot of room
>for respectful disagreement.  Rather than try to point out every
>detail on which his opinions might not be universally held,
>I'll offer the following:
(snip)

part of my original post:

> I think that FPGA dynamic Icc is high because of all the "superfluous"
> nets which are toggled, rather than due to any property of the silicon
> process used to make the logic elements.
 


Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiserve.com.
Article: 5441
Subject: Re: Mealy/Moore state machines
From: sarfati@netvision.net.il
Date: Sun, 16 Feb 97 08:32:38 PDT
Links: << >>  << T >>  << A >>

Hi,

A Meally state machine has outputs which are combinatorial product of current 
state and inputs, while a Moore state machine has outputs which are only 
dependent on current state.

IMO, a Meally state machine is usually a bad choise for an FPGA, since it 
generates an async design and its outputs can have glitches and setup/hold 
timing problems. It's even worse if you want to convert your FPGA into an ASIC 
(most ASIC designs must be fully syncronous in order to be checkable).

I think the best way to design a state-machine is to use a one-hot Moore state 
machine, assigning a separate FF to each desired output signal; this approach 
gives good speed, predictable delays and clean signals.
 
However, sometimes you can't afford the additional clock(s) required for a 
fully sync design - just be sure you are aware of all (usually external) 
timing constraints.

			Regards
			Assaf Sarfati


Article: 5442
Subject: Re: HELP: XC4000 download cable
From: Peter Alfke <peter@xilinx.com>
Date: Sun, 16 Feb 1997 12:47:48 -0700
Links: << >>  << T >>  << A >>
Just read pages 4-68 and 4-69 of the data book. They contain all the
timing information you might need.
Operating the PROGRAM pin is only needed when you want to re-program an
already configured part.

And I thought that we had always supplied extensive documentation for
all programming modes...

Peter Alfke, Xilinx Applications
Article: 5443
Subject: Implementing Phase Comparator in XC7354
From: "John G. Wohlbier" <wohlbier@softswitch.com>
Date: Sun, 16 Feb 1997 20:25:37 -0600
Links: << >>  << T >>  << A >>
First of all excuse me if this is not the group for CPLD discussion.  I looked
for a group of the pld variety and found none.

We are trying to implement a phase comparator in our XC7354.  More specifically
we want to functionally duplicate Phase Comparator 2 in the 4046 CMOS part.  I
have entered and simulated the design successfully.  My concern is that on fitting
it recognizes the combinational loops (there are 4 NAND latches) and mentions
redundancy should be added and minimization turned off. I have turned off the
minimization, but am unsure about the redundancy comment.  If anyone has gone
through this exercise I would appreciate your experience.  Is there redundancy
built into this circuit already (you can see the circuit in the CMOS Data Book.)
I know the key to simulating it was setting up the proper initial conditions, will
I have to do this somehow on implementation?  We will test it within the week which
will tell us if it works, but I wanted to make sure there is nothing I am missing.

Thanks,

john g. wohlbier
Article: 5444
Subject: Re: Altera Max Plus 2 Software bug
From: Scott Redman <sredman@pacbell.com>
Date: Sun, 16 Feb 1997 22:26:10 -0800
Links: << >>  << T >>  << A >>
Contact Altera's Customer Support, I believe there is a patch for
this problem.

-- Scott

> 
> Hello Max Plus 2 User
> 
> I have a Problem with the Software version 7.1
> My Problem ocured also with version 7.0
> 
> The Problem is: If i compile a 10K design i get an internal error at 5% in the
>                 SNF Extractor.
> 
> If i compile the design with a 10KA or MAX 7000 or MAX 8000 it works.
> Only with 10K i have those problems.
> 
> I send you a small GDF File wit my Problem.
> 
> My System : Win 95
>             Pentium 166 Mhz
>             90 Mb Ram
> 
> If there is anybody out there who knows something about this let me know.
> 
>   Thanks a lot
>
Article: 5445
Subject: Re: Mealy/Moore state machines
From: Ray Andraka <randraka@ids.net>
Date: Sun, 16 Feb 1997 23:06:46 -0800
Links: << >>  << T >>  << A >>
sarfati@netvision.net.il wrote:
> ....
> IMO, a Meally state machine is usually a bad choise for an FPGA, since it
> generates an async design and its outputs can have glitches and setup/hold
> timing problems. It's even worse if you want to convert your FPGA into an ASIC
> (most ASIC designs must be fully syncronous in order to be checkable).
>....

Plus the architecture supports a Moore machine better.  No logic follows
the flop in the CLB, so by definition, the Mealy machine needs an
additional CLB and it's associated delay to decode the state.  On the
otherhand, the logic for a Moore machine can often be incorporated right
in the same CLB as the flop (especially if a one hot design is used) 

-Ray Andraka, P.E.
Chairman, the Andraka Consulting Group
401/884-7930     Fax 401/884-7950
email randraka@ids.net
http://www.ids.net/~randraka
Article: 5446
Subject: Cypress says good-bye to Anti-Fuse
From: Kayvon Irani <kirani@cinenet.net>
Date: Mon, 17 Feb 1997 00:09:52 -0800
Links: << >>  << T >>  << A >>
Hi every one:

	After Xilinx left the anti-fuse market a couple of months ago, Cypress 
	also decides to stop marketing its anti-fuse line of FPGAs referring
	their anti-fuse customers to Quicklogic. It's hard to figure out the
	main reason behind this decision by  reading Quicklogic and Cypress'
	press releases. Is anti-fuse running out of steam ? Does Cypress know
	some thing we don't know? 

	Regards,
	Kayvon Irani
	Los Angeles
Article: 5447
Subject: Re: Mealy/Moore state machines
From: Christoph Grimm <grimm@informatik.uni-frankfurt.de>
Date: Mon, 17 Feb 1997 10:45:11 +0100
Links: << >>  << T >>  << A >>
P Nibbs wrote:

> I was wondering if someone could point out the advantages/disadvantages
> and reasons between choosing between Mealy or Moore state machines.
> 
> How does it affect the performance of the state machine, and when
> synthesised, what are the effects on the resulting circuitry?
> 
> Thanks in advance for any advice,
> 
> Cheers,
> 
> Phil.


The difference is, that the ouput of Moore-Machines is only dependent
on the current state of the Automata. This requires more states, as
each possible output requires its own state. An advantage is, that
the the output of a Moore Machine is independent from changes of
the input vector, so that the behaviour of a Moore machine in complex
systems may be less critical.

-- 
Christoph Grimm              

... One hour of programming saves one minute thinking
Article: 5448
Subject: Re: XC6200 config resources
From: Bill Wilkie <bill.wilkie@xilinx.com>
Date: Mon, 17 Feb 1997 10:28:09 +0000
Links: << >>  << T >>  << A >>
Hi Oliver,

The XC6200 family datasheet on the Xilinx web page has recently been
updated, so it might be worth having a look at that.

To answer your specific question, all the 6200 cell functions and
routing muxs are controlled by SRAM bits. All these SRAM bits can
be written and read by a microprocessor through the built-in FastMAP
parallel interface. This allows groups of configuration bits to
be accessed together as 8-bit, 16-bit or 32-bit words. Each byte has
its own individual memory-mapped address.

The Wildcard registers allow a write of identical data to a group of
bytes using only a single write cycle. This is described in the
datasheet.

Bill Wilkie,
Xilinx.
Article: 5449
Subject: Re: HELP: XC4000 download cable
From: Gerhard Hoffmann <ghf@berlin.snafu.de>
Date: Mon, 17 Feb 1997 05:33:35 -0800
Links: << >>  << T >>  << A >>
David Charles Hirschfield wrote:

> The documentation says that for the XC4000 the programming/downloading
> process is as follows:
 
> Raise the PROG line, wait some indeterminate time, and then lower it to
> begin programming the board.

I don't have the data book here, but i think you must rise prog-
again before you start feeding the chip or it will stay in 
configuration clear state, no matter what programming data you apply.

(prog is lo active!)

> Toggle the CCLK line while feeding data to the DIN line until all the
> bits in the .bit file have been sent.

Gerhard

--
Gerhard Hoffmann	dk4xp


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