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Messages from 4975

Article: 4975
Subject: Re: Motorola FPGA anyone ?
From: akugel@t-online.de (Andreas Kugel)
Date: 7 Jan 1997 21:49:57 GMT
Links: << >>  << T >>  << A >>
>Hi Andreas,                                                       
>                                                                  
>while I can't help you with the group buy, I was curious about    
>your experiences with the Moto FPGA. Are you using the free            
>software ? Which design capture method are you using (Viewlogi/        
>OrCad/VHDL/Verilog)?                                                   
>                                                                       
>Just wondering, I have tooled with the APR tool a bit and              
>got started on a netlist generator for one of the tools I'm            
>use sometime "diglog". Since diglog is free and the APR is             
>free, this would be a good way to get into FPGAs for people.           
>However, I think it's hard to get the parts. In the US,                
>Universities and get free parts from Moto, but this doesn't            
>help everyone.                                                         
>                                                                       
>Anyway, do you think there is much interest in a MPA netlister         
>and libraries for free CAD tools like diglog ?                         
                                                                       
I use the free software (current version is 2.3)
I tried some register intensive designs with not much logic (max 5
levels deep) and got a 95% utilisation @ 40MHz with a MPA1016
and a 75% utilisation @ 40Mhz (larger but similar design) with
a MPA1036 (autolayout estimations).

Place&ROute prcessing time are up to 2 hours on a 90MHz Pentium/32MB.

The chips are available (at least I got a quotation) from Future
Electronics.

Motorola donated a free sample (MPA1036HI).

I use a standard EDA schematic editor as front-end tool. To write 
a symbol library is quite easy, just port the MPA library to your
schemtaic tool. 
The EDIF output of my Ulticap editor needs some postprocessing but then
it works OK.

A free schemtic tools would be nice, but if you already have a schematic
entry you can use that.

Comments?

Andreas


-- 
Andreas Kugel,  Karolinenstr. 4  
76135 Karlsruhe, Germany
Phone: (49) 721 377865, Fax (49) 721 937 49 12
E-mail: akugel@t-online.de

Article: 4976
Subject: Motorola 68HC16 background debugger
From: wctech@why.net (Larry Chen)
Date: 8 Jan 1997 02:03:46 GMT
Links: << >>  << T >>  << A >>
If you are using or going to use 68HC16 microcontroller, you may
be interested to look at HC16BGND, an advanced programmer’s 
interface that helps you to develop, test, and refine your 
assembly language programs for MOTOROLA’s 68HC16 microcontrollers.
The key features include:
- Run under MS Windows
- Interface through PC’s parallel port
- Motorola suggested 10 pin target connector
- Download and debug HC16 assembly language program in S19 or HEX format
- trace through your code by step through or step over
- set up to 100 breakpoints
- On-screen editing of register and data memory
- On-fly assembly of instruction using mnemonics in program memory
- Open infinite Register, Program, and Data windows
- Watch window so that you can watch important variables
- Exchange data through Windows clipboard
- File I/O which can be used to automatically read a hex input file
  into the file and write the result to an output file.
- Easy to use.  Just click on the menu with left mouse or click on 
  the windows’ area.  Everything is self-explained
- Convenient and easy to install due to its parallel port interface.
  You can use laptop to do an on-site demonstration of you products
- Low cost
- 30 day money back guarantee and one year product warranty
For more information or need a demo program,
see http://users.why.net/wctech/hc16bgnd.htm, 
or FTP to FTP.WHY.NET/FTP/PUB/USERS/WCTECH, 
or send email to WCTECH@WHY.NET

Larry Chen
WC Technology
Article: 4977
Subject: Re: Oscillator with PLD's or FPGA's
From: Cord Elias <cord@ind.rwth-aachen.de>
Date: Wed, 08 Jan 1997 11:31:24 +0100
Links: << >>  << T >>  << A >>
Kardos, Botond wrote:
> 
> Hi!
> 
>    Have anyone ever realized a quartz controlled oscillator with a PLD
> or an FPGA without other IC's ? I know that the simplest oscillator with
> a 74hc04 won't work (the quartz is connected parralel to the inverter),
> but it work's with 74hcu04 because this circuit is unbuffered
> (single-stage inverter).
>    Thx for any ideas !
> 
> --
> Kardos, Botond  -  at Innomed Medical Co. Ltd. in Hungary
> eMail: kardos@mail.matav.hu
> phone/fax: (36 1) 268-0934

Hello,

I did such a thing with a xilinx-fpga (xc3000 series) without
any problem; these parts have special circuity on-chip for
that purpose.

-- 
Cord Elias
Article: 4978
Subject: Re: design should fit, but it doesn't
From: Thomas Hadlich <hadlich@infaut.et.uni-magdeburg.de>
Date: Wed, 08 Jan 1997 11:33:47 +0100
Links: << >>  << T >>  << A >>
I am replying to Eric Edwards reply, so maybe I am missing some
parts of the original request..

But my suggestion would be to try to change the state machine encoding.
ASYL+ is using the "compact" encoding by default. "One-hot" encoding
would use more serial cells, and probably use less logic cells.
Related to this is, when you use some kind of encoding within your
original design, the synthesizer may not recognize this, and may 
produce not optimal code. 
I had best results when using either enumerated or integer type for
state varibles (signals) and then choosing the encoding style in the
synthesis process.. 

Thomas 
--
-------------------------------------------------------------------
|    Thomas Hadlich    hadlich@infaut.et.uni-magdeburg.de         |
|                      http://infaut.et.uni-magdeburg.de/~hadlich |
-------------------------------------------------------------------
Article: 4979
Subject: Re: ASICs Vs. FPGA in Safety Critical Apps.
From: Friedrich Beckmann <beckmann@item.uni-bremen.de>
Date: Wed, 08 Jan 1997 14:52:09 +0100
Links: << >>  << T >>  << A >>
Rich K. wrote:
> 
> James W. Swonger <jws@billy.mlb.semi.harris.com> wrote in article
> <5attn9$mkg@hearye.mlb.semi.harris.com>...
> >  If you're really interested in SEU-immune, high-rel FPGAs you should go
> > to the companies which are building Class S, rad hard versions of the
> > ACTEL form (Lockheed Martin, partnered with Actel) and Xilinx form
> > (Honeywell). These will be able to provide you with bit error rate,
> > total dose and other reliability and failure/fault analysis information
> > (presuming they care to, and that's not a given; they'll probably make
> > you pass through Marketing first to see if you're a customer or just a
> > babbler).
> >
> 
 
> Also, is Honeywell building the Xilinx compatible part?  Is there contact
> information on this?  I know Harris had a data sheet on some of these
> Xililinx devices a few years ago but I believe they dropped the part.
> 
> rk

A few weeks ago I tried to find a rad hard fpga device. 
ACTEL can provide you with rad hard devices. Due to a previous Xilinx 
design I tried to find a rad hard Xilinx Device and I went through
the marketing departments...

As far as I could find out, there is no rad hard Xilinx Device
available.

The application of this was a satellite. 

Fritz
 
* Friedrich Beckmann                                          *
* University of Bremen                  TEL: +49 421 218 4079 *
* FB1 - Institute for Microelectronics  FAX: +49 421 218 4434 *
Article: 4980
Subject: Re: Flex 8K boot-up problem
From: "Kardos, Botond" <kardos@mail.matav.hu>
Date: Wed, 8 Jan 1997 14:30:05 GMT
Links: << >>  << T >>  << A >>
Marcello Lajolo wrote:
> 
> Do you have assigned device correctly?
> It is necessary to specify in section "Device Options"
> of the menu "Assign" that you want a configuration scheme
> of type "Active Parallel Up/Down".
> 

   Thanx for the hint, you gave me the idea that I should check if the
configuration EPROM contains valid data. I my design everything was OK,
but for some other reasons the offset generation was wrong. So
everything's fine, thanx again !

   Botond

-- 
Kardos, Botond  -  at Innomed Medical Co. Ltd. in Hungary
eMail: kardos@mail.matav.hu
phone/fax: (36 1) 268-0934
Article: 4981
Subject: Oscillator with PLD's or FPGA's
From: "Kardos, Botond" <kardos@mail.matav.hu>
Date: Wed, 8 Jan 1997 14:36:35 GMT
Links: << >>  << T >>  << A >>
Hi!

   Have anyone ever realized a quartz controlled oscillator with a PLD
or an FPGA without other IC's ? I know that the simplest oscillator with
a 74hc04 won't work (the quartz is connected parralel to the inverter),
but it work's with 74hcu04 because this circuit is unbuffered
(single-stage inverter).
   Thx for any ideas !

-- 
Kardos, Botond  -  at Innomed Medical Co. Ltd. in Hungary
eMail: kardos@mail.matav.hu
phone/fax: (36 1) 268-0934
Article: 4982
Subject: FAQ
From: st7jp@Bayou.UH.EDU (,, ,)
Date: 8 Jan 1997 10:37:40 -0600
Links: << >>  << T >>  << A >>

Hi folks!  I'm new to this newsgroup and was wondering if
some sort of a FAQ exists that I can look up ?

Thanks a million!

sudhir
Article: 4983
Subject: Altera clique
From: Gabby Shpirer <gabby@isv.dec.com>
Date: Wed, 08 Jan 1997 19:27:52 +0200
Links: << >>  << T >>  << A >>
Hello Altera people,



I'm trying to compile an hirarchical design into 4 deferent devices

with no big success.



Our design combined from 4 blocks and we tried to put each block into a

deferent EPM7096LC68-12. 

What we did:

We had 4 blocks on the top scheme, and with the clique function we

attached to each block a deferent device.

At the end of the compilation, the compiler shouts that it didn't use

one of the devices but the project fit by putting two blocks in one

device, and that aint what we wanted.





Please if you can give us more info about partitioning a top design,

that can be a great help.







Thanx,



   Gabby.



Digital Jerusalem.



Mailto:gabby@isv.dec.com
Article: 4984
Subject: Re: Altera clique
From: Sundar Gopalan <sundar@com21.com>
Date: Wed, 08 Jan 1997 09:58:41 -0800
Links: << >>  << T >>  << A >>
Gabby Shpirer wrote:
> 
> Hello Altera people,
> 
> I'm trying to compile an hirarchical design into 4 deferent devices
> 
> with no big success.
> 
> Our design combined from 4 blocks and we tried to put each block into a
> 
> deferent EPM7096LC68-12.
> 
> What we did:
> 
> We had 4 blocks on the top scheme, and with the clique function we
> 
> attached to each block a deferent device.
> 
> At the end of the compilation, the compiler shouts that it didn't use
> 
> one of the devices but the project fit by putting two blocks in one
> 
> device, and that aint what we wanted.
> 
> Please if you can give us more info about partitioning a top design,
> 
> that can be a great help.
> 
> Thanx,
> 
>    Gabby.
> 
> Digital Jerusalem.
> 
> Mailto:gabby@isv.dec.com

The Altera Clique feature helps you acheive timing goals. 
If for some reason your initial compile did not meet 
these goals, you can list out the critical paths using the
timing analyzer and then add these paths using the Clique 
feature to optimize timing. The Clique function tries to 
keep the specific nodes together (Within a LAB).

Altera tools do not partition efficiently. (Actually none of 
FPGA tools that I know of partition very well) It is best if you 
partition the design yourself instead of letting the tools do 
the same.

Depending on your design entry (VHDL, Verilog, GDF, TDF) you 
can describe in a modular fashion so that they are compiled into
different devices. This way you can simulate as one block, but
synthesize into multiple devices.

Also if possible I would suggest you use one BIG device instead 
of using multiple devices even if it is more expensive approach.
(I am assuming that you are not using those BIG devices already!!)


Sundar Gopalan
Article: 4985
Subject: Re: Altera clique
From: Sundar Gopalan <sundar@com21.com>
Date: Wed, 08 Jan 1997 09:59:00 -0800
Links: << >>  << T >>  << A >>
Gabby Shpirer wrote:
> 
> Hello Altera people,
> 
> I'm trying to compile an hirarchical design into 4 deferent devices
> 
> with no big success.
> 
> Our design combined from 4 blocks and we tried to put each block into a
> 
> deferent EPM7096LC68-12.
> 
> What we did:
> 
> We had 4 blocks on the top scheme, and with the clique function we
> 
> attached to each block a deferent device.
> 
> At the end of the compilation, the compiler shouts that it didn't use
> 
> one of the devices but the project fit by putting two blocks in one
> 
> device, and that aint what we wanted.
> 
> Please if you can give us more info about partitioning a top design,
> 
> that can be a great help.
> 
> Thanx,
> 
>    Gabby.
> 
> Digital Jerusalem.
> 
> Mailto:gabby@isv.dec.com

The Altera Clique feature helps you acheive timing goals. 
If for some reason your initial compile did not meet 
these goals, you can list out the critical paths using the
timing analyzer and then add these paths using the Clique 
feature to optimize timing. The Clique function tries to 
keep the specific nodes together (Within a LAB).

Altera tools do not partition efficiently. (Actually none of 
FPGA tools that I know of partition very well) It is best if you 
partition the design yourself instead of letting the tools do 
the same.

Depending on your design entry (VHDL, Verilog, GDF, TDF) you 
can describe in a modular fashion so that they are compiled into
different devices. This way you can simulate as one block, but
synthesize into multiple devices.

Also if possible I would suggest you use one BIG device instead 
of using multiple devices even if it is more expensive approach.
(I am assuming that you are not using those BIG devices already!!)


Sundar Gopalan
Article: 4986
Subject: Re: Oscillator with PLD's or FPGA's
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 08 Jan 1997 13:38:16 -0700
Links: << >>  << T >>  << A >>
Xilinx XC3000 and XC31000 have an on-chip single-stage inverter,
intended for being wrapped around a 1 MHz to 40 MHz crystal, and there
are thousands of designs using this feature.
More recent Xilinx architectures don't have this on-chip circuitry for
the following reasons:

You can buy a complete oscillator can for essentially the same price as
a crystal ( around one dollar in single quantities ). IThe complete
oscillator is only slightly larger than a crystal, and the dedicated
oscillator consumes significantly less power ( Icc ) than the invertyer
on the FPGA.

A canned oscillator keeps the digital designer away from the
high-frequency analog issues of crystal oscillator design, including the
start-up conditions.

Eliminating that inverter avoids exotic analog testing at Xilinx.

It avoids fingerpointing between FPGA and crystal manufacturer when
something does not work reliably. ( "You don't provide enough gain" vs.
"you specified the load capacitance incorrectly".

There have been no complaints from our customer base when we deleted the
crystal oscillator option from the newer architectures, but the option
remains and will remain on the XC3000 and XC3100 family devices, which
will be available for many years to come.

Peter Alfke, Xilinx Applications
Article: 4987
Subject: Re: FAQ
From: "John L. Smith" <jsmith@univision.com>
Date: Wed, 08 Jan 1997 15:13:54 -0800
Links: << >>  << T >>  << A >>
,, , wrote:
> 
> Hi folks!  I'm new to this newsgroup and was wondering if
> some sort of a FAQ exists that I can look up ?
> 
> Thanks a million!
> 
> sudhir

AFAIK, No FAQ, but check out COMP.ARCH.FPGA Archive at

http://www.super.org:8000/FPGA/thread_old.html

for old posts.

-- 
John L. Smith, Pr. Engr.     | Sometimes we are inclined to class
Univision Technologies, Inc. | those who are once-and-a-half witted
6 Fortune Dr.                | with the half-witted, because we
Billerica, MA 01821-3917     | appreciate only a third part of their wit.
jsmith@univision.com         | - Henry David Thoreau
Article: 4988
Subject: Re: What Does ASIC Stand For?
From: bkwilli@smart.net (Bryan Williams)
Date: Wed, 08 Jan 1997 23:54:41 GMT
Links: << >>  << T >>  << A >>
eswar@mega.megamed.com (Subramnyeswar Saladi) wrote:

>John Cooley (jcooley@world.std.com) wrote:
>: simonson@skopen.dseg.ti.com (Kevin M Simonson) writes:
>
>: >     I'm feeling really ignorant right now.  Is there anyone who can tell
>: >me what ASIC stands for?  Thanks.
>: > 
>: >                                     ---Kevin Simonson
>
>: Aren't "ASICs" a brand of tennis shoe?   :^)
>
>Why were the shoes named ASIC's ?
>
We're on a tangent here, but I think it's  Application-Specific
Integrated Cross-training Shoe.

At least that's what my pointy-haired manager told me.
;)
Article: 4989
Subject: Linux version for EDA
From: "Karl W. Pfalzer" <karlp@ez-synthesis.com>
Date: Wed, 08 Jan 1997 16:37:42 -0800
Links: << >>  << T >>  << A >>
Our company is preparing to introduce ASIC synthesis-related
EDA tools for the Linux (x86) platform, in the near future.

To help our planning, please answer the 2 questions below:

1)  Which of the following release(s) of Linux do you
    currently run (or plan on running in the near future) ?

 [ ]  1.1.??
 [ ]  1.2.??
 [ ]  2.0.??
 [ ]  other: _______________ (please specify)


2)  If you use Sun machines; which OS release(s) do you currently run 
    (or plan on running in the near future) ?

 [ ]  SunOS 4.1.??
 [ ]  SunOS 5.4.?? (Solaris 2.4)
 [ ]  SunOS 5.5    (Solaris 2.5)


You can check your OS version by typing "uname -sr" at the Unix prompt.

PLEASE EMAIL US DIRECTLY and we will post the results to these newsgroups, 
in a short while.

Thank you.

-- 
Synthesis Solutions, Inc.
http://www.ez-synthesis.com
vmail: (415) 431-6429
Article: 4990
Subject: Re: Oscillator with PLD's or FPGA's
From: fliptron@netcom.com (Philip Freidin)
Date: Thu, 9 Jan 1997 08:51:40 GMT
Links: << >>  << T >>  << A >>
In article <E3oII7.K8A@nonexistent.com> kardos@mail.matav.hu writes:
>Hi!
>
>   Have anyone ever realized a quartz controlled oscillator with a PLD
>or an FPGA without other IC's ? I know that the simplest oscillator with
>a 74hc04 won't work (the quartz is connected parralel to the inverter),
>but it work's with 74hcu04 because this circuit is unbuffered
>(single-stage inverter).
>   Thx for any ideas !

Sure it works (with both). You may just need to put a resistor in 
parallel with the crystal (20,000,000 ohms), and maybe some capacitors to 
ground on both sides (10 to 20 pF). An easy way to get this right is to 
put the circuit together, and leave out the crystal. It should oscillate 
anyway. Adjust the resistor an capacitor to give an RC oscillator at 
about the frequency of the xtal. then put the xtal back into the circuit.

As for FPGAs, all the Xilinx XC3000, XC3100, XC3000A, and XC3100A devices 
have specifically got an XTAL in and out pin to support an XTAL 
oscillator with no extra ICs.

>
>-- 
>Kardos, Botond  -  at Innomed Medical Co. Ltd. in Hungary
>eMail: kardos@mail.matav.hu
>phone/fax: (36 1) 268-0934

Philip Freidin.

Self starting oscillators that dont, and amplifiers that do :-)


Article: 4991
Subject: Repost: New CAD tools for new Xilinx XC6200 FPGA
From: ludwig@inf.ethz.ch (Stefan Ludwig)
Date: 9 Jan 1997 10:16:41 +0100
Links: << >>  << T >>  << A >>
The first announcement went out just before Christmas. I'm not
sure everyone was able to read it before it expired, hence
the repost.



Announcement of Trianus/Hades tools for Xilinx XC6200 FPGA
==========================================================

The Institute for Computer Systems of ETH Zurich is proud to announce the
first publicly available CAD tool suite for the new Xilinx XC6200 FPGA
architecture.

The Trianus/Hades package was developed using the Oberon System over the past
three years by two graduate students, Stephan Gehring and Stefan Ludwig. It
uses and runs under the Oberon System V4 from the Institute for Computer
Systems, ETH Zurich, Switzerland and the Institute for System Software,
University of Linz, Austria. See the text below for a detailed description of
the capabilities of the CAD software.

Go to http://www-cs.inf.ethz.ch/Wirth/CADTools.html#Trianus for more
information and for downloading instructions or use anonymous ftp to
ftp-cs.inf.ethz.ch and go to directory /pub/Trianus

The development of this software was possible due to the open architecture of
the XC6200. It was not developed by Xilinx, Inc. and is different from their
Camelot software for the XC6200.

We would like to thank Xilinx Scotland and Xilinx San Jose for their
continuing support over the past years, without which the development of this
software would not have been possible.

Comments and criticism is welcomed.

Happy New Year!

Stefan Ludwig, Stephan Gehring

------------------------------------------------------------------------
Stefan H-M Ludwig                         Institute for Computer Systems
mailto:ludwig@inf.ethz.ch                 ETH Zentrum
http://www.inf.ethz.ch/personal/ludwig    CH-8092 Zurich, Switzerland
Phone: +41-1-632 7301                     Fax: +41-1-632 1307




Trianus/Hades by Stephan Gehring/Stefan Ludwig

The Trianus/Hades software system consists of a suite of tightly integrated
tools for the efficient design and implementation of algorithms for a custom
computing machine. The software is built upon a generic framework for FPGA
circuit design and comprises a compiler for the Lola hardware description
language, a layout editor, a circuit checker, a technology mapper, a placer, a
router, and a bit-stream generator and loader for the Xilinx XC6200
architecture. We argue that a tight coupling of design tools provides a base
for fast iterative and interactive circuit design, a feature which current
systems provide only in a very limited form.
The Hades synthesis back-end uses simple, deterministic algorithms, which give
predictable results at high speeds. Typically, compile, place and route times
are under 1 minute on a Pentium-class PC. Hence, it is possible to develop
hardware with the same turnaround times as is common for software
development.


Hardware Description Language Lola by Niklaus Wirth

Lola was designed as a simple, easily learned hardware description language
for describing synchronous, digital circuits. In addition to its use in a
digital design course for second year computer science students at ETH Zurich,
the Institute for Computer Systems uses it as a hardware description language
for describing hardware designs in general and coprocessor applications in
particular. The purpose of Lola is to statically describe the structure and
functionality of hardware components and of the connections between them. A
Lola text is composed of declarations and statements. It describes the
hardware on the gate level in the form of signal assignments. Signals are
combined using operators and assigned to other signals. Signals and the
respective assignments can be grouped together into types. An instance of a
type is a hardware component. Types can be composed of instances of other
types, thereby supporting a hierarchical design style and they can be generic
(e.g. parameterizable with the word-width of a circuit).
Article: 4992
Subject: Re: FAQ
From: Geoffrey Bostock <geoff.bostock@zetnet.co.uk>
Date: Thu, 9 Jan 1997 09:35:20 GMT
Links: << >>  << T >>  << A >>
In message <5b0igk$h2r@Bayou.UH.EDU>
        st7jp@Bayou.UH.EDU (,, ,) writes: 


> Hi folks!  I'm new to this newsgroup and was wondering if
> some sort of a FAQ exists that I can look up ?

> Thanks a million!

> sudhir

If you want a grounding in FPGAs and Programmable Logic you could try my book:-

FPGAs and Programmable LSI - A Designer's Handbook
Published by Newnes (Butterworth Heinemann) - ISBN 0 7506 2883 9

It is not too high-powered but gives (I think!) a good introduction 
to the subject.

Geoff Bostock



Article: 4993
Subject: Re: Linux & EDA at Usenix 97
From: aswhelan@trog.dra.hmg.gb (Al Whelan)
Date: 9 Jan 1997 09:44:45 GMT
Links: << >>  << T >>  << A >>
Peter Collins (peter@exemplar.com) wrote:
: There will be a Birds of a Feather Session on Linux and EDA at
: Usenix 97 in Anaheim on Jan 7 at 7 pm. We'll share
: information on EDA software currently available on Linux, ideas

: If you can't make it, but would like a summary of the
: BOF and further Linux & EDA developments, you can also send email
: to info@linuxeda.com

Any chance you could post a summary here?

--
Al

---------------------------------------------------------

I plan to die like my grandfather, peacefully in his sleep.
Not in screaming terror, like his passengers.
Article: 4994
Subject: Re: Linux & EDA at Usenix 97
From: Uwe Bonnes <bon@elektron.ikp.physik.th-darmstadt.de>
Date: 9 Jan 1997 11:03:40 GMT
Links: << >>  << T >>  << A >>
In comp.lang.verilog Peter Collins <peter@exemplar.com> wrote:
: There will be a Birds of a Feather Session on Linux and EDA at
: Usenix 97 in Anaheim on Jan 7 at 7 pm. We'll share
: information on EDA software currently available on Linux, ideas
: for promoting more support and the current state of LinuxEDA.
: For developers  there will be information on how to support Linux
: from the practical side of third party tools like license servers,
: memory managers and online documentation tools.

Since about one year I try to convince Oliver Bartels
(http://www.bartels.de) to risk a Linux port of his PCB Layout package
BAE. Mr. Bartels argues that he had only about 5 requests for a Linux
version at all, so he doubts real interesst and market chance. If you think
other and have need for a Linux PCB package, please let him know
(obartels@bartels.de).

F.y.i:
Many commercial PCB packages have Mr. Bartels Autorouter Kernel licenced.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.th-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 4995
Subject: DES Keysearch by FPGA: $10,000 prize
From: trei@ziplink.net (Peter Trei)
Date: 9 Jan 1997 16:20:48 -0500
Links: << >>  << T >>  << A >>

RSA Data Security will soon sponsor a 'DES Challenge', in which
participants are asked to attempt to decrypt a message supplied by
RSA. The first person or group to email RSA the correct key and the
decrypted message will receive a $10,000 prize.

I believe that a reconfigurable logic system is a near-ideal candidate
to attack this problem. The winner, aside from the money, will also
gain a great deal of positive publicity. This challenge is acheivable
with a plausible level of time and effort.

This is a 'known plaintext challenge': The first few bytes of the
encrypted message are known, but the key used for encryption, and the
rest of the message, are not. If the key is found, the rest of the
message can be easily decrypted.

There are no restrictions on the mechanisms which can be used to
recover the DES key. The fastest method is probably brute force;
testing each of the 2^56 keys until a match is found.

DES was originally designed for hardware implementation, and is thus
easier to run on a reconfigurable logic system than many later
encryption algorithms.

In 1993, Michael J. Wiener of Bell-Northern Research, published a
paper 'Efficient DES Keysearch', in which he gave a detailed
description of such a keysearch engine, based on custom chips, which
could search the entire keyspace in about 7 hours.

The paper includes a gate-level description of the custom chip, which
can test one key per clock cycle due to a clever pipelined design.

The chip he describes is constructed using 0.8 um CMOS, and contains
26086 gates, spread over 76637 sites. It runs at 50 MHz, testing 50
million keys/sec. By contrast, the best known key search algorithm
capable of running on a Pentium tests about 100,000 keys/sec at that
speed. 

Applying some of the speedups and simplifications learned from the
work done on software search algorithms, I beleive it should be simple
to reduce the site count by about 3600, getting it down to about
73,000 sites. It should also be possible to simplify some of the
wiring. In this mode, the chip would identify 'candidate keys',
roughly one in 2^32, which would then be tested on a general purpose
computer.

I am not conversant with the conventions and constraints of
reconfigurable hardware design. I give this detailed information in
hope that it will enable readers to decide whether their systems are
capable of emulating this chip. Other designs are possible.

Anyone interested? RSA has issued a press release and given out some
example data for testing systems, but still has nothing on their web
site. The actual challenge will be issued during the RSA Data Security
Conference later this month.

Peter Trei (not affiliated with RSA)
trei@process.com
ptrei@acm.org

I append RSA's press release.
------------------------------


RSA Announces New "DES Challenge"

Tens of thousands of dollars in cash prizes offered; contest should 
improve overall Internet security by illustrating relative strength 
of different crypto algorithms and keysizes.

Business Editors and Computer Writers


REDWOOD CITY, Calif.-Jan 2, 1997--RSA Data Security, Inc., a wholly 
owned subsidiary of Security Dynamics Technology, Inc. (NASDAQ: 
SDTI), today announced an Internet-based contest with cash prizes.   
The contest, known as the "RSA DES Challenge", challenges 
mathematicians, hackers and computer experts around the world to 
decipher encrypted messages.  The goal of the contest is to quantify 
the security offered by the government endorsed DES encryption 
standard and other secret-key ciphers at various key sizes.

The challenge proper will be launched during the RSA Data Security 
Conference to be held in San Francisco, January 28-31, with the 
target ciphertexts for the different contests being simultaneously 
posted on the company web-site, at http://www.rsa.com/

RSA Data Security pioneered the Internet-based "cracking" contest, 
when it launched the original "RSA Factoring Challenge" back in 1991.  
Since then, the company has paid out over $100,000 in prize money to 
mathematicians and hackers around the world, and the data gained from 
that Challenge (which is ongoing) has greatly increased 
mathematicians' understanding of the strength of encryption 
techniques based on the "factoring problem", such as the RSA Public 
Key Cryptosystem T.


Background

It's widely agreed that 56-bit keys, such as those offered by the 
government's DES standard, offer marginal protection against the 
committed adversary. By inertia as much as anything else, DES is 
still used for many applications, and the 20-year-old algorithm is 
proposed to be exportable under the latest incarnation of Clipper. It 
is the perfect time to demonstrate to the world that better systems 
are both required - and available - thus improving the world's 
security.

There have been theoretical studies done showing that a specialized 
computer "DES cracker" could be built for a modest sum, which could 
crack keys in mere hours by exhaustive search. However, no one is 
known to have built such a machine in the private sector - and nobody 
knows if one has been built in any government, either.

The successes of the RSA Factoring Challenge show that for some types 
of problems, it's possible to recruit spare "cycles" on a large 
number of machines distributed around the Internet. Therefore, by 
offering a suitable incentive, it should be possible to recruit 
sufficient CPU power across the Internet to exhaustively search the 
DES keyspace in a matter of weeks.

Computer scientists have already developed software that will allow 
even the novice computer user to participate in the cracking effort.  
By incorporating the key search software in a "screen saver", a 
simple PC anywhere on the Internet can devote its spare time to 
working on the problem - remotely and completely unattended.  Even 
people with limited computer skills will be able to participate.  In 
the RSA DES Challenge, the motto will definitely be "The More, The 
Merrier".


The Contest

Full details of the RSA DES Challenge will be posted on the RSA home 
page (http://www.rsa.com/) during the first weeks of January. 
Complete rules for the competition will be provided as well as 
example challenges and solutions against which computer scientists 
and hackers can test their software. 

In conjunction with the RSA DES Challenge, RSA will simultaneously 
launch a series of other contests based around the RC5 Symmetric 
Block Cipher (another encryption algorithm).  Since RC5 is a variable 
key length block cipher, targets that offer increasing resistance 
against so-called "exhaustive search attacks" will be posted in the 
hope of assessing the full impact of a widely-distributed exhaustive 
search. There will be 12 challenges based on the use of RC5. Prizes 
will be awarded for the recovery of each of 12 keys which are chosen 
to be of lengths varying from 40 bits all the way up to 128 bits, 
with the length increasing in steps of eight bits.

The email sender of the first correctly formatted submissions to each 
contest will receive a cash prize. For the RSA DES Challenge the 
first sender of the secret DES key will receive $10,000. For the 
other contests the prize money awarded will vary with the difficulty 
of the RC5 key attacked.

For more information about the ongoing RSA Factoring Challenge send 
email to challenge-administrator@rsa.com and for the latest news and 
developments send email to challenge-news@rsa.com. 


About RSA Data Security, Inc.

RSA Data Security, Inc., a wholly owned subsidiary of Security 
Dynamics Technologies, Inc., is the world's brand name for 
cryptography, with more than 75 million copies of RSA encryption and 
authentication technologies installed and in use worldwide. RSA 
technologies are part of existing and proposed standards for the 
Internet and World Wide Web, IT4, ISO, ANSI, IEEE, and business, 
financial and electronic commerce networks around the globe. The 
company develops and markets platform-independent developer's kits 
and end-user products, and provides comprehensive cryptographic 
consulting services. For more information on any of RSA's encryption 
technologies, please call RSA directly at 415/595-8782 or send 
electronic mail to sales@rsa.com. RSA also provides information on 
its Web site at http://www.rsa.com. 



****************************************************************
Kurt R. Stammberger
Director, Technology Marketing
RSA Data Security, Inc. (A Security Dynamics Company)
415-595-8782 vox           415-595-1873 fax
kurt@rsa.com               www.rsa.com


Article: 4996
Subject: Are you looking for CHIP MANUFACTURER websites ???
From: Gray Creager <gcreager@scruznet.com>
Date: Thu, 09 Jan 1997 13:40:44 -0800
Links: << >>  << T >>  << A >>
Don't be fooled by imitations...

I have been keeping the BEST listing anywhere on the internet for the
past 1 1/2 years and it gets updated frequently. Right now, there are
327 CHIP MANUFACTURER websites listed!

Check it out (brief or verbose versions available) and bookmark it.

http://www.scruznet.com/~gcreager/hello5.htm

--
Gray Creager
Applications Engineer
Xicor, Inc.
http://www.xicor.com
Article: 4997
Subject: would you be my friend?
From: dozer@netwizards.net
Date: Fri, 10 Jan 1997 00:48:03
Links: << >>  << T >>  << A >>
Hello,

I'm 14 years old and I think I may be a gay.  I'm looking for some support and friendship 
with a older male age 18-40.  Please email if you can help.

Article: 4998
Subject: Re: Altera clique
From: Benjamin D Klass <bdk+@andrew.cmu.edu>
Date: Fri, 10 Jan 1997 11:13:41 -0500
Links: << >>  << T >>  << A >>

Mark Adam's suggestion for using the Linked SNF extractor is a good one,
but you can also do multi-chip designs with one project.  The key is not
to "chips" instead of "cliques."

A clique is a strong hint to the compiler that logic should be kept
together, but the compiler can ignore it.  A "chip" forces the compiler
to put certain specified logic in a certain device.  Since you want four
devices, create four chips and assign pins and as much logic as you want
to specify to each chip.  If you leave some logic unassigned, Maxplus2
will automatically divide that logic among the chips.  Also "reserve
resources" can be used to keep utilization within each device down.

I think that Maxplus2 does a pretty good job of paritioning, but pins
created by to tranfer "internal signals" between chips can be a hard to
work with if the design changes.

If you know exactly which logic goes in which chip, the Linked SNF
extractor is probably best.  If you want Maxplus2 to do some of the
paritioning work, use chips.

ben

Article: 4999
Subject: Re: Altera clique
From: waynet@goodnet.com (Wayne Turner)
Date: Fri, 10 Jan 97 16:22:57 GMT
Links: << >>  << T >>  << A >>
Gabby Shpirer wrote:
> 
> Hello Altera people,
> 
> I'm trying to compile an hirarchical design into 4 deferent devices
> 
> with no big success.
> 
> Our design combined from 4 blocks and we tried to put each block into a
> 
> deferent EPM7096LC68-12.
> 
> What we did:
> 
> We had 4 blocks on the top scheme, and with the clique function we
> attached to each block a deferent device.
> At the end of the compilation, the compiler shouts that it didn't use
> one of the devices but the project fit by putting two blocks in one
> device, and that aint what we wanted.
> Please if you can give us more info about partitioning a top design,
> that can be a great help.
> 
> Thanx,
> 
>    Gabby.
> 

You said you used the Clique function.  Did you try the Assign Chip menu 
option?  Grab each block (one at a time) and assign them to a different chip 
(under the Assign -> Pin/Location/Chip menu).  You can assign any block of 
logic to a particular chip this way (the chip you can call what you want; c1, 
c2, etc...).  

Just make sure you make the appropriate interconnections on the board to 
connect them together, if needed.

Wayne


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