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Messages from 26075

Article: 26075
Subject: Re: FPGA Express strikes again! Xilinx response
From: krw@attglobal.net (Keith R. Williams)
Date: Tue, 03 Oct 2000 02:54:11 GMT
Links: << >>  << T >>  << A >>
On Tue, 3 Oct 2000 02:17:24, bob_42690@my-deja.com wrote:

> 
> 
> >
> > P.S.  I'm not threatened by being called an "amateur".  I
> > understood the comment.  I am a relative newbie though (25+ years
> > as a hardware designer, 1+ years doing this *neat* stuff).  Just
> > to be clear, I am also rather new to synthesis (good grief, I've
> > been dreaming *in* VHDL recently), so treat me kindly.  ;-)
> 
> I had a dream that I was debugging a VHDL simulation!  Now that's not
> right.  Must be some type of recursion thing.

Well my dreams were a little more bizare than recursion (though 
as an engineer, recursion is bizare enough).  This was more on 
the lines of:
  
zz_zzz:process (clock, reset, dream)
       variable dreams: actresses;		
       begin
       If    reset = '1'         --  If asynchronous reset
         then eyes <= open;      --    then *Damn*!
       elsif falling_edge(clock) --  If clock broken or not 
morning yet
         then                    --    then
           Snore   <= true;      --      ;-)
           case dreams is        --      Select a dream    
             when Pammela =>     --        When interesting
               ...               --          err, nevermind!

..well you get the idea.  I was dreaming *IN* VHDL.  Ack!  
..and I'm not good at VHDL, either! ;-)

----
  Keith

Article: 26076
Subject: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Phil Hays <spampostmaster@sprynet.com>
Date: Mon, 02 Oct 2000 22:59:31 -0700
Links: << >>  << T >>  << A >>
"Keith R. Williams" wrote:

> ..Amplify is another issue altogether. I'd like some information
> from anyone with experience with it.

I had written a longer response to this, and was cut off by Dr. Watson.  Joy.

I have used Amplify.  I would recommend it if you writing HDL that pushes the
silicon for speed.  Amplify will allow for clock rate improvement by improvement
of mapping and by placement information.  I think it is a good tool.

Amplify fits between a "push the button" type flow and a "I'll put every F-map
in the exact right spot" type flow.  It will get better results (meaning clock
rate) than the first.  It will NOT get better results than the second, however
it takes rather less design effort.

It is a spendy tool, however schedules and buying faster parts mean money as
well.

Questions, ask.


-- 
Phil Hays

Article: 26077
Subject: Re: Coregen
From: Christophe Heyert <heyertc@rsd.bel.alcatel.be>
Date: Tue, 03 Oct 2000 08:46:56 +0200
Links: << >>  << T >>  << A >>
Johan Petersson wrote:
> 
> Hi Christophe,
> 
> What simulator are you using? I have not used coregen RAM, but my wild
> guess
> would be that you have a bug in your simulator :)
> 
> Good luck,
> Johan P :)
> 
> Christophe Heyert wrote:
> >
> > A very strange thing happened to me yesterday. I'm using a RAM block
> > generated by the Coregenerator in
> > my structural design.
> > The first time I didn't have any problems i my behavioral simulation,
> > but the second time the following error appeared.
> >
> > Internal ERROR : Access violation
> >                  Occurred in architecture BEHAVIORAL of entity
> > C_MEM_BLOCK_V1_0 (which is a single port RAM block).
> >
> > Where does this problem come from?
> >
> > christophe



We're using Fusion from Viewlogic, and indeed, sometimes it behaves very
strange.
I simply copied the entire design in a new project directory and the
problem was solved.

christophe

Article: 26078
Subject: Re: Xilinx Demo Board
From: Christophe Heyert <heyertc@rsd.bel.alcatel.be>
Date: Tue, 03 Oct 2000 08:52:10 +0200
Links: << >>  << T >>  << A >>
Qian Zhang wrote:
> 
> Hi Friends
> 
> Here I have Xilinx demo board,
> but I dont know how to use it.
> Where can I find some information?
> 
> Also Who can tell me how to generate bit file
> so that I can download to demo board?
> Thank you very much!
> 
> Qian


Look on the Xilinx website. In the application notes you might find some
info about demo boards.
If you are using Alliance from Xilinx you can either generate the bit
file by setting the configuration option ON in the options. There is
also an icon in the GUI that will generate your bit file.

greetz,
christophe

Article: 26079
Subject: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
From: Nicolas Matringe <nicolas.matringe@ipricot.com>
Date: Tue, 03 Oct 2000 09:45:47 +0200
Links: << >>  << T >>  << A >>
Rick Filipkiewicz a écrit :

> XST, Xilinx's own Verilog & VHDL synth tool, is now just about useable
> since the 3.1i release has a decent-ish manual. It also runs nicely
> from the command line. I'm going to try & benchmark it against
> Synplify fairly soon.

Hi
Tell me about your benchmarking so that I can do it against Leonardo

-- 
Nicolas MATRINGE           IPricot European Headquarters
Conception electronique    16 rue du Moulin des Bruyeres
Tel +33 1 46 67 51 11      F-92400 COURBEVOIE - FRANCE
Fax +33 1 46 67 51 01      http://www.IPricot.com/

Article: 26080
Subject: Re: Programming Cypress Graphics Clock Generator
From: "Sherdyn" <sherdyn@yahoo.com>
Date: Tue, 3 Oct 2000 17:08:49 +0800
Links: << >>  << T >>  << A >>
Hi Steve,

I am quite sure the programming sequence is correct as I have tried with
different output frequencies. The problem arises when I have a divider (even
a divide by 2 circuit) in FPGA.

Below is the divide-by two circuit that I use in VHDL:-

library IEEE;
use IEEE.std_logic_1164.all;

entity clk_div2 is
port(RESETN   : in STD_LOGIC;
        CLK          : in STD_LOGIC;
----------------------------------------------------------------------------
---
        HCLK       : out STD_LOGIC
    );
end clk_div2;

architecture RTL clk_div2 is

signal hclk_sig : STD_LOGIC;

begin

hclk <= hclk_sig;

process(RESETN, clk)
begin
   if RESETN = '0' then
      hclk_sig <= '0';
   elsif (clk'event AND clk = '1') then
      hclk_sig <= NOT hclk_sig;
   end if;
end process;

end RTL;

Any problem on the above??

Sherdyn

Steve Wiseman <steve@steves-house.org.uk> wrote in message
news:39D8D348.D6EF4BC1@steves-house.org.uk...
> Sherdyn wrote:
> >
> > Hi,
> >
> > I have encountered a strange problem with Cypress PLL ICD2061A.
>
> I've used these successfully several times - they're great, but not
> always obvious. Have you used the bitstream generation proglet, or
> hand-cranked the calculations?
> Things I've got wrong in the past:-
> * Bitstream backwards, (the datasheet used to be rather ambigous)
> * non-monotonic serial clock, <- this was the real problem, use a
> fast, fast scope , or a few pF just to take the edge off anyway.
> * looking at the wrong output pin. (D'oh!)
>
> I'd pay good money for one of these devices, in a regular 14-pin
> oscmod case, with a watch LCD and up-down buttons for frequency,
> sometimes, just to see how close to the edge a design is running.
> Only the non-availability of watch LCDs has stopped me doing this
> myself...)
>
> > So what could FPGA causes the PLL not to work well? Jitter or something
> > else. Any clue?
>
> The don't seem too vulnerable to jitter, but I generally never hung
> them off anything other than other oscmods, or used their internal
> crystal drivers.
>
> Good luck -
>
> Steve



Article: 26081
Subject: Re: "Xilinx Adds FPGA Support to Free Web Design Tools"
From: Jerry English <jenglish@planetc.com>
Date: Tue, 03 Oct 2000 08:42:40 -0400
Links: << >>  << T >>  << A >>
Why not post or make available your files so those with other tools can benchmark it also?

Rick Filipkiewicz wrote:

> rickman wrote:
>
> > I also noticed that there are big differences other than just the chips targeted. The existing
> > WebPack does not include FPGA Express synthesis, (not sure about XST, whatever that is) but the
> > press release indicates that it now includes a full HDL capability.
> > --
> >
>
> XST, Xilinx's own Verilog & VHDL synth tool, is now just about useable since the 3.1i release has a
> decent-ish manual. It also runs nicely from the command line. I'm going to try & benchmark it against
> Synplify fairly soon.
>
> Now, Xilinx, how about actually getting some SpartanII's out the door so we can use the new free s/w.


Article: 26082
Subject: JVM processor
From: "Martin Schoeberl" <martin.schoeberl@chello.at>
Date: Tue, 03 Oct 2000 13:00:39 GMT
Links: << >>  << T >>  << A >>
Hi,

I'm thinking about implementing a JVM ( Java Virtual Machine ) processor in
a FPGA.
But I don't want to invent the wheel once more.
Does enyone know if this is done allready?

Thanks
Martin
------------------------------------------------------
    Martin Schoeberl, mailto:martin@good-ear.com
          Need some ear training? Take a look at
           -----> http://www.good-ear.com/ <-----



Article: 26083
Subject: Re: FEC in FPGAs?
From: "Bill Wilkie" <bill.wilkie@xilinx.com>
Date: Tue, 3 Oct 2000 06:59:51 -0700
Links: << >>  << T >>  << A >>
Shahzad,

You identified flexibility as a key advantage of the FPGA solution. FPGAs are also competitive in terms of cost and speed. See http://www.xilinx.com/products/xaw/reed/ for some details on
a Reed-Solomon solution. Similar results are attainable for Viterbi and interleavers.

Another advantage with the FPGA solution is that if you use cores they are usually quickly migrated to new FPGA architectures as they  appear. You can therefore take advantage of higher clock speeds, new I/O voltage standards, etc.

Regards,
Bill.

Article: 26084
Subject: Re: JVM processor
From: "Jan Gray" <jsgray@acm.org>
Date: Tue, 03 Oct 2000 14:49:01 GMT
Links: << >>  << T >>  << A >>
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:XLkC5.64438$zJ5.3129190@news.chello.at...
> Hi,
>
> I'm thinking about implementing a JVM ( Java Virtual Machine ) processor
in
> a FPGA.
> But I don't want to invent the wheel once more.
> Does enyone know if this is done allready?

Here are a couple of Java processor core implementations that I have read
have been run in an FPGA:

Austin Kim (Lucent), Morris Chang (IIT) paper: Designing a Java
Microprocessor Core Using FPGA Technology
http://csl.cs.iit.edu/~java/publication/asic98.html

Advancel Logic Corp. TinyJ
http://www.advancel.com/home.htm

Jedi Technologies JStar
http://www.jeditech.com/jstarwp.html

Derivation Systems LavaCore
http://www.derivation.com/news/pressrelease_06-21-1999.html

Vulcan Moon
http://www.vulcanasic.com/eda.htm

I suspect at least one of the Sun picoJava cores has been synthesized to an
FPGA.  Certainly it had been discussed.

See also www.fpgacpu.org/usenet/java.html.

And someday we'll have an FPGA CPU+SoC implementing (or hosting) a JVM,
hosting an EDA application, with jbits, that emits version n+1 of itself.

Jan Gray
Gray Research LLC
www.fpgacpu.org




Article: 26085
Subject: Re: JVM processor
From: "Jan Gray" <jsgray@acm.org>
Date: Tue, 03 Oct 2000 14:51:51 GMT
Links: << >>  << T >>  << A >>
> See also www.fpgacpu.org/usenet/java.html.
Sorry, make that www.fpgacpu.org/usenet/javaproc.html.

Jan Gray
Gray Research LLC




Article: 26086
Subject: Re: Synthesis failures
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Tue, 03 Oct 2000 09:35:42 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
> 
> This seems very odd that both FPGA Express and Synplify have the same bug that I assume worked
> correctly at one time. It would be hard to imagine that this problem has been there from the start
> and no one noticed it. So how could two vendors develop the same bug at the same time?

Rick,

I've narrowed this down, trying a whole bunch of test cases.  It appears
that Synplify v6.0 has a problem with the falling-edge clock for the
RAM.  If the RAM's clock is rising edge, the falling edge stuff gets
implemented correctly.  If the RAM's clock is falling-edge triggered,
the tool is confused.  Synplicity's tech support knows about this
problem, and apparently it's been fixed in the beta of v6.1.

As for FPGA Express, I *know* that versions 3.3 and earlier had no
problem doing falling-edge clocks, because I did a handful of XC4KE
designs that used 'em, and everything worked fine.  It's v3.4 that has
the problem, at least with SpartanXL, and I have a simple test case that
proves it.  I kept the install of v3.3, or so I thought, but it access
faults every time I try to run it, so I can't test it.

Kudos to Xilinx tech support: I got two e-mails from two different
support engineers last night -- one was at 7:09 pm; the other at 11:06
pm (Arizona time).

-- a
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26087
Subject: Re: Synthesis failures
From: Andy Peters <"apeters <"@> n o a o [.] e d u>
Date: Tue, 03 Oct 2000 09:37:35 -0700
Links: << >>  << T >>  << A >>
rickman wrote:
 
> Are you sure that this is not a new bug. I used both rising and falling
> edge clocks in a VHDL design I did using FPGA Express and Xilinx M1.5
> about two years ago. There were no inverters in any of my clock paths.

Here's the code that demonstrates the clock-inverter bug.  Anyone wanna
run it through FPGA Express v3.3?

library ieee;
use ieee.std_logic_1164.all;

entity digsamp is
    port (
        sysclk   : in  std_logic;  -- master clock
        mreset_l : in  std_logic;  -- global reset
        din      : in  std_logic_vector(15 downto 0);  -- data input
        den      : in  std_logic;  -- an enable
        dout     : out std_logic_vector (15 downto 0));  -- output data
end entity digsamp;

architecture foo of digsamp is
    -- sync input stuff with the clock:
    signal din_s : std_logic_vector (15 downto 0);
    signal den_s : std_logic;

    -- intermediate signals:
    signal din_d : std_logic_vector (15 downto 0);
    signal dout_fe : std_logic_vector (15 downto 0);
    
begin

    syncin: process (sysclk, mreset_l) is
    begin
        if mreset_l = '0' then
            din_s <= (others => '0');
            den_s <= '0';
        elsif rising_edge(sysclk) then
            din_s <= din;
            den_s <= den;
        end if;
    end process syncin;

    -- latch din when enabled:
    latchit: process (sysclk, mreset_l) is
    begin
        if mreset_l = '0' then
            din_d <= (others => '0');
        elsif rising_edge(sysclk) then
            if den_s = '1' then
                din_d <= din_s;
            end if;
        end if;
    end process latchit;

    -- for giggles, delay it by catching it on the falling edge of the
clock:
    invclock: process (sysclk, mreset_l) is
    begin
        if mreset_l = '0' then
            dout_fe <= (others => '0');
        elsif falling_edge(sysclk) then
            dout_fe <= din_d;
        end if;
    end process invclock;

    -- drive out out on the falling edge of the clock:
    outdrive: process (sysclk, mreset_l) is
    begin
        if mreset_l = '0' then
            dout <= (others => '0');
        elsif rising_edge(sysclk) then
            dout <= dout_fe;
        end if;
    end process outdrive;
end architecture foo;


-- 
----------------------------
Andy Peters
Sr. Electrical Engineer
National Optical Astronomy Observatory
950 N Cherry Ave
Tucson, AZ 85719
apeters (at) n o a o [dot] e d u

Article: 26088
Subject: Pwr/Gnd ( again)
From: erika_uk@my-deja.com
Date: Tue, 03 Oct 2000 17:42:43 GMT
Links: << >>  << T >>  << A >>
hey,

Sourcing a GND and VCC was an issue weeks ago in this news group.

Xilinx claims that the Virtex is rich in terms of routing ressources,
so why not source the Pwr and Gnd wires from the IOB?

I know a friend who does so in the xc4k, is it not possible in virtex ?

--Erika


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 26089
Subject: Re: Altera FPGA experts needed
From: steve (Steve Rencontre)
Date: Tue, 3 Oct 2000 18:45 +0100 (BST)
Links: << >>  << T >>  << A >>
In article <NiHB5.7086$1H2.873605@typhoon.tampabay.rr.com>, 
sramirez@deleet.cfl.rr.com (S. Ramirez) wrote:

>      I thought that Altera made "EPLDs" and CPLDs.
>      However, I thought that the Flex 10K/6K families are gate arrays,
> thereby making them an FPGAs, technically.
>      Please correct me if I am wrong.

Altera don't call their Flex devices FPGAs but everyone else does. Are 
they 'really' FPGAs or not? It's an angels-on-pinheads question.

> "Netscape User" <your_email@here.net> wrote in message
> news:39D6C2D8.CE6E3315@here.net...
> > First of all, Altera makes CPLD's not FPGAs...minor technical
> > distinction.  I'm of the belief that recruiters who post technically
> > accurate job listings get better technical candidates!
> >
> > > We are setting up a design center in new delhi, india.
> > >
> > > Pre-IPO company.
> > >
> > > Stock options in US parent company.
> > >
> > > www.forasic.com
> >
> > Have you considered listing your job postings under www.jobtrak.com?
> >
> 
> 
> 


--
Steve Rencontre		http://www.rsn-tech.co.uk
//#include <disclaimer.h>


Article: 26090
Subject: Re: FEC in FPGAs?
From: erika_uk@my-deja.com
Date: Tue, 03 Oct 2000 17:50:27 GMT
Links: << >>  << T >>  << A >>
what about power consumption ? an issue never risen why?
In article <ee6e1ae.0@WebX.sUN8CHnE>,
  "Bill Wilkie" <bill.wilkie@xilinx.com> wrote:
> Shahzad,
>
> You identified flexibility as a key advantage of the FPGA solution.
FPGAs are also competitive in terms of cost and speed. See
http://www.xilinx.com/products/xaw/reed/ for some details on
> a Reed-Solomon solution. Similar results are attainable for Viterbi
and interleavers.
>
> Another advantage with the FPGA solution is that if you use cores
they are usually quickly migrated to new FPGA architectures as they
appear. You can therefore take advantage of higher clock speeds, new
I/O voltage standards, etc.
>
> Regards,
> Bill.
>


Sent via Deja.com http://www.deja.com/
Before you buy.

Article: 26091
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Oct 2000 21:15:47 GMT
Links: << >>  << T >>  << A >>
Personally, I'm not going to spend the $$$ for it.  I've already built a fairly
sizable library of completely placed thingies (technical term for macros), that
will run rings around what amplify will do, plus, it'll work with a customer's
tool suite, and has a better than even shot of being portable across synthesis
tools.  As for the design effort, for first time through it will reduce the
effort, but once you have the widgets made that time is invisible.  If you are
not reusing the pieces (one time designs), then it is fast to just place them in
the floorplanner (xilinx) and be done with it.

Phil Hays wrote:
> 
> "Keith R. Williams" wrote:
> 
> > ..Amplify is another issue altogether. I'd like some information
> > from anyone with experience with it.
> 
> I had written a longer response to this, and was cut off by Dr. Watson.  Joy.
> 
> I have used Amplify.  I would recommend it if you writing HDL that pushes the
> silicon for speed.  Amplify will allow for clock rate improvement by improvement
> of mapping and by placement information.  I think it is a good tool.
> 
> Amplify fits between a "push the button" type flow and a "I'll put every F-map
> in the exact right spot" type flow.  It will get better results (meaning clock
> rate) than the first.  It will NOT get better results than the second, however
> it takes rather less design effort.
> 
> It is a spendy tool, however schedules and buying faster parts mean money as
> well.
> 
> Questions, ask.
> 
> --
> Phil Hays

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26092
Subject: Re: Pwr/Gnd ( again)
From: Ray Andraka <ray@andraka.com>
Date: Tue, 03 Oct 2000 21:19:31 GMT
Links: << >>  << T >>  << A >>
SO you are using up a pin to get your fixed logic '1' or '0' ????  Perhaps from
an unbonded pin...

erika_uk@my-deja.com wrote:
> 
> hey,
> 
> Sourcing a GND and VCC was an issue weeks ago in this news group.
> 
> Xilinx claims that the Virtex is rich in terms of routing ressources,
> so why not source the Pwr and Gnd wires from the IOB?
> 
> I know a friend who does so in the xc4k, is it not possible in virtex ?
> 
> --Erika
> 
> Sent via Deja.com http://www.deja.com/
> Before you buy.

-- 
-Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com  
http://www.andraka.com  or http://www.fpga-guru.com

Article: 26093
Subject: Xilinx Licensing.
From: korthner@inf.furukawa.co.jp
Date: 04 Oct 2000 10:44:34 +0900
Links: << >>  << T >>  << A >>
Okay, now I'm really confused with Xilinx's Licensing.

A few weeks ago, we had the distributor over, pushing the new ISE.

If we pay for the time based license for 3.1i Base, we get the old
GUI, support for up to Virtex '50.  Or we can pay more, get the 'ISE'
version (Which is explained to me as a new GUI, same tools.)
Alternatively, We can get the 'Express', which is full device support,
3.1i synthesis tools, old GUI.  Pay an *additional fee* for the ISE,
and still get full device support, new GUI.

We're using Spartan II / Virtex '150, so we can't use the Base, since
it only supports up to Virtex '50.

All this was last week.

And now, Virtex is going to release all of this for free with the
WebPack?  (Up to the XCV-300, anyways.)  Am I missing something, or
did they not inform my distributor?

Anything that can sort this mess ou is appreciated.

-Kent

Article: 26094
Subject: Re: Xilinx Student Edition 2.1i first impressions
From: Netscape User <your_namel@email_address.net>
Date: Tue, 03 Oct 2000 18:54:52 -0700
Links: << >>  << T >>  << A >>
At $55, who's complaining?  I only wish XSE 2.1i worked out of the box
under Win2000.
So far I can't seem to get the stupid flexlm to see my ethernet card. 
(Everything 
works fine under Win98SE.)

Interestingly enough, the 'demo license' that comes with XSE 2.1i is
identical to
the commercial version of Foundation Express 2.1i (as far as I can
tell.)  The demo-license *appears* to allow the implementation tools to
target any part up to the XCV-1000/1000E!  The included FPGA-express
seems to behave likewise.  The demo-license doesn't support synthesis 
contraints, so of course you would not be able to generate an optimal
design 
placement/routing.  This is all very preliminary, of course, as I
haven't actually
worked through a very large design to test my theory.  

Not that it makes much difference to me, as my workplace has the Xilinx
Foundation Express software (3.1i)  It's nice to know that I ever wanted
do some very large project as a hobby, the Xilinx 2.1i student-edition
will allow it. 

Andy Peters wrote:
> 
> Seems to me that once the "next generation" of Xilinx' tools are
> released, the previous generation becomes the Student Edition.
> 
> What an interesting way to keep selling the old stuff!
> 
> -- a
> ----------------------------
> Andy Peters
> Sr. Electrical Engineer
> National Optical Astronomy Observatory
> 950 N Cherry Ave
> Tucson, AZ 85719
> apeters (at) n o a o [dot] e d u

Article: 26095
Subject: Re: GPIO on AVNET Xilinx FPGA board? any cables?!?
From: Netscape User <your_namel@email_address.net>
Date: Tue, 03 Oct 2000 19:00:51 -0700
Links: << >>  << T >>  << A >>
> > That AMP connector is a board-to-board 0.8mm pitch job, so you will not
> > find a cable that fits it.
> >
> > This sounds like a good time to vent some steam in the direction of
> > whoever designed a prototypng board with a 0.8mm pitch connector on it.
>
> You might try looking in the Samtec catalogue. They have some 0.8 mm stuff that
> might be suitable for a bodge. And you can generally get their stuff within a
> few days or max 5-6 if its a custom special. Contrast AMP and or their distis:
> MOQ = 10-20 GUnits, lead time after your design has qualified for museum
> status.
> 
> Company connector rules after much bitter experience:
> 
> (1) If its not a PC world connector and its not in the Samtec book it doesn't
> get used.
> 
> (2) If a client insists on some AMP special they source it.

***SIGH***

Ok, looks like I'll work something out with the PCI-edge connector on
the AVNET Xilinx board.  The development kit (ADS Xilinx XCV300
Development System) seemed like a great deal, $2495 for Foundation
Express 2.1i software and the FPGA board.  I guess nothing is perfect.

I've had good experience with an Xess XS40-4010XL board, so I may try
one of their Virtex boards.  At least Xess's boards have standard I/O
pin headers on their boards.  Unfortunately, they use the Virtex in
PQ240 package, so "general-purpose I/Os" are very scarce (if you use all
the nice board features like SRAM, RAMDAC, audio codec, video digitizer,
etc.)

Article: 26096
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: krw@attglobal.net (Keith R. Williams)
Date: Wed, 04 Oct 2000 02:19:00 GMT
Links: << >>  << T >>  << A >>
On Tue, 3 Oct 2000 05:59:31, Phil Hays 
<spampostmaster@sprynet.com> wrote:

> "Keith R. Williams" wrote:
> 
> > ..Amplify is another issue altogether. I'd like some information
> > from anyone with experience with it.
> 
> I had written a longer response to this, and was cut off by Dr. Watson.  Joy.
> 
> I have used Amplify.  I would recommend it if you writing HDL that pushes the
> silicon for speed.  Amplify will allow for clock rate improvement by improvement
> of mapping and by placement information.  I think it is a good tool.

Ok, this is goodness.  

> Amplify fits between a "push the button" type flow and a "I'll put every F-map
> in the exact right spot" type flow.  It will get better results (meaning clock
> rate) than the first.  It will NOT get better results than the second, however
> it takes rather less design effort.

Yes, I have some serious speed problems (200MHz in a XCV600E-7). 
The good news is that it's mostly dataflow.  The only 
"arithmetic" is address decoding.  Latency is a problem, but not 
a serious one.  I can reduce stages later.  As I have indicated, 
my problems more of a lack of experience and even a "guru", 
beieve it or not.  I'm learning fast, but it would be a whole lot
faster if I had someone who would admit that they knew VHDL, not 
to mention FPGA design.
 
> It is a spendy tool, however schedules and buying faster parts mean money as
> well.

Exactly.  The cost of sitting me down in a chair is far more than
Amplify.  If I get the damned thing working I'm a hero (or at 
least not waste of manpower), no matter what the cost inbetween. 

> Questions, ask.

I've gone through the Amplify PowerPoint-Ware. ...well, mostly.  
I have many questions, which I really should talk to their FAEs 
about.  ...though since you've volunteered!  ;-)

- I've looked through the flow and it seems that my Synplify 
license is useless, given that I wanted to stay with Virtex (I'm 
still fighting with a SpartanXL, so this isn't a biggie).

- Given the above, and Synplicities wish to move me to -Pro, why?
 Sure, I see some use for -Pro for higher speed designs, but 
doesn't Amplify trump -Pro here.  I don't see the cross.

- How hard is Amplify to learn.  Can I pick it up (they did send 
me the manual) or should I take a *valuable* week off to go to 
their new training?  By the time I get to the left-coast I might 
just as well take their -Pro classes as well.  The Xilinx 
floor-planner has caused me nothing but problems.  Yes, 
self-inflicted I'm quite sure. 

There are many more questions, but I'm about to go dream in VHDL,
again.  Today was not good.

----
  Keith

Article: 26097
Subject: Re: Amplify experience, was: FPGA Express strikes again! Xilinx response
From: Phil Hays <spampostmaster@sprynet.com>
Date: Tue, 03 Oct 2000 20:21:56 -0700
Links: << >>  << T >>  << A >>
Ray Andraka wrote:

> Personally, I'm not going to spend the $$$ for it.  I've already built a fairly
> sizable library of completely placed thingies (technical term for macros), that
> will run rings around what amplify will do, plus, it'll work with a customer's
> tool suite, and has a better than even shot of being portable across synthesis
> tools.

I'm aware of your design style and am not surprised that you don't want to use
Amplify.


> If you are
> not reusing the pieces (one time designs), then it is fast to just place them in
> the floorplanner (xilinx) and be done with it.

Amplify is easier and faster to use than the Xilinx floorplanner and gets better
results.  It is faster to use as you have fewer things to place.  The placement
is stable even if the source changes.  Amplify does a better job of mapping to
logic by using the hints from the block level floorplan.


-- 
Phil Hays

Article: 26098
Subject: Re: Xilinx Licensing.
From: rickman <spamgoeshere4@yahoo.com>
Date: Tue, 03 Oct 2000 23:45:01 -0400
Links: << >>  << T >>  << A >>
Good luck. I have not understood Xilinx licensing since day one. I guess
I understand it when a chip company says they "have" to charge for the
software that you *must* use in order to make use of their chips. I
understand why they give away (nearly) the same software for use by
"students". Maybe I can even understand a motovation for licensing
software for a limited time. 

But I start having problems understanding all the various options and
permutations of their software for different feature sets, range of
chips supported and all the other nonsense involved in trying to figure
out how to get a design done in the least amount of trouble. 

The pricing structure changes so frequently that you could likely make
big bucks not from being able to use their tools, but rather just
understanding the marketing well enough to offer advice on what and how
to buy them!

Kinda like the weather in the northeast. If you don't like it, just wait
a little while... it will change!

At least the new WebPack ISE is a step in the right direction. Does
anyone understand why they are limiting the chips supported? How does
that benefit them as a company?


korthner@inf.furukawa.co.jp wrote:
> 
> Okay, now I'm really confused with Xilinx's Licensing.
> 
> A few weeks ago, we had the distributor over, pushing the new ISE.
> 
> If we pay for the time based license for 3.1i Base, we get the old
> GUI, support for up to Virtex '50.  Or we can pay more, get the 'ISE'
> version (Which is explained to me as a new GUI, same tools.)
> Alternatively, We can get the 'Express', which is full device support,
> 3.1i synthesis tools, old GUI.  Pay an *additional fee* for the ISE,
> and still get full device support, new GUI.
> 
> We're using Spartan II / Virtex '150, so we can't use the Base, since
> it only supports up to Virtex '50.
> 
> All this was last week.
> 
> And now, Virtex is going to release all of this for free with the
> WebPack?  (Up to the XCV-300, anyways.)  Am I missing something, or
> did they not inform my distributor?
> 
> Anything that can sort this mess ou is appreciated.
> 
> -Kent

-- 

Rick "rickman" Collins

rick.collins@XYarius.com

Ignore the reply address. To email me use the above address with the XY
removed.



Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius
4 King Ave
Frederick, MD 21701-3110
301-682-7772 Voice
301-682-7666 FAX

Internet URL http://www.arius.com

Article: 26099
Subject: test
From: "J.L. Mitchell" <polj08012@yahoo.com>
Date: Wed, 04 Oct 2000 03:59:44 GMT
Links: << >>  << T >>  << A >>
test



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