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Messages from 7750

Article: 7750
Subject: HELP: FPGA, MGA, Std. Cell Break-even analysis
From: SRIRAM SRINIVASAN <sriram@umr.edu>
Date: 10 Oct 97 21:10:27 GMT
Links: << >>  << T >>  << A >>
Hi!


	It would be helpful if some one could give me data on costs of 
FPGA, MGA (Masked Gate Arrays) and Std. Cell based ICs to perform a 
break-even analysis.

	Thanx

--Sriram
-----
sriram@umr.edu
Article: 7751
Subject: Thesis on web: Regular Datapaths on FPGAs
From: akoch@ICSI.Berkeley.EDU (Andreas Koch)
Date: 11 Oct 1997 01:00:06 GMT
Links: << >>  << T >>  << A >>
I have put my doctoral thesis ``Regular Datapaths on
Field-Programmable Gate Arrays'' up as

	http://www.icsi.berkeley.edu/~akoch/koch-thesis.pdf.gz

I would be grateful for comments.

Abstract
========
Field-Programmable Gate Arrays (FPGAs) are a recent kind of
programmable logic device.  They allow the implementation of
integrated digital electronic circuits without requiring the complex
optical, chemical and mechanical processes used in a conventional chip
fabrication.  FPGAs can be embedded in traditional system designflows
to perform prototyping and emulation tasks.  In addition, they also
enable novel applications such as configurable computers with hardware
dynamically adaptable to a specific problem.

The growing chip capacity now allows even the implementation of CPUs
and DSPs on single FPGAs.  However, current design automation tools
trace their roots to times of very limited FPGA sizes, and are
primarily optimized for the implementation of random glue logic.  The
wide datapaths common to CPUs and DSPs are only processed with reduced
performance.

This thesis presents Structured Design Implementation (SDI), a suite
of specialized tools coordinated by a common strategy, which aims to
efficiently map even larger regular datapaths to FPGAs.  In all steps,
regularity is preserved whenever possible, or restored after
disruptive operations were required.

The circuits are composed from parametrizable modules providing a
variety of logical, arithmetical and storage functions.  For each
module, multiple target FPGA-specific implementation alternatives may
be generated in both gate-level netlist and layout views.

A floorplanner based on a genetic algorithm is then used to
simultaneously choose an actual implementation from the set of
alternatives for each module, and to arrange the selected module
implementations in a linear placement.  The floorplanning operation
optimizes for short routing delays, high routability, and fit into the
target FPGA.

In addition, the coarse granularity of an FPGA as compared to a gate
array (large logic blocks instead of small transistors as building
blocks) necessitates a compaction phase to avoid inefficiencies. 
Floorplanning takes this into account by grouping modules amenable to
compaction, and prepares for a merging of their functions across
module boundaries.

For each set of compactable modules, structure extraction and
regularity analysis phases search for a common regular bit-sliced
structure across all modules in the set.  The new master-slices thus
discovered are then processed using conventional logic synthesis and
technology mapping techniques, reducing both area and delay over their
pre-compaction levels.

Since the originally generated module layout is invalidated by the
compaction operation, the mapped logic blocks in each compacted
master-slice have to be re-placed in a regular manner.  This
microplacement operation is performance-driven, and optimizes delay,
control signal routing and slice abutment across master-slice
boundaries.  The compacted modules are then reassembled from the
microplaced master-slices according to the structural information
extracted previously.

The result is the efficient mapping of a regular bit-sliced datapath
architecture to a regular bit-sliced layout.  Practical experiments
for Xilinx XC4000 FPGAs show delay reductions of up to 33% as compared
to layouts produced by conventional tools.  The exploitation of
regularity during processing also reduces CAD runtimes by up to 78%.

-- 
Andreas Koch                                  Email  : akoch@icsi.berkeley.edu
International Computer Science Institute      Phone  : (510) 642-4274 182
1947 Center Street, Suite 600                 Phax   : (510) 643-9153
Berkeley, CA 94704-1198, USA                  * PGP key available on request *
-- 
Andreas Koch                                  Email  : akoch@icsi.berkeley.edu
International Computer Science Institute      Phone  : (510) 642-4274 182
1947 Center Street, Suite 600                 Phax   : (510) 643-9153
Berkeley, CA 94704-1198, USA                  * PGP key available on request *
Article: 7752
Subject: Re: How fast can fully pipelined XC4000 logic go?
From: Brad Taylor <Brad.Taylor@xilinx.com>
Date: Fri, 10 Oct 1997 19:51:18 -0700
Links: << >>  << T >>  << A >>
Brian Drummond wrote:

> 
> I understood there was a "tweaked" 3000 series which could be _clocked_
> at around 300 MHz (and achieve quite impressive speeds with real designs
> too) the XC3100A family.
> 
> This still seems (on paper) faster than the 4000XL family ( but of
> course, smaller). Are there any plans to match this sort of performance
> in the XC4000 family?
> 
> - Brian

From some work I have done here at Xilinx, I would say that the
XC4000XL-1 FPGAs are quite a bit faster than the XC3100A-09 for most
applications. In addition the XL is coming out in a new speed grade (the
-09) which will be 10-15% faster. 

Maximum frequency seems to be related it to the register to LUT ratio
and the amount of floorplanning. DSP applications tend to be limited by
the speed of the carry chain. The following table is a gross
generalization, but it might give you some sense of what you can do with
the XL-1.


Type of design             Reg/LUT Floorplanning  XC4000XL-1 Fmax 
--------------------------------------------------------------------
Emulation of ASICs          1:10     multi-chip   8 -  25 MHz
Typical Synthesis design    1:2        none      25 -  50 MHz
Targeted to 4K FPGA         1:1      datapath    50 -  80 MHZ
Handcrafted FPGA            2:1      extensive   80 - 133 MHz
Extreme systolic pipeline  10:1      routing    100 - 300 MHz

 


This XC4000XL-1 data might also be useful for DSP work:

4 cascaded 32 bit adders = 33  MHz
32 bit adder             = 70  MHz
16 bit adder             = 100 MHz
 8 bit adder             = 125 MHz
 1 bit adder             = 200 MHz



Hope this helps 
-
Brad Taylor
Article: 7753
Subject: Re: How fast can fully pipelined XC4000 logic go?
From: Ho Siu Hung <eg_hsh@stu.ust.hk>
Date: Sat, 11 Oct 1997 13:02:03 +0800
Links: << >>  << T >>  << A >>
On 9 Oct 1997, Erik de Castro Lopo wrote:
> I'm in the process of designing something in the 4010XL which is using
> about 98%
> of the CLBs, has about half the CLBs being clocked at 100MHz and is still
> meeting
> all timing constraints. I'm really quite impressed.

How many CLBs between latch may I ask?  I am also doing a project using
4010XL.  Are you using an external clock through a clock pin?  What is the
maximum clock allowed?  Do Xilinx 4000 series support an internal clock
with the clock enable pin tie to outside?
-------------------------------------------------------------------------------
| Best Regards, 	  +--------+   | Campus: eg_hsh@stu.ust.hk	      |
| David Ho		  | ¶ů≤–ļĶ |   |	 cshosh@cs.ust.hk	      |
| Ho Siu Hung		  +--------+   |   	                              |
| University of Science and Technology |    ICQ: 798357                       |
| Computer Engineering Year 3 (CPEG)   =======================================|
-------------------------------------------------------------------------------


Article: 7754
Subject: FPGA News Resource Page
From: "Richard Yu" <twinstar@datainternet.com>
Date: 11 Oct 1997 07:25:34 GMT
Links: << >>  << T >>  << A >>
I remember there is a homepage storing all discussion in this newsgroup but
I have lost its address.  Can someone help me on that?  Is there also a
similar homepage with all previous discussions on VHDL?  Thanx in
advance!!!

Article: 7755
Subject: FPGA News Resource Page
From: "Richard Yu" <twinstar@datainternet.com>
Date: 11 Oct 1997 07:41:05 GMT
Links: << >>  << T >>  << A >>
I remember there is a homepage storing all discussion in this newsgroup but
I have lost its address.  Can someone help me on that?  Is there also a
similar homepage with all previous discussions on VHDL?  Thanx in
advance!!!

Article: 7756
Subject: Re: How fast can fully pipelined XC4000 logic go?
From: brian@shapes.demon.co.uk (Brian Drummond)
Date: Sat, 11 Oct 1997 14:02:44 GMT
Links: << >>  << T >>  << A >>
Christy Looby <clooby@nmrc.ucc.ie> wrote:

>brian@shapes.demon.co.uk (Brian Drummond) writes:

>> I understood there was a "tweaked" 3000 series which could be _clocked_
>> at around 300 MHz (and achieve quite impressive speeds with real designs
>> too) the XC3100A family.
>
>In `Signal Processing at 250MHz using high speed FPGAs', Proc. FPGA'97,
>	pp62-68, B. von Herzen reports a spectral correlator measured
>	at 250MHz using XC3195-09. This is achieved in a timing-by-construction
>	design flow. Indeed clock speeds of 300MHz are possible with 3195.

That really is impressive. Thanks for the reference.

>> Are there any plans to match this sort of performance
>> in the XC4000 family?
>
>The quote in the reference above "..it is faster to travel to the right than
>to the left, and slightly faster to travel down than up...(XC3100) .. Families
>such as the XC4000 do not have this directionality, but are not as fast for
>direct interconnect between neighbours."
>	This indicates the above question is unlikely to have a positive answer.

For current XC4000 series parts, true. But ultimately... ?

- Brian

Article: 7757
Subject: Re: FPGA News Resource Page
From: "Steven K. Knapp" <sknapp@optimagic.com>
Date: 11 Oct 1997 19:21:01 GMT
Links: << >>  << T >>  << A >>
I believe that you are looking for the comp.arch.fpga archive which is at
'http://www.super.org:8000/FPGA/arrive.html'.  However, I understand that
more recent articles are no longer stored there.

The VHDL archive is at
'http://kona.ee.pitt.edu/NewsGroupArchives/comp.lang.vhdl/index.html'.

These newsgroups, their archives, and other related material is available
via The Programmable Logic Jump Station at
'http://www.optimagic.com/newsgroups.html'.

Richard Yu <twinstar@datainternet.com> wrote in article
<01bcd616$eaec23a0$8e8249ca@philip-tsang>...
| I remember there is a homepage storing all discussion in this newsgroup
but
| I have lost its address.  Can someone help me on that?  Is there also a
| similar homepage with all previous discussions on VHDL?  Thanx in
| advance!!!
| 
| 
Article: 7758
Subject: Re: FPGA News Resource Page
From: Jerry Hicks <wghhicks@ix.netcom.com>
Date: Sat, 11 Oct 1997 20:28:54 -0400
Links: << >>  << T >>  << A >>
And don't forget good old http://www.dejanews.com for searches...

;)

J Hicks
jerry_hicks@bigfoot.com
Article: 7759
Subject: Looking for CUPL, PALASM, etc. source
From: Jerry Hicks <wghhicks@ix.netcom.com>
Date: Sat, 11 Oct 1997 20:51:21 -0400
Links: << >>  << T >>  << A >>
Hello All,

I would like to implement ports packages for any compilers available in
source form to be submitted to FreeBSD.

Any links to such would be appreciated.

TIA,

Jerry Hicks
jerry_hicks@bigfoot.com
Article: 7760
Subject: free router for Xilinx 3000?
From: hmoffatt@mail.com (Hamish Moffatt)
Date: 12 Oct 1997 06:10:29 GMT
Links: << >>  << T >>  << A >>
I suppose I would be a bit hopeful in asking if there
was a free place and router for Xilinx XC3000?



thanks,
Hamish

-- 
Hamish Moffatt, StudIEAust              hamish@debian.org, hmoffatt@mail.com
Student, computer science & computer systems engineering.    3rd year, RMIT.
http://hamish.home.ml.org/ (PGP key here)             CPOM: [*****     ] 56%
Your train has been cancelled due to defective government at Spring Street..
Article: 7761
Subject: Re: Looking for CUPL, PALASM, etc. source
From: z80@ds.com (Peter)
Date: Sun, 12 Oct 1997 07:54:46 GMT
Links: << >>  << T >>  << A >>
The original PALASM was written in Fortran (!) and the source was
freely available. This is early 1980s.

I believe it was re-written in C later, but that's all I know.

As for CUPL, I don't think any sources for this were ever in the
public domain. The program itself used to be given away with some
programmers.

Peter.

Return address is invalid to help stop junk mail.
E-mail replies to z80@digiXYZserve.com but
remove the XYZ.
Article: 7762
Subject: design sites
From: "Thielemans - Van Heghe" <robbren@skynet.be>
Date: 12 Oct 1997 10:11:29 GMT
Links: << >>  << T >>  << A >>
Hello,

Apart from the FPGA vendor sites, are there other design sites with
applications available ?
Thanks in advance !
Article: 7763
Subject: Re: design sites
From: Jerry Hicks <wghhicks@ix.netcom.com>
Date: Sun, 12 Oct 1997 16:56:44 -0400
Links: << >>  << T >>  << A >>
Thielemans - Van Heghe wrote:
> 
> Hello,
> 
> Apart from the FPGA vendor sites, are there other design sites with
> applications available ?
> Thanks in advance !

Several people are working to get some of what's available ported to the
various open operating systems (Linux, FreeBSD, etc.)

Not much found yet, anything you might find we would very much like to
hear about (esp. anything in source form).

Hamish Moffatt (hmoffatt@mail.com) is working on ports for Debian/GNU
Linux, I am working on FreeBSD. (jerry_hicks@bigfoot.com).

Ask your vendors what support they give to developers using these
systems.  There is strength in numbers!

Good Luck!

Jerry Hicks.
Article: 7764
Subject: Synopsys, XACT, XC4000: CLB estimates
From: Christian Schaefer <schaefer@ls12.informatik.uni-dortmund.de>
Date: Mon, 13 Oct 1997 16:18:58 +0200
Links: << >>  << T >>  << A >>
Hello,

the Synopsys command "report_fpga" gives some statistics about
CLBs, function generators and flip flops. When we feed the designs
to XACT, they use significantly more CLBs than Synopsys reported.
Additionally, the XACT design statistics gives two values for
CLB utilization: the actual occupied CLBs and the "packed CLBs"
(often significant lower).

What are the relations between Synopsys estimates, XACT "packed
CLBs" and the actual used number of CLBs? The XACT manual says
nothing about "packed CLBs".

Christian.
Article: 7765
Subject: New AT40K FPGA Arch.
From: "Martin Mason" <mtmason@ix.netcom.com>
Date: Mon, 13 Oct 1997 09:30:12 -0700
Links: << >>  << T >>  << A >>
New AT40K DSP FPGA info available at URLs:

Press Release: http://www.atmel.com/atmel/news/19971013.html

White paper: http://www.atmel.com/atmel/acrobat/dsp40k.pdf

Datasheet: http://www.atmel.com/acrobat/doc0896.pdf




Article: 7766
Subject: I looked up Altera in an Italian dictionary.....
From: "Austin Franklin" <dar8kroom@ix.netcom.com>
Date: 13 Oct 1997 19:49:21 GMT
Links: << >>  << T >>  << A >>
This is NOT meant to be any kind of a slander or slight towards Altera...in
fact, I highly respect the company and the people I have worked with from
there.  But...while I was in Italy, for some reason, I decided to look up
the meaning of 'Altera' in an Italian dictionary...and here's exactly what
it read...

Altera - v.t. alter; adulterate; falsify.

Kind of a bummer for Altera....may be they should have done a bit more
research into their name before choosing it....  They probably don't do
much business in Italy, I would guess.

They don't call the Mazda Miata the Miata in Portugal....you might want to
look that one up too!

Austin Franklin
darkroom@ix.netcom.com

Article: 7767
Subject: Atmel's NEW FPGA.
From: "Martin Mason" <mtmason@ix.netcom.com>
Date: Mon, 13 Oct 1997 14:35:30 -0700
Links: << >>  << T >>  << A >>
 New AT40K DSP FPGA info. available at URLs:

White paper: http://www.atmel.com/atmel/acrobat/dsp40k.pdf

Datasheet: http://www.atmel.com/acrobat/doc0896.pdf

N E W S   R E L E A S E
ATMEL'S NEW AT40K SERIES FPGA OFFERS
HIGH SPEED COMPUTING AND FreeRAM(tm)

New AT40K FPGAs With Eight-Sided, Look-up-Table (LUT)-Based Cell
Architecture, 50K Gates and Distributed SRAM Implements 50 MHz Array
Multipliers

SAN JOSE, CA, October 13, 1997....  Atmel Corporation (Nasdaq: ATML)
announced today that it has introduced a new family of fully PCI-compliant,
dynamically reconfigurable AT40K Coprocessor FPGAs.
Ranging in size from 5,000 to 50,000 usable gates, the 5-device AT40K
family of SRAM-based FPGAs features distributed 10ns programmable
synchronous/asynchronous, dual port/single port SRAM.  The devices are
supported by 8 global clocks, CacheLogicģ ability (partially or fully
reconfigurable without loss of data), and automatic component generators.
I/O counts range from 128 to 384, and AT40K devices are available in
industry standard packages ranging from 84-pin PLCC to 475-pin BGA.  All
members of the family can be pin-locked and support both 3V and 5V designs.
The AT40K offers the most efficient, lowest cost FPGA for designs using
SRAM.  This is accomplished with Atmel's innovative, patented distributed
10ns SRAM capability, called "FreeRAM," which allows the RAM to be used
without losing logic resources.  Multiple independent, synchronous or
asynchronous, dual port or single port RAM functions (FIFO, scratch pad,
etc.) can be created using Atmel's macro generator tool.  "Traditional
FPGAs use logic cells for SRAM.  For each block of RAM a customer uses in
such FPGAs, they lose a block of logic.  Other FPGAs incorporate large SRAM
blocks in the array, making them expensive, slower and less flexible for
designs requiring small amounts of distributed RAM," said Joel Rosenberg,
Atmel's Director of FPGA Marketing.  "The AT40K solves the logic versus
SRAM trade-off by placing discrete, 10ns 32x4 SRAM blocks under the
repeater intersections.  Logic and memory can be effectively implemented in
the same relative area of the FPGA, improving system performance and
reducing silicon overhead.  Therefore, Atmel provides a more cost effective
RAM than any other FPGA available,"  Rosenberg concluded.
The AT40K also has architectural features that make it optimal for
computational DSP functions.  Multipliers are the basis of all
high-performance computing applications.  The AT40K's eight-sided,
look-up-table-based cell is optimized for the implementation of large array
multipliers that require no routing and offer exceptionally high
performance. The AT40K's patented 8-sided core cell with direct horizontal,
vertical and diagonal cell-to-cell connections implements ultra fast array
and vector multipliers without using any bussing resources.  Each 4-input
logic cell contains two 3-input look-up tables (LUTs), an upstream AND gate
for multipliers, register, clock and preset and registered or
non-registered internal feedback.  A full-adder can be implemented in each
logic cell.
The AT40K's patented Cache Logic capability and associated QuickChange^Ŕ
design tools enables a large number of design coefficients and variables to
be created and implemented in a very small amount of silicon, enabling vast
improvement in system functionality and speed at much lower cost than
conventional FPGAs.  This is important in DSP applications including
multimedia,  telecom, industrial control, image processing and general
computing.
The AT40K FPGAs are pin-compatible with Xilinx's XC4000 and XC5200 family,
allowing users to upgrade their existing designs to higher speed, lower
cost and power, without having to relayout their boards.   The AT40K
supports pin-locking, enabling faster time-to-market by allowing the system
board to be manufactured prior to final logic implementation.  "The AT40K
I/O pins each have 28 different paths into the array.  Each I/O pin can be
directly connected to any one of three adjacent logic cells on the array
edge or to a multitude of cells in the core," according to Rosenberg.
"This allows multiple logic cells along the edge of the array or in the
core of the array to drive the device I/O pins.  This gives the designer
the unprecedented ability to drive I/O pads from almost anywhere in the
FPGA."
Atmel provides EDA support for both its AT6000 and AT40K Coprocessor FPGAs
through its FPGA Designer 5.0 suite of design tools.  In addition, the tool
has more than 50 automatic component generators that can be used to create
fully-specified, reusable soft  cores of virtually any logic or SRAM
functions.

 These soft cores can be "instantiated" in the VHDL or Verilog functions
from behavioral designs and executes the appropriate component generator to
achieve a fully optimized implementation.
Atmel's design tools provide seamless integration with industry standard
tools from Cadence (Concept/Verilog), Everest, Exemplar, Mentor, OrCAD,
Synario, Veribest and Viewlogic.  Atmel's Automatic Macro Generator tools
are integrated into the synthesis process, enabling push-button synthesis
of high density behavioral designs optimized for speed, area and power
consumption, with no manual intervention.
Pricing, Packaging and Availability - AT40K Coprocessor FPGAs are available
in 84-pin PLCC; 100-pin VQFP; 144-pin TQFP; 160-, 208-, 240-, 304-pin PQFP
and 225-, 352- or 432-BGA and 475-PGA packages.  Pricing for the 20K gate,
8K RAM AT40K20 in an 84-pin PLCC is $44 each in quantities of 1,000 units.
FPGA Designer 5.0 is available now and is priced at $995.

Headquartered in San Jose, California, with principal manufacturing
facilities in Colorado Springs, Colorado and in Rousset, France, Atmel
designs, develops, manufactures, and markets on a worldwide basis Flash,
EEPROMs, and EPROMs, as well as programmable logic, microcontrollers, and
application-specific devices.
Atmel product and financial information can be retrieved from its
Fax-on-Demand service.  In North America call 1-(800) 292-8635.
International, from a fax phone, call 1-(408) 441-0732.  You can send your
request via e-mail to literature@atmel.com or visit Atmel's Web site at
http://www.atmel.com

CacheLogic is a registered trademark of Atmel Corporation.  FreeRAM,
QuickChange and FPGA Designer 5.0 are trademarks of Atmel Corporation.
Terms and product names in this document may be trademarks of others.








Article: 7768
Subject: VHDL Simulation
From: Dean Brown <dvb@logq.com>
Date: Mon, 13 Oct 1997 14:43:58 -0700
Links: << >>  << T >>  << A >>
Has anyone ever used Accolade's PeakVHDL VHDL simulator ?  If so, I'm
curious what your experience with it was, e.g. ease of use, run times,
support of the VHDL language, etc.  Any feedback would be welcome.

Thanks

Dean Brown.
Santa Clara, CA.

Article: 7769
Subject: $$$ NOW
From: phd567@aol.com (PHD567)
Date: 14 Oct 1997 01:04:30 GMT
Links: << >>  << T >>  << A >>
Subject: Whaddya got to lose??
From: phd567@aol.com (PHD567)
Date: Mon, Oct 13, 1997 20:23 EDT
Message-id: <19971014002301.UAA29311@ladder02.news.aol.com>



Yes, I know it's spam, but just consider this before you hit the delete
button:  If you follow this plan and ONLY SIX PEOPLE respond, you'll
break even.  So what have you got to lose???

DO YOU WANT TO MAKE MONEY FAST???

Of course you do, we all do !!! Here's how to do so with little effort,
and, yes IT'S LEGAL.

A little while back, I was browsing these newsgroups, just like you
are now, and came across an article similar to this that said you could
make thousands of dollars within weeks with only an initial investment
of
$6.00! So I thought, "Yeah, right, this must be a scam!", but like most
of
us, I was curious. Like most of us, I kept reading. Anyway, it said that
if
you send $1.00 to each of the 6 names and addresses stated in the
article,
you could make thousands in a very short period of time.  You then place
your
own name and address at the bottom of the list at #6, and post the
article
to
at least 200 newsgroups.(There are about 22,000.)

No catch, that was it.

Even though the investment was a measely $6, I had three questions that
needed to be answered before I could get involved in this sort of thing.

1. IS THIS REALLY LEGAL??

I called a lawyer first.  The lawyer was a little skeptical that I would
actually make any money but he said it WAS LEGAL if I wanted to try it. 
I
told him it sounded a lot like a chain letter but the details of the
system (SEE BELOW) actually made it a legitimate legal business.

2. Would the Post Office be ok with this....I called them:
1-800-725-2161
and they confirmed THIS IS ABSOLUTELY LEGAL! (See Title 18,h sections
1302
NS 1341 of Postal Lottery Laws). This clarifies the program of
collecting
names and addresses for a mailing list.

3. Is this moral?  Well, everyone who sends me a buck has a good chance
of
getting A LOT of money ... a much better chance than buying a lottery
ticket!!!

So, having these questions answered, I invested EXACTLY $7.92 ... six
$1.00 bills and six 32 cent postage stamps ... and boy am I glad I did
!!!

Within 7 days, I started getting money in the mail! I was shocked! I
still
figured it would end soon, and didn't give it another thought. But the
money
just continued coming in. In my first week, I made about $20.00 to
$30.00
dollars. By the end of the second week I had a mad total of $1,000.00
!!!!!
In the third week I had over $10,000.00 and it was still growing. This
is
now
my fourth week and I have made a total of just over $42,000.00 and it's
still
coming in .....

It's certainly worth $6.00 and 6 stamps !!!

So now I'm reposting this so I can make even more money!  The *ONLY*
thing
stopping *ANYONE* from enrichening their own bank account is pure
laziness ! It took me all of 5 MINUTES to print this out, follow the
directions, and begin posting to newsgroups.  It took me a mere 45
minutes to post to over 200 newsgroups.  And for this GRAND TOTAL
investment of $ 7.92 (US) and under ONE HOUR of my time, I have reaped
an incredible amount of money -- like nothing I've ever even heard of
anywhere before !  'Nuff said !

Let me tell you how this works, and most importantly, why it works. 
Also,
make sure you print a copy of this article now, so you can get the
information
off of it when you need it. The process is very simple and consists of
THREE
easy steps.


============
HOW IT WORKS
============

Mail the 6 envelopes to the following addresses:

STEP 1:
------

Get 6 separate pieces of paper and write the following on each
piece of paper:

    PLEASE ADD ME TO YOUR MAILING LIST.
    $1 US DOLLAR PROCESSING FEE IN ENCLOSED.
    
(THIS IS KEY AS THIS IS WHAT MAKES IT LEGAL SINCE YOU ARE PAYING FOR
 AND LATER OFFERING A SERVICE).
 
Now get 6 $1.00 bills and place ONE inside EACH of the 6 pieces of
paper so the bill will not be seen through the envelope to prevent
theft/robbery. Then, place one paper in each of the 6 envelopes and
seal them. You should now have 6 sealed envelopes, each with a piece
of paper stating the above phrase and a U.S. $1.00 bill.


#1   J&D Enterprises
     PO BOX 1717
     NORMAN, OK 73070

#2   THE WINDFALL COMPANY
       PO BOX 298
     ATWOOD, CA 92811-0298

#3   JA Gualtieri
     45-350 Columbia St. W.
     Waterloo, ON, Canada
     N2L 6G3

#4  ASHLE
     347 JAMBOREE
     MANCHESTER, MO 63021

#5  North Shore Designs 2
       330 Edgewater Road
       Pasadena, MD 21122

#6  H.P.
      P.O. Box 421635
      Middletown, OH  45042-7934


STEP 2: Now take the #1 name off the list that you see above, move the
other names up (6 becomes 5, 5 becomes 4, etc...) and add YOUR Name as
number 6 on the list.  (If you want to remain anonymous, put a nickname,
but the address MUST be correct. It, of course, MUST contain your
country, state/district/area, zip code, etc!!! You wouldn't want your
money to fly away, wouldn't you?!?!).

STEP 3: Now post your amended article to at least 200 newsgroups.
Remember, 200 postings is just a guideline. The more you post, the
more money you make!


Don't know HOW to post in the news groups? Well do exactly the
following:

------------------------------------------------------------------------
        HOW TO POST TO NEWSGROUPS FAST WITH YOUR WEB BROWSER:


                The fastest way to post a newsletter:

Highlight and COPY(Ctrl-C) the text of this posted message and
PASTE(Ctrl-V) it into a plain text editor(as Wordpad) and save it.
After you have made the necessary changes that are stated above,
simply COPY(Ctrl-C) and PASTE(Ctrl-V) the text into the message
composition window, after selecting a newsgroup, and post it! (Or
you can attach the file, without writing nothing to the message window.)
------------------------------------------------------------------------

        If you have Netscape Navigator 3.0 do the following:

1. Click on any newsgroup like normal, then click on 'TO NEWS'. This
will bring up a box to type a message in.
2. Leave the newsgroup box like it is, change the subject box to
something flashy, something to catch the eye, as "$$$ NEED CASH $$$?!!
READ HERE!$!$!$" or "$$$!!!MAKE FAST CASH, YOU CAN'T LOSE!!!$$$". Or
you can use my subject title.
3. Now click on 'ATTACHMENTS'. Then click on 'ATTACH FILE'. Find your
file on your Hard Disk(the one you saved from the text editor). Once
you find it, click on it and then click 'OPEN' and 'OK'. You sould now
see
your file name in the attachments box.
4. Now click on 'SEND'/'POST'. You see? Now you just have 199 to
go!!!(Don't worry, it's easy and quick once you get used to it.)

NOTE: All the versions of Netscape Navigator's are similar to each
other, so you'll have no problem to do this if you don't have Netscape
Navigator 3.0.

------------------------------------------------------------------------
                                !QUICK TIP!
             (For Netscape Navigator 3.x and above)

You can post this message to many newsgroups at a time, by simply
selecting a newsgroup near the top of the screen, hold down the SHIFT,
and then select a newsgroup near the bottom of the screen. All of the
newsgroups in/between will be selected. After that, you follow/do the
basic steps, stated below at this letter, except of step #1. You can
go to the page stated below in this letter and click on a newsgroup to
open up the newsgroups window. Once you've done this, in the same window
go
to 'OPTIONS', and then mark 'SHOW ALL NEWSGROUPS' and 'SHOW ALL
MESSAGES'. Now you can see all the newsgroups and you can apply easier
the above tip.
------------------------------------------------------------------------

        If you have MS Internet Explorer do the following:

1. Go to the newsgroups and press 'POST AN ARTICLE'. To the new window
type your headline in the subject area and then click in the large
window below. There either PASTE your letter(which it's been copied
from the text editor), or attach the file which contains it.

2. Then click on 'SEND' or 'OK'. 

NOTE: All versions of MS Internet Explorer are similar to each other,
so you won't have any problem doing this. 


GENERAL NOTES ON POSTING: A nice page where you'll find all the
newsgroups if you want help is http://www.liszt.com/ (When you go to
the home page, click on the link 'Newsgroup Directory'). But I don't
think
you'll have any problem posting because it's very easy once you've
found the newsgroups. All these web browsers are similar. It doesn't
matter
which one you have.(But it makes it very easy if you have Netscape
Navigator 3.0 or later. You may download it from the Internet if you
don't have it.) You just have to remember the basic steps, stated
below.

BASIC STEPS FOR POSTING: 
1. Find a newsgroup and you click on it.
2. You click on 'POST AN/NEW ARTICLE' or 'TO NEWS' or anything else
similar to these.
3. You type your flashy headline in the subject box.
4. Now, either you attach the file containing your amended letter, or
you PASTE the letter.(You have to COPY it from the text editor, of
course, from before.)
5. Finaly, you click on 'SEND' or 'POST' or 'OK', whatever is there.
------------------------------------------------------------------------

**REMEMBER, THE MORE NEWSGROUPS YOU POST IN, THE MORE MONEY YOU
WILL
MAKE!! BUT YOU HAVE TO POST A MINIMUM OF 200**

That's it! You will begin receiving money from around the world within
day's! You may eventually want to rent a P.O.Box due to the large
amount of mail you receive. If you wish to stay anonymous, you can
invent a name to use, as long as the postman will deliver it. 

**JUST MAKE SURE ALL THE ADDRESSES ARE CORRECT.**

=================
Now the WHY part:
=================

Out of 200 postings, say I receive only 5 replies (a very low
example). So then I made $5.00 with my name at #6 on the letter. Now,
each of the 5 persons who just sent me $1.00 make the MINIMUM 200
postings, each with my name at #5 and only 5 persons respond to each of
the original 5, that is another $25.00 for me, now those 25 each make
200 MINIMUM posts with my name at #4 and only 5 replies each, I will
bring in an additional $125.00! Now, those 125 persons turn around and
post the MINIMUM 200 with my name at #3 and only receive 5 replies each,
I will make an additional $626.00! OK, now here is the fun part, each of
those 625 persons post a MINIMUM 200 letters with my name at #2 and they
each only receive 5 replies, that just made me $3,125.00!!! Those 3,125
persons will all deliver this message to 200 newsgroups with my name at
#1 and if still 5 persons per 200 newsgroups react I will receive
$15,625,00! With a original investment of only $6.00! AMAZING!  And as
I said 5 responses is actually VERY LOW! Average is probable 20 to 30!

So lets put those figures at just 15 responses per person. Here is what
you will make:

at #6 $15.00

at #5 $225.00

at #4 $3,375.00

at #3 $50,625.00

at #2 $759,375.00

at #1 $11,390,625.00

When your name is no longer on the list, you just take the latest
posting in the newsgroups, and send out another $6.00 to names on the
list, putting your name at number 6 again. And start posting again.
The thing to remember is, do you realize that thousands of people all
over the world are joining the internet and reading these articles
everyday, JUST LIKE YOU are now!! So can you afford $6.00 and see if
it really works?? I think so... People have said, "what if the plan is
played out and no one sends you the money? So what! What are the chances
of that happening when there are tons of new honest users and new honest
people who are joining the internet and newsgroups everyday and are
willing to give it a try? Estimates are at 20,000 to 50,000 new users,
every day, with thousands of those joining the actual internet.
Remember, 
play FAIRLY and HONESTLY and this will work. You just have to be honest.

** By the way, if you try to deceive people by posting the messages with
your name in the list and not sending the money to the rest of the
people already on the list, you will NOT get as much. Someone I talked
to knew someone who did that and he only made about $150.00, and
that's after seven or eight weeks! Then he sent the 6 $1.00 bills,
people added him to their lists, and in 4-5 weeks he had over $10k. This
is the fairest and most honest way I have ever seen to share the wealth
of the world without costing anything but our time!!! You also may want
to buy mailing and e-mail lists for future dollars.

Make sure you print this article out RIGHT NOW, also. Try to keep a
list of everyone that sends you money and always keep an eye on the
newsgroups to make sure everyone is playing fairly. Remember, HONESTY
IS THE BEST POLICY. You don't need to cheat the basic idea to make the
money!!

GOOD LUCK to all and please play fairly and reap the huge rewards from
this, which is tons of extra CASH.

Please remember to declare your extra income. Thanks once again...














Article: 7770
Subject: Help with School Project
From: Thina Nguyen <thinnguy@lint.cisco.com>
Date: Mon, 13 Oct 1997 18:16:14 -0700
Links: << >>  << T >>  << A >>
My name is Thina Nguyen and I work at Cisco systems.  I'm doing a school 
project on PLDs (FPGAs) and need to interview a few board designers on 
general stuff like price, quality, features, etc.

I would appreciate if you anyone could just answer the two questions at 
the bottom - they should be pretty quick and easy.  

The Altera folks (the company we're analyzing) have narrowed the 
following product/non-product needs that they think are important to 
designers when considering using PLDs - 

The Product needs for PLD customers are:
F1. In system programmability of the device from a host or a on board 
EPROM
F2. Prices that are competitive with Gate Arrays
F3. Availability of devices in a wide range of  logic capacity, register 
counts, on chip RAM, speed grades, pin counts and package types
F4. Low power dissipation

The Non-Product needs for PLD customers are:
F1. Availability of parts on short notice in large volumes delivered to 
the customers assembly house. (Short production lead times)
F2. Excellent Application Engineering support from the factory in using 
the Software Tools. (Consultative sales force)
F3. Supplier reliability (Company credibility)
F4. Availability of consultants and engineers familiar with the device 


(1) Can you please give me an allocation (in percentages) in terms of 
importance of the needs mentioned above when you are deciding between 
PLDs,  FPGAs more specifically.  For example, 

Importance associated with price 	80%
Importance associated with quality	20%

Importance associated with product needs (above) 	35%
Importance associated with non-product needs (above)	65%

Allocate product need to four product features (above)
P Feature 1	10%
P Feature 2	20%
P Feature 3	30%
P Feature 4	40%

Allocate product need to four non-product features (above)	
NP Feature 1	10%
NP Feature 2	20%
NP Feature 3	30%
NP Feature 4	40%

(2) Also, are any of these needs (below) more important to you than the 
ones mentioned above?  And are there any other needs you feel are 
important and not mentioned?

a) ESD protection on inputs/outputs
b) Fast, easy to use Software on a wide range of platforms like PCís and 
workstations with         efficient synthesis and layout
c) Support for industry standard logic design entry methods which 
include hardware description         languages like VHDL and Verilog
d) Easy fit with the customerís CAD methodology
e) Easy fit into the customerís manufacturing flow when it comes to 
programming the device
f) Availability of Software cores that allow design reuse and improve 
productivity

Thanks for your help!
Regards,
Thina
Article: 7771
Subject: Re: FPGA based CPU ideas, and novel extensions => distributed RAM and Altera CPUs
From: "Jan Gray" <jsgray@acm.org.nospam>
Date: Tue, 14 Oct 1997 00:15:40 -0700
Links: << >>  << T >>  << A >>
David Atkins wrote in message ...
>Any of these kicking around for Altera, if not for a good reason, ?
>Somehting of an interest but not in aposition to find the time for the
>money to get into, we use 10k10's at present and the techniques would be
>intersting, any pointer greatfully recieved.


(Disclaimer: I have studied but never used Altera devices.)

FPGA RISC CPUs, e.g. CPUs with adequate register files, can certainly be
implemented in the Altera FLEX 10K family, which has many nice features.
However, in my opinion, the Xilinx XC4000 architecture seems a better
platform (higher performance) for this application because of its
distributed RAM feature.  In particular, a simple RISC datapath benefits
from a 2-read, 1-write port register file.  In an XC4000, these can (in
theory) be built and run at up to about 10 ns/cycle using two banks of dual
port mode distributed RAM.  [tWCTS=9.0, 8.4, 7.7 ns in XC4000XL-3, -2, -1].
Of course to take advantage of this 66-100 MHz operation you need the deeply
pipelined even/odd ALUs I described in another recent posting.

In contrast, in a FLEX 10K device, you would use EABs (the 256x8 embedded
RAM blocks).  A 32x32 2-read 1-write register file would then require 3
cycles using 4 EABs, or 2 cycles using 8 EABs (two copies of the register
file), at (in theory) 10+ ns/cycle.  [tEAWRCREG and tEARCREG=11.6, 9.5 ns in
EPF10K50V-4, -3].  (Perhaps an Altera expert will provide more correct and
up-to-date information.)  Of course, an accumulator or stack oriented
instruction set architecture (with TOS in a register) could reduce the
average number of EAB accesses per cycle.

EABs could certainly excel at building LARGE register files (e.g. for vector
registers or multiple thread contexts or register windows), on-chip RAM,
ROM, caches, TLBs, cache tag RAMs for off-chip caches, etc.  Indeed an AMD
29000 style variable sized register window implementation might avoid enough
memory traffic to outperform a simpler 32-register RISC with half the cycle
time.  Might not.

Alas, compared to distributed RAM, EABs are often too narrow (256x8 instead
of 128x16) and coarse.  Take a simple I-cache design.  A (256 byte) 16-entry
by 4-word line by 32-bit I-cache in an XC4000 is one column of 16 CLBs for a
16x24 cache tag RAM, one column for a tag comparator and other control
logic, and four columns for a 4x16x32 cache data RAM.  Total approximately
6x16 CLBs, 10% of a 4025E, 3% of a XC4085XL.  A (512 byte) 2-way set assoc,
32-entry cache would be about 200 CLBs, still a small percentage of a large
device.  Whereas the smallest such 32-bit cache you can build from EABs is 4
EABs (both tags and data in same EABs) with two cycle cache access .  4 EABs
is 33% of the EAB resources in a 10K100.

Another feature XC4000 has but which FLEX10K lacks is TBUFs (3-state
drivers).  These are very handy for sharing one wide bus across chip.  In
the old J32 design, the processor half of the XC4010 uses almost every
available TBUF to drive many different results onto the "result bus",
destined for write-back into the register file:
* adder/subtractor
* logic unit
* operand A << 1, << 2, << 4, >> 1, >> 2, >> 4
* data-in (byte, halfword, word)
* sign extension of word/byte data-in for lbu/lbs/lhu/lhs
* next-PC (for jal (jump-and-link)) to save the next-PC into a register
* data-out during the first cycle of store instructions (not written back)

and the 32-bit on-chip data bus half of the XC4010 uses TBUFs for:
* various peripherals and boot ROM to return read data
* driving off-chip data-in onto the on-chip bus
* bus byte-lane shifting -- for instance for "lbu r1,3(r0)" (load byte
unsigned from address 3), we move data on mem.d[31:24] down to mem.d[7:0]

On the other hand, even the 10K10 provides an astonishing 3x144 FastTrack
row channels, so it seems straightforward to deliver even eight or ten
32-bit possible results to multiplexors implemented in LABs.

Assuming each EAB/row is responsible for 8 bits of the processor, a 10K10
might implement a splendid 16- or 24-bit RISC.  Furthermore you can always
implement a 32-bit processor with an 8- or 16-bit datapath, if you perform
several execute cycles per instruction.

Jan Gray


Article: 7772
Subject: Re: VHDL Simulation
From: ees1ht@ee.surrey.ac.uk (Hans)
Date: 14 Oct 1997 08:09:31 GMT
Links: << >>  << T >>  << A >>
In article <3442961D.633DF4A8@logq.com>, dvb@logq.com says...
>
>Has anyone ever used Accolade's PeakVHDL VHDL simulator ?  If so, I'm
>curious what your experience with it was, e.g. ease of use, run times,
>support of the VHDL language, etc.  Any feedback would be welcome.
>
>Thanks
>
>Dean Brown.
>Santa Clara, CA.
>
My experience with PeakVHDL for educational purposes is that itís great! I 
donít think you can find a better VHDL simulator for that price. I have no 
experience in using the simulator on a commercial product though.

Look at their support web page and you will find that they update the simulator 
nearly every week (8Mbyte!). There were some postings in the past about 
stability problems, however, it never crashed on my machine under NT4. Last 
week I extracted a timed VHDL file from Altera's Max2Plus and ran it through 
PeakVHDL without a  problem. Obviously there are some bugs but so far I haven't 
found a serious one. If you do find a bug, email it to them and they will 
probably have a patch the following day. 


Good luck,
Hans.


Article: 7773
Subject: Synopsys: OPT-906
From: Christian Schaefer <schaefer@ls12.informatik.uni-dortmund.de>
Date: Tue, 14 Oct 1997 12:21:04 +0200
Links: << >>  << T >>  << A >>
Hello,

I have just another question: We tried to write and read back designs in
VHDL-format on CLB-level. Synopsys gives error OPT-906 after reading
back the design:

"Currently, FPGA designs created by compile
that contain programmable cells can be saved only in DB
format."

Is there a newer version than 3.4a that already has the capability to
read back designs with CLB cells in VHDL format?

Thanks in advance,
Christian.
Article: 7774
Subject: viewlogic question
From: "Rich K." <rich.katz-nospam@gsfc.nasa.gov>
Date: 14 Oct 1997 10:48:41 GMT
Links: << >>  << T >>  << A >>
hi guys and gals,

this might be a bit off topic and i hope that the net-religious-zealots
don't get too upset.

anyways,

i imagine that there a lot of viewlogic users out there.  what we would
like to do is to be able to attach something to a pin of a component (that
is not used) which will tell the pcb netlister that the pin is
intentionally not used and not to complain about it.  getting a billion pin
unconnected messages is sort of useless and very time consuming to
disposition each one - i'd rather once deliberately put on the schematic my
intention not to use a pin - then the netlister will complain about real
mistakes.  also, it shouldn't affect simulation nor should it appear in the
netlist.  i know that orcad has the little 'x' you attach which does this. 
is there a way to do this in viewlogic?

currently we are adding nets to the pins and labelling them all 'nc' and
then manually going into the netlist to remove the 'nc' net.

any better ideas?

thanks for the help,
 
------------------------------------------------------------
rk
"there's nothing like real data to screw up a great theory,"
- me, modified from the slightly more colorful original
------------------------------------------------------------


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